execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         -- Non-zero to enable log data collection
  17         LOG_LENGTH : natural := 0
  18         );
  19     port (
  20         clk   : in std_ulogic;
  21         rst   : in std_ulogic;
  22
  23         -- asynchronous
  24         flush_out : out std_ulogic;
  25         busy_out : out std_ulogic;
  26
  27         e_in  : in Decode2ToExecute1Type;
  28         l_in  : in Loadstore1ToExecute1Type;
  29
  30         ext_irq_in : std_ulogic;
  31
  32         -- asynchronous
  33         l_out : out Execute1ToLoadstore1Type;
  34         f_out : out Execute1ToFetch1Type;
  35
  36         e_out : out Execute1ToWritebackType;
  37
  38         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  39
  40         icache_inval : out std_ulogic;
  41         terminate_out : out std_ulogic;
  42
  43         log_out : out std_ulogic_vector(14 downto 0);
  44         log_rd_addr : out std_ulogic_vector(31 downto 0);
  45         log_rd_data : in std_ulogic_vector(63 downto 0);
  46         log_wr_addr : in std_ulogic_vector(31 downto 0)
  47         );
  48 end entity execute1;
  49
  50 architecture behaviour of execute1 is
  51     type reg_type is record
  52         e : Execute1ToWritebackType;
  53         f : Execute1ToFetch1Type;
  54         busy: std_ulogic;
  55         terminate: std_ulogic;
  56         lr_update : std_ulogic;
  57         next_lr : std_ulogic_vector(63 downto 0);
  58         mul_in_progress : std_ulogic;
  59         mul_finish : std_ulogic;
  60         div_in_progress : std_ulogic;
  61         cntz_in_progress : std_ulogic;
  62         slow_op_insn : insn_type_t;
  63         slow_op_dest : gpr_index_t;
  64         slow_op_rc : std_ulogic;
  65         slow_op_oe : std_ulogic;
  66         slow_op_xerc : xer_common_t;
  67         last_nia : std_ulogic_vector(63 downto 0);
  68         log_addr_spr : std_ulogic_vector(31 downto 0);
  69     end record;
  70     constant reg_type_init : reg_type :=
  71         (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
  72          busy => '0', lr_update => '0', terminate => '0',
  73          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  74          slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  75          next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
  76
  77     signal r, rin : reg_type;
  78
  79     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  80     signal cr_in : std_ulogic_vector(31 downto 0);
  81
  82     signal valid_in : std_ulogic;
  83     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  84     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  85     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  86     signal rot_sign_ext: std_ulogic;
  87     signal rotator_result: std_ulogic_vector(63 downto 0);
  88     signal rotator_carry: std_ulogic;
  89     signal logical_result: std_ulogic_vector(63 downto 0);
  90     signal countzero_result: std_ulogic_vector(63 downto 0);
  91
  92     -- multiply signals
  93     signal x_to_multiply: MultiplyInputType;
  94     signal multiply_to_x: MultiplyOutputType;
  95
  96     -- divider signals
  97     signal x_to_divider: Execute1ToDividerType;
  98     signal divider_to_x: DividerToExecute1Type;
  99
 100     -- signals for logging
 101     signal exception_log : std_ulogic;
 102     signal irq_valid_log : std_ulogic;
 103
 104     type privilege_level is (USER, SUPER);
 105     type op_privilege_array is array(insn_type_t) of privilege_level;
 106     constant op_privilege: op_privilege_array := (
 107         OP_ATTN => SUPER,
 108         OP_MFMSR => SUPER,
 109         OP_MTMSRD => SUPER,
 110         OP_RFID => SUPER,
 111         OP_TLBIE => SUPER,
 112         others => USER
 113         );
 114
 115     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 116         return boolean is
 117     begin
 118         if op_privilege(op) = SUPER then
 119             return true;
 120         elsif op = OP_MFSPR or op = OP_MTSPR then
 121             return insn(20) = '1';
 122         else
 123             return false;
 124         end if;
 125     end;
 126
 127     procedure set_carry(e: inout Execute1ToWritebackType;
 128                         carry32 : in std_ulogic;
 129                         carry : in std_ulogic) is
 130     begin
 131         e.xerc.ca32 := carry32;
 132         e.xerc.ca := carry;
 133         e.write_xerc_enable := '1';
 134     end;
 135
 136     procedure set_ov(e: inout Execute1ToWritebackType;
 137                      ov   : in std_ulogic;
 138                      ov32 : in std_ulogic) is
 139     begin
 140         e.xerc.ov32 := ov32;
 141         e.xerc.ov := ov;
 142         if ov = '1' then
 143             e.xerc.so := '1';
 144         end if;
 145         e.write_xerc_enable := '1';
 146     end;
 147
 148     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 149                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 150     begin
 151         return (ca xor msb_r) and not (msb_a xor msb_b);
 152     end;
 153
 154     function decode_input_carry(ic : carry_in_t;
 155                                 xerc : xer_common_t) return std_ulogic is
 156     begin
 157         case ic is
 158         when ZERO =>
 159             return '0';
 160         when CA =>
 161             return xerc.ca;
 162         when ONE =>
 163             return '1';
 164         end case;
 165     end;
 166
 167     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 168         return std_ulogic_vector is
 169         variable msr_out: std_ulogic_vector(63 downto 0);
 170     begin
 171         -- ISA says this:
 172         --  Defined MSR bits are classified as either full func-
 173         --  tion or partial function. Full function MSR bits are
 174         --  saved in SRR1 or HSRR1 when an interrupt other
 175         --  than a System Call Vectored interrupt occurs and
 176         --  restored by rfscv, rfid, or hrfid, while partial func-
 177         --  tion MSR bits are not saved or restored.
 178         --  Full function MSR bits lie in the range 0:32, 37:41, and
 179         --  48:63, and partial function MSR bits lie in the range
 180         --  33:36 and 42:47. (Note this is IBM bit numbering).
 181         msr_out := (others => '0');
 182         msr_out(63 downto 31) := msr(63 downto 31);
 183         msr_out(26 downto 22) := msr(26 downto 22);
 184         msr_out(15 downto 0)  := msr(15 downto 0);
 185         return msr_out;
 186     end;
 187
 188 begin
 189
 190     rotator_0: entity work.rotator
 191         port map (
 192             rs => c_in,
 193             ra => a_in,
 194             shift => b_in(6 downto 0),
 195             insn => e_in.insn,
 196             is_32bit => e_in.is_32bit,
 197             right_shift => right_shift,
 198             arith => e_in.is_signed,
 199             clear_left => rot_clear_left,
 200             clear_right => rot_clear_right,
 201             sign_ext_rs => rot_sign_ext,
 202             result => rotator_result,
 203             carry_out => rotator_carry
 204             );
 205
 206     logical_0: entity work.logical
 207         port map (
 208             rs => c_in,
 209             rb => b_in,
 210             op => e_in.insn_type,
 211             invert_in => e_in.invert_a,
 212             invert_out => e_in.invert_out,
 213             result => logical_result,
 214             datalen => e_in.data_len
 215             );
 216
 217     countzero_0: entity work.zero_counter
 218         port map (
 219             clk => clk,
 220             rs => c_in,
 221             count_right => e_in.insn(10),
 222             is_32bit => e_in.is_32bit,
 223             result => countzero_result
 224             );
 225
 226     multiply_0: entity work.multiply
 227         port map (
 228             clk => clk,
 229             m_in => x_to_multiply,
 230             m_out => multiply_to_x
 231             );
 232
 233     divider_0: entity work.divider
 234         port map (
 235             clk => clk,
 236             rst => rst,
 237             d_in => x_to_divider,
 238             d_out => divider_to_x
 239             );
 240
 241     dbg_msr_out <= ctrl.msr;
 242     log_rd_addr <= r.log_addr_spr;
 243
 244     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 245     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 246     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 247
 248     busy_out <= l_in.busy or r.busy;
 249     valid_in <= e_in.valid and not busy_out;
 250
 251     terminate_out <= r.terminate;
 252
 253     execute1_0: process(clk)
 254     begin
 255         if rising_edge(clk) then
 256             if rst = '1' then
 257                 r <= reg_type_init;
 258                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 259                 ctrl.irq_state <= WRITE_SRR0;
 260             else
 261                 r <= rin;
 262                 ctrl <= ctrl_tmp;
 263                 assert not (r.lr_update = '1' and valid_in = '1')
 264                     report "LR update collision with valid in EX1"
 265                     severity failure;
 266                 if r.lr_update = '1' then
 267                     report "LR update to " & to_hstring(r.next_lr);
 268                 end if;
 269             end if;
 270         end if;
 271     end process;
 272
 273     execute1_1: process(all)
 274         variable v : reg_type;
 275         variable a_inv : std_ulogic_vector(63 downto 0);
 276         variable result : std_ulogic_vector(63 downto 0);
 277         variable newcrf : std_ulogic_vector(3 downto 0);
 278         variable result_with_carry : std_ulogic_vector(64 downto 0);
 279         variable result_en : std_ulogic;
 280         variable crnum : crnum_t;
 281         variable crbit : integer range 0 to 31;
 282         variable scrnum : crnum_t;
 283         variable lo, hi : integer;
 284         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 285         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 286         variable bo, bi : std_ulogic_vector(4 downto 0);
 287         variable bf, bfa : std_ulogic_vector(2 downto 0);
 288         variable cr_op : std_ulogic_vector(9 downto 0);
 289         variable cr_operands : std_ulogic_vector(1 downto 0);
 290         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 291         variable btnum, banum, bbnum : integer range 0 to 31;
 292         variable crresult : std_ulogic;
 293         variable l : std_ulogic;
 294         variable next_nia : std_ulogic_vector(63 downto 0);
 295         variable carry_32, carry_64 : std_ulogic;
 296         variable sign1, sign2 : std_ulogic;
 297         variable abs1, abs2 : signed(63 downto 0);
 298         variable overflow : std_ulogic;
 299         variable zerohi, zerolo : std_ulogic;
 300         variable msb_a, msb_b : std_ulogic;
 301         variable a_lt : std_ulogic;
 302         variable lv : Execute1ToLoadstore1Type;
 303         variable irq_valid : std_ulogic;
 304         variable exception : std_ulogic;
 305         variable exception_nextpc : std_ulogic;
 306         variable trapval : std_ulogic_vector(4 downto 0);
 307         variable illegal : std_ulogic;
 308         variable is_branch : std_ulogic;
 309         variable taken_branch : std_ulogic;
 310         variable abs_branch : std_ulogic;
 311         variable spr_val : std_ulogic_vector(63 downto 0);
 312     begin
 313         result := (others => '0');
 314         result_with_carry := (others => '0');
 315         result_en := '0';
 316         newcrf := (others => '0');
 317         is_branch := '0';
 318         taken_branch := '0';
 319         abs_branch := '0';
 320
 321         v := r;
 322         v.e := Execute1ToWritebackInit;
 323         lv := Execute1ToLoadstore1Init;
 324         v.f.redirect := '0';
 325
 326         -- XER forwarding. To avoid having to track XER hazards, we
 327         -- use the previously latched value.
 328         --
 329         -- If the XER was modified by a multiply or a divide, those are
 330         -- single issue, we'll get the up to date value from decode2 from
 331         -- the register file.
 332         --
 333         -- If it was modified by an instruction older than the previous
 334         -- one in EX1, it will have also hit writeback and will be up
 335         -- to date in decode2.
 336         --
 337         -- That leaves us with the case where it was updated by the previous
 338         -- instruction in EX1. In that case, we can forward it back here.
 339         --
 340         -- This will break if we allow pipelining of multiply and divide,
 341         -- but ideally, those should go via EX1 anyway and run as a state
 342         -- machine from here.
 343         --
 344         -- One additional hazard to beware of is an XER:SO modifying instruction
 345         -- in EX1 followed immediately by a store conditional. Due to our
 346         -- writeback latency, the store will go down the LSU with the previous
 347         -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
 348         --
 349         -- We will need to handle that if we ever make stcx. not single issue
 350         --
 351         -- We always pass a valid XER value downto writeback even when
 352         -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
 353         -- to work for RC instructions.
 354         --
 355         if r.e.write_xerc_enable = '1' then
 356             v.e.xerc := r.e.xerc;
 357         else
 358             v.e.xerc := e_in.xerc;
 359         end if;
 360
 361         -- CR forwarding
 362         cr_in <= e_in.cr;
 363         if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
 364             for i in 0 to 7 loop
 365                 if r.e.write_cr_mask(i) = '1' then
 366                     cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
 367                 end if;
 368             end loop;
 369         end if;
 370
 371         v.lr_update := '0';
 372         v.mul_in_progress := '0';
 373         v.div_in_progress := '0';
 374         v.cntz_in_progress := '0';
 375         v.mul_finish := '0';
 376
 377         -- signals to multiply and divide units
 378         sign1 := '0';
 379         sign2 := '0';
 380         if e_in.is_signed = '1' then
 381             if e_in.is_32bit = '1' then
 382                 sign1 := a_in(31);
 383                 sign2 := b_in(31);
 384             else
 385                 sign1 := a_in(63);
 386                 sign2 := b_in(63);
 387             end if;
 388         end if;
 389         -- take absolute values
 390         if sign1 = '0' then
 391             abs1 := signed(a_in);
 392         else
 393             abs1 := - signed(a_in);
 394         end if;
 395         if sign2 = '0' then
 396             abs2 := signed(b_in);
 397         else
 398             abs2 := - signed(b_in);
 399         end if;
 400
 401         x_to_multiply <= MultiplyInputInit;
 402         x_to_multiply.is_32bit <= e_in.is_32bit;
 403
 404         x_to_divider <= Execute1ToDividerInit;
 405         x_to_divider.is_signed <= e_in.is_signed;
 406         x_to_divider.is_32bit <= e_in.is_32bit;
 407         if e_in.insn_type = OP_MOD then
 408             x_to_divider.is_modulus <= '1';
 409         end if;
 410
 411         x_to_multiply.not_result <= sign1 xor sign2;
 412         x_to_multiply.addend <= (others => sign1 xor sign2);
 413         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 414         if e_in.is_32bit = '0' then
 415             -- 64-bit forms
 416             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 417             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 418             if e_in.insn_type = OP_DIVE then
 419                 x_to_divider.is_extended <= '1';
 420             end if;
 421             x_to_divider.dividend <= std_ulogic_vector(abs1);
 422             x_to_divider.divisor <= std_ulogic_vector(abs2);
 423         else
 424             -- 32-bit forms
 425             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 426             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 427             x_to_divider.is_extended <= '0';
 428             if e_in.insn_type = OP_DIVE then   -- extended forms
 429                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 430             else
 431                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 432             end if;
 433             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 434         end if;
 435
 436         ctrl_tmp <= ctrl;
 437         -- FIXME: run at 512MHz not core freq
 438         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 439         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 440
 441         irq_valid := '0';
 442         if ctrl.msr(MSR_EE) = '1' then
 443             if ctrl.dec(63) = '1' then
 444                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
 445                 report "IRQ valid: DEC";
 446                 irq_valid := '1';
 447             elsif ext_irq_in = '1' then
 448                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#500#, 64));
 449                 report "IRQ valid: External";
 450                 irq_valid := '1';
 451             end if;
 452         end if;
 453
 454         v.terminate := '0';
 455         icache_inval <= '0';
 456         v.busy := '0';
 457         -- send MSR[IR] and ~MSR[PR] up to fetch1
 458         v.f.virt_mode := ctrl.msr(MSR_IR);
 459         v.f.priv_mode := not ctrl.msr(MSR_PR);
 460
 461         -- Next insn adder used in a couple of places
 462         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 463
 464         -- rotator control signals
 465         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 466         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 467         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 468         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 469
 470         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 471         ctrl_tmp.irq_state <= WRITE_SRR0;
 472         exception := '0';
 473         illegal := '0';
 474         exception_nextpc := '0';
 475         v.e.exc_write_enable := '0';
 476         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 477         v.e.exc_write_data := e_in.nia;
 478         if valid_in = '1' then
 479             v.last_nia := e_in.nia;
 480         end if;
 481
 482         if ctrl.irq_state = WRITE_SRR1 then
 483             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 484             v.e.exc_write_data := ctrl.srr1;
 485             v.e.exc_write_enable := '1';
 486             ctrl_tmp.msr(MSR_SF) <= '1';
 487             ctrl_tmp.msr(MSR_EE) <= '0';
 488             ctrl_tmp.msr(MSR_PR) <= '0';
 489             ctrl_tmp.msr(MSR_IR) <= '0';
 490             ctrl_tmp.msr(MSR_DR) <= '0';
 491             ctrl_tmp.msr(MSR_RI) <= '0';
 492             ctrl_tmp.msr(MSR_LE) <= '1';
 493             v.e.valid := '1';
 494             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 495
 496         elsif irq_valid = '1' and valid_in = '1' then
 497             -- we need two cycles to write srr0 and 1
 498             -- will need more when we have to write HEIR
 499             -- Don't deliver the interrupt until we have a valid instruction
 500             -- coming in, so we have a valid NIA to put in SRR0.
 501             exception := '1';
 502
 503         elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
 504             instr_is_privileged(e_in.insn_type, e_in.insn) then
 505             -- generate a program interrupt
 506             exception := '1';
 507             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 508             -- set bit 45 to indicate privileged instruction type interrupt
 509             ctrl_tmp.srr1(63 - 45) <= '1';
 510             report "privileged instruction";
 511
 512         elsif valid_in = '1' and e_in.unit = ALU then
 513
 514             report "execute nia " & to_hstring(e_in.nia);
 515
 516             v.e.valid := '1';
 517             v.e.write_reg := e_in.write_reg;
 518             v.slow_op_insn := e_in.insn_type;
 519             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 520             v.slow_op_rc := e_in.rc;
 521             v.slow_op_oe := e_in.oe;
 522             v.slow_op_xerc := v.e.xerc;
 523
 524             case_0: case e_in.insn_type is
 525
 526             when OP_ILLEGAL =>
 527                 -- we need two cycles to write srr0 and 1
 528                 -- will need more when we have to write HEIR
 529                 illegal := '1';
 530             when OP_SC =>
 531                 -- check bit 1 of the instruction is 1 so we know this is sc;
 532                 -- 0 would mean scv, so generate an illegal instruction interrupt
 533                 -- we need two cycles to write srr0 and 1
 534                 if e_in.insn(1) = '1' then
 535                     exception := '1';
 536                     exception_nextpc := '1';
 537                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#C00#, 64));
 538                     report "sc";
 539                 else
 540                     illegal := '1';
 541                 end if;
 542             when OP_ATTN =>
 543                 -- check bits 1-10 of the instruction to make sure it's attn
 544                 -- if not then it is illegal
 545                 if e_in.insn(10 downto 1) = "0100000000" then
 546                     v.terminate := '1';
 547                     report "ATTN";
 548                 else
 549                     illegal := '1';
 550                 end if;
 551             when OP_NOP =>
 552                 -- Do nothing
 553             when OP_ADD | OP_CMP | OP_TRAP =>
 554                 if e_in.invert_a = '0' then
 555                     a_inv := a_in;
 556                 else
 557                     a_inv := not a_in;
 558                 end if;
 559                 result_with_carry := ppc_adde(a_inv, b_in,
 560                                               decode_input_carry(e_in.input_carry, v.e.xerc));
 561                 result := result_with_carry(63 downto 0);
 562                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 563                 carry_64 := result_with_carry(64);
 564                 if e_in.insn_type = OP_ADD then
 565                     if e_in.output_carry = '1' then
 566                         set_carry(v.e, carry_32, carry_64);
 567                     end if;
 568                     if e_in.oe = '1' then
 569                         set_ov(v.e,
 570                                calc_ov(a_inv(63), b_in(63), carry_64, result_with_carry(63)),
 571                                calc_ov(a_inv(31), b_in(31), carry_32, result_with_carry(31)));
 572                     end if;
 573                     result_en := '1';
 574                 else
 575                     -- trap, CMP and CMPL instructions
 576                     -- Note, we have done RB - RA, not RA - RB
 577                     if e_in.insn_type = OP_CMP then
 578                         l := insn_l(e_in.insn);
 579                     else
 580                         l := not e_in.is_32bit;
 581                     end if;
 582                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 583                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 584                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 585                         -- values are equal
 586                         trapval := "00100";
 587                     else
 588                         if l = '1' then
 589                             -- 64-bit comparison
 590                             msb_a := a_in(63);
 591                             msb_b := b_in(63);
 592                         else
 593                             -- 32-bit comparison
 594                             msb_a := a_in(31);
 595                             msb_b := b_in(31);
 596                         end if;
 597                         if msb_a /= msb_b then
 598                             -- Subtraction might overflow, but
 599                             -- comparison is clear from MSB difference.
 600                             -- for signed, 0 is greater; for unsigned, 1 is greater
 601                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 602                         else
 603                             -- Subtraction cannot overflow since MSBs are equal.
 604                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 605                             a_lt := (not l and carry_32) or (l and carry_64);
 606                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 607                         end if;
 608                     end if;
 609                     if e_in.insn_type = OP_CMP then
 610                         if e_in.is_signed = '1' then
 611                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 612                         else
 613                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 614                         end if;
 615                         bf := insn_bf(e_in.insn);
 616                         crnum := to_integer(unsigned(bf));
 617                         v.e.write_cr_enable := '1';
 618                         v.e.write_cr_mask := num_to_fxm(crnum);
 619                         for i in 0 to 7 loop
 620                             lo := i*4;
 621                             hi := lo + 3;
 622                             v.e.write_cr_data(hi downto lo) := newcrf;
 623                         end loop;
 624                     else
 625                         -- trap instructions (tw, twi, td, tdi)
 626                         v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 627                         -- set bit 46 to say trap occurred
 628                         ctrl_tmp.srr1(63 - 46) <= '1';
 629                         if or (trapval and insn_to(e_in.insn)) = '1' then
 630                             -- generate trap-type program interrupt
 631                             exception := '1';
 632                             report "trap";
 633                         end if;
 634                     end if;
 635                 end if;
 636             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS =>
 637                 result := logical_result;
 638                 result_en := '1';
 639             when OP_B =>
 640                 is_branch := '1';
 641                 taken_branch := '1';
 642                 abs_branch := insn_aa(e_in.insn);
 643             when OP_BC =>
 644                 -- read_data1 is CTR
 645                 bo := insn_bo(e_in.insn);
 646                 bi := insn_bi(e_in.insn);
 647                 if bo(4-2) = '0' then
 648                     result := std_ulogic_vector(unsigned(a_in) - 1);
 649                     result_en := '1';
 650                     v.e.write_reg := fast_spr_num(SPR_CTR);
 651                 end if;
 652                 is_branch := '1';
 653                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 654                 abs_branch := insn_aa(e_in.insn);
 655             when OP_BCREG =>
 656                 -- read_data1 is CTR
 657                 -- read_data2 is target register (CTR, LR or TAR)
 658                 bo := insn_bo(e_in.insn);
 659                 bi := insn_bi(e_in.insn);
 660                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 661                     result := std_ulogic_vector(unsigned(a_in) - 1);
 662                     result_en := '1';
 663                     v.e.write_reg := fast_spr_num(SPR_CTR);
 664                 end if;
 665                 is_branch := '1';
 666                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 667                 abs_branch := '1';
 668
 669             when OP_RFID =>
 670                 v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
 671                 v.f.priv_mode := not a_in(MSR_PR);
 672                 -- Can't use msr_copy here because the partial function MSR
 673                 -- bits should be left unchanged, not zeroed.
 674                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 675                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 676                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 677                 if a_in(MSR_PR) = '1' then
 678                     ctrl_tmp.msr(MSR_EE) <= '1';
 679                     ctrl_tmp.msr(MSR_IR) <= '1';
 680                     ctrl_tmp.msr(MSR_DR) <= '1';
 681                 end if;
 682                 -- mark this as a branch so CFAR gets updated
 683                 is_branch := '1';
 684                 taken_branch := '1';
 685                 abs_branch := '1';
 686
 687             when OP_CNTZ =>
 688                 v.e.valid := '0';
 689                 v.cntz_in_progress := '1';
 690                 v.busy := '1';
 691             when OP_ISEL =>
 692                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 693                 if cr_in(31-crbit) = '1' then
 694                     result := a_in;
 695                 else
 696                     result := b_in;
 697                 end if;
 698                 result_en := '1';
 699             when OP_CROP =>
 700                 cr_op := insn_cr(e_in.insn);
 701                 report "CR OP " & to_hstring(cr_op);
 702                 if cr_op(0) = '0' then -- MCRF
 703                     bf := insn_bf(e_in.insn);
 704                     bfa := insn_bfa(e_in.insn);
 705                     v.e.write_cr_enable := '1';
 706                     crnum := to_integer(unsigned(bf));
 707                     scrnum := to_integer(unsigned(bfa));
 708                     v.e.write_cr_mask := num_to_fxm(crnum);
 709                     for i in 0 to 7 loop
 710                         lo := (7-i)*4;
 711                         hi := lo + 3;
 712                         if i = scrnum then
 713                             newcrf := cr_in(hi downto lo);
 714                         end if;
 715                     end loop;
 716                     for i in 0 to 7 loop
 717                         lo := i*4;
 718                         hi := lo + 3;
 719                         v.e.write_cr_data(hi downto lo) := newcrf;
 720                     end loop;
 721                 else
 722                     v.e.write_cr_enable := '1';
 723                     bt := insn_bt(e_in.insn);
 724                     ba := insn_ba(e_in.insn);
 725                     bb := insn_bb(e_in.insn);
 726                     btnum := 31 - to_integer(unsigned(bt));
 727                     banum := 31 - to_integer(unsigned(ba));
 728                     bbnum := 31 - to_integer(unsigned(bb));
 729                     -- Bits 5-8 of cr_op give the truth table of the requested
 730                     -- logical operation
 731                     cr_operands := cr_in(banum) & cr_in(bbnum);
 732                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 733                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 734                     for i in 0 to 31 loop
 735                         if i = btnum then
 736                             v.e.write_cr_data(i) := crresult;
 737                         else
 738                             v.e.write_cr_data(i) := cr_in(i);
 739                         end if;
 740                     end loop;
 741                 end if;
 742             when OP_MCRXRX =>
 743                 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
 744                 bf := insn_bf(e_in.insn);
 745                 crnum := to_integer(unsigned(bf));
 746                 v.e.write_cr_enable := '1';
 747                 v.e.write_cr_mask := num_to_fxm(crnum);
 748                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 749                                      newcrf & newcrf & newcrf & newcrf;
 750             when OP_MFMSR =>
 751                 result := ctrl.msr;
 752                 result_en := '1';
 753             when OP_MFSPR =>
 754                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 755                     "=" & to_hstring(a_in);
 756                 result_en := '1';
 757                 if is_fast_spr(e_in.read_reg1) then
 758                     result := a_in;
 759                     if decode_spr_num(e_in.insn) = SPR_XER then
 760                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 761                         result(63 downto 32) := (others => '0');
 762                         result(63-32) := v.e.xerc.so;
 763                         result(63-33) := v.e.xerc.ov;
 764                         result(63-34) := v.e.xerc.ca;
 765                         result(63-35 downto 63-43) := "000000000";
 766                         result(63-44) := v.e.xerc.ov32;
 767                         result(63-45) := v.e.xerc.ca32;
 768                     end if;
 769                 else
 770                     spr_val := c_in;
 771                     case decode_spr_num(e_in.insn) is
 772                     when SPR_TB =>
 773                         spr_val := ctrl.tb;
 774                     when SPR_TBU =>
 775                         spr_val(63 downto 32) := (others => '0');
 776                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 777                     when SPR_DEC =>
 778                         spr_val := ctrl.dec;
 779                     when SPR_CFAR =>
 780                         spr_val := ctrl.cfar;
 781                     when SPR_PVR =>
 782                         spr_val(63 downto 32) := (others => '0');
 783                         spr_val(31 downto 0) := PVR_MICROWATT;
 784                     when 724 =>     -- LOG_ADDR SPR
 785                         spr_val := log_wr_addr & r.log_addr_spr;
 786                     when 725 =>     -- LOG_DATA SPR
 787                         spr_val := log_rd_data;
 788                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 789                     when others =>
 790                         -- mfspr from unimplemented SPRs should be a nop in
 791                         -- supervisor mode and a program interrupt for user mode
 792                         if ctrl.msr(MSR_PR) = '1' then
 793                             illegal := '1';
 794                         end if;
 795                     end case;
 796                     result := spr_val;
 797                 end if;
 798             when OP_MFCR =>
 799                 if e_in.insn(20) = '0' then
 800                     -- mfcr
 801                     result := x"00000000" & cr_in;
 802                 else
 803                     -- mfocrf
 804                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 805                     result := (others => '0');
 806                     for i in 0 to 7 loop
 807                         lo := (7-i)*4;
 808                         hi := lo + 3;
 809                         if crnum = i then
 810                             result(hi downto lo) := cr_in(hi downto lo);
 811                         end if;
 812                     end loop;
 813                 end if;
 814                 result_en := '1';
 815             when OP_MTCRF =>
 816                 v.e.write_cr_enable := '1';
 817                 if e_in.insn(20) = '0' then
 818                     -- mtcrf
 819                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 820                 else
 821                     -- mtocrf: We require one hot priority encoding here
 822                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 823                     v.e.write_cr_mask := num_to_fxm(crnum);
 824                 end if;
 825                 v.e.write_cr_data := c_in(31 downto 0);
 826             when OP_MTMSRD =>
 827                 if e_in.insn(16) = '1' then
 828                     -- just update EE and RI
 829                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 830                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 831                 else
 832                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 833                     -- and 63 (LE) (IBM bit numbering)
 834                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 835                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 836                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 837                     if c_in(MSR_PR) = '1' then
 838                         ctrl_tmp.msr(MSR_EE) <= '1';
 839                         ctrl_tmp.msr(MSR_IR) <= '1';
 840                         ctrl_tmp.msr(MSR_DR) <= '1';
 841                     end if;
 842                 end if;
 843             when OP_MTSPR =>
 844                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 845                     "=" & to_hstring(c_in);
 846                 if is_fast_spr(e_in.write_reg) then
 847                     result := c_in;
 848                     result_en := '1';
 849                     if decode_spr_num(e_in.insn) = SPR_XER then
 850                         v.e.xerc.so := c_in(63-32);
 851                         v.e.xerc.ov := c_in(63-33);
 852                         v.e.xerc.ca := c_in(63-34);
 853                         v.e.xerc.ov32 := c_in(63-44);
 854                         v.e.xerc.ca32 := c_in(63-45);
 855                         v.e.write_xerc_enable := '1';
 856                     end if;
 857                 else
 858                     -- slow spr
 859                     case decode_spr_num(e_in.insn) is
 860                     when SPR_DEC =>
 861                         ctrl_tmp.dec <= c_in;
 862                     when 724 =>     -- LOG_ADDR SPR
 863                         v.log_addr_spr := c_in(31 downto 0);
 864                     when others =>
 865                         -- mtspr to unimplemented SPRs should be a nop in
 866                         -- supervisor mode and a program interrupt for user mode
 867                         if ctrl.msr(MSR_PR) = '1' then
 868                             illegal := '1';
 869                         end if;
 870                     end case;
 871                 end if;
 872             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
 873                 result := rotator_result;
 874                 if e_in.output_carry = '1' then
 875                     set_carry(v.e, rotator_carry, rotator_carry);
 876                 end if;
 877                 result_en := '1';
 878             when OP_SETB =>
 879                 bfa := insn_bfa(e_in.insn);
 880                 crbit := to_integer(unsigned(bfa)) * 4;
 881                 result := (others => '0');
 882                 if cr_in(31 - crbit) = '1' then
 883                     result := (others => '1');
 884                 elsif cr_in(30 - crbit) = '1' then
 885                     result(0) := '1';
 886                 end if;
 887
 888             when OP_ISYNC =>
 889                 v.f.redirect := '1';
 890                 v.f.redirect_nia := next_nia;
 891
 892             when OP_ICBI =>
 893                 icache_inval <= '1';
 894
 895             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
 896                 v.e.valid := '0';
 897                 v.mul_in_progress := '1';
 898                 v.busy := '1';
 899                 x_to_multiply.valid <= '1';
 900
 901             when OP_DIV | OP_DIVE | OP_MOD =>
 902                 v.e.valid := '0';
 903                 v.div_in_progress := '1';
 904                 v.busy := '1';
 905                 x_to_divider.valid <= '1';
 906
 907             when others =>
 908                 v.terminate := '1';
 909                 report "illegal";
 910             end case;
 911
 912             v.e.rc := e_in.rc and valid_in;
 913
 914             -- Mispredicted branches cause a redirect
 915             if is_branch = '1' then
 916                 if taken_branch = '1' then
 917                     ctrl_tmp.cfar <= e_in.nia;
 918                 end if;
 919                 if e_in.br_pred = '0' then
 920                     if abs_branch = '1' then
 921                         v.f.redirect_nia := b_in;
 922                     else
 923                         v.f.redirect_nia := std_ulogic_vector(signed(e_in.nia) + signed(b_in));
 924                     end if;
 925                 else
 926                     v.f.redirect_nia := next_nia;
 927                 end if;
 928                 if taken_branch /= e_in.br_pred then
 929                     v.f.redirect := '1';
 930                 end if;
 931             end if;
 932
 933             -- Update LR on the next cycle after a branch link
 934             -- If we're not writing back anything else, we can write back LR
 935             -- this cycle, otherwise we take an extra cycle.  We use the
 936             -- exc_write path since next_nia is written through that path
 937             -- in other places.
 938             if e_in.lr = '1' then
 939                 if result_en = '0' then
 940                     v.e.exc_write_enable := '1';
 941                     v.e.exc_write_data := next_nia;
 942                     v.e.exc_write_reg := fast_spr_num(SPR_LR);
 943                 else
 944                     v.lr_update := '1';
 945                     v.next_lr := next_nia;
 946                     v.e.valid := '0';
 947                     report "Delayed LR update to " & to_hstring(next_nia);
 948                     v.busy := '1';
 949                 end if;
 950             end if;
 951
 952         elsif valid_in = '1' then
 953             -- instruction for other units, i.e. LDST
 954             if e_in.unit = LDST then
 955                 lv.valid := '1';
 956             end if;
 957
 958         elsif r.f.redirect = '1' then
 959             v.e.valid := '1';
 960         elsif r.lr_update = '1' then
 961             v.e.exc_write_enable := '1';
 962             v.e.exc_write_data := r.next_lr;
 963             v.e.exc_write_reg := fast_spr_num(SPR_LR);
 964             v.e.valid := '1';
 965         elsif r.cntz_in_progress = '1' then
 966             -- cnt[lt]z always takes two cycles
 967             result := countzero_result;
 968             result_en := '1';
 969             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
 970             v.e.rc := r.slow_op_rc;
 971             v.e.xerc := r.slow_op_xerc;
 972             v.e.valid := '1';
 973         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
 974             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
 975                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
 976                 if r.mul_in_progress = '1' then
 977                     overflow := '0';
 978                     case r.slow_op_insn is
 979                         when OP_MUL_H32 =>
 980                             result := multiply_to_x.result(63 downto 32) &
 981                                       multiply_to_x.result(63 downto 32);
 982                         when OP_MUL_H64 =>
 983                             result := multiply_to_x.result(127 downto 64);
 984                         when others =>
 985                             -- i.e. OP_MUL_L64
 986                             result := multiply_to_x.result(63 downto 0);
 987                     end case;
 988                 else
 989                     result := divider_to_x.write_reg_data;
 990                     overflow := divider_to_x.overflow;
 991                 end if;
 992                 if r.mul_in_progress = '1' and r.slow_op_oe = '1' then
 993                     -- have to wait until next cycle for overflow indication
 994                     v.mul_finish := '1';
 995                     v.busy := '1';
 996                 else
 997                     result_en := '1';
 998                     v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
 999                     v.e.rc := r.slow_op_rc;
1000                     v.e.xerc := r.slow_op_xerc;
1001                     v.e.write_xerc_enable := r.slow_op_oe;
1002                     -- We must test oe because the RC update code in writeback
1003                     -- will use the xerc value to set CR0:SO so we must not clobber
1004                     -- xerc if OE wasn't set.
1005                     if r.slow_op_oe = '1' then
1006                         v.e.xerc.ov := overflow;
1007                         v.e.xerc.ov32 := overflow;
1008                         v.e.xerc.so := r.slow_op_xerc.so or overflow;
1009                     end if;
1010                     v.e.valid := '1';
1011                 end if;
1012             else
1013                 v.busy := '1';
1014                 v.mul_in_progress := r.mul_in_progress;
1015                 v.div_in_progress := r.div_in_progress;
1016             end if;
1017         elsif r.mul_finish = '1' then
1018             result := r.e.write_data;
1019             result_en := '1';
1020             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1021             v.e.rc := r.slow_op_rc;
1022             v.e.xerc := r.slow_op_xerc;
1023             v.e.write_xerc_enable := r.slow_op_oe;
1024             v.e.xerc.ov := multiply_to_x.overflow;
1025             v.e.xerc.ov32 := multiply_to_x.overflow;
1026             v.e.xerc.so := r.slow_op_xerc.so or multiply_to_x.overflow;
1027             v.e.valid := '1';
1028         end if;
1029
1030         if illegal = '1' then
1031             exception := '1';
1032             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
1033             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1034             -- set bit 44 to indicate we have an illegal
1035             ctrl_tmp.srr1(63 - 44) <= '1';
1036             report "illegal";
1037         end if;
1038         if exception = '1' then
1039             v.e.exc_write_enable := '1';
1040             if exception_nextpc = '1' then
1041                 v.e.exc_write_data := next_nia;
1042             end if;
1043         end if;
1044
1045         v.e.write_data := result;
1046         v.e.write_enable := result_en and not exception;
1047
1048         -- generate DSI or DSegI for load/store exceptions
1049         -- or ISI or ISegI for instruction fetch exceptions
1050         if l_in.exception = '1' then
1051             if l_in.instr_fault = '0' then
1052                 if l_in.segment_fault = '0' then
1053                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
1054                 else
1055                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#380#, 64));
1056                 end if;
1057             else
1058                 if l_in.segment_fault = '0' then
1059                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1060                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1061                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1062                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1063                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#400#, 64));
1064                 else
1065                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#480#, 64));
1066                 end if;
1067             end if;
1068             v.e.exc_write_enable := '1';
1069             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1070             v.e.exc_write_data := r.last_nia;
1071             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1072         end if;
1073
1074         if exception = '1' or l_in.exception = '1' then
1075             ctrl_tmp.irq_state <= WRITE_SRR1;
1076             v.f.redirect := '1';
1077             v.f.virt_mode := '0';
1078             v.f.priv_mode := '1';
1079         end if;
1080
1081         if v.f.redirect = '1' then
1082             v.busy := '1';
1083             v.e.valid := '0';
1084         end if;
1085
1086         -- Outputs to loadstore1 (async)
1087         lv.op := e_in.insn_type;
1088         lv.nia := e_in.nia;
1089         lv.addr1 := a_in;
1090         lv.addr2 := b_in;
1091         lv.data := c_in;
1092         lv.write_reg := gspr_to_gpr(e_in.write_reg);
1093         lv.length := e_in.data_len;
1094         lv.byte_reverse := e_in.byte_reverse;
1095         lv.sign_extend := e_in.sign_extend;
1096         lv.update := e_in.update;
1097         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1098         lv.xerc := v.e.xerc;
1099         lv.reserve := e_in.reserve;
1100         lv.rc := e_in.rc;
1101         lv.insn := e_in.insn;
1102         -- decode l*cix and st*cix instructions here
1103         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1104             e_in.insn(5 downto 1) = "10101" then
1105             lv.ci := '1';
1106         end if;
1107         lv.virt_mode := ctrl.msr(MSR_DR);
1108         lv.priv_mode := not ctrl.msr(MSR_PR);
1109
1110         -- Update registers
1111         rin <= v;
1112
1113         -- update outputs
1114         f_out <= r.f;
1115         l_out <= lv;
1116         e_out <= r.e;
1117         flush_out <= f_out.redirect;
1118
1119         exception_log <= exception;
1120         irq_valid_log <= irq_valid;
1121     end process;
1122
1123     e1_log: if LOG_LENGTH > 0 generate
1124         signal log_data : std_ulogic_vector(14 downto 0);
1125     begin
1126         ex1_log : process(clk)
1127         begin
1128             if rising_edge(clk) then
1129                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1130                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1131                             exception_log &
1132                             irq_valid_log &
1133                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1134                             "000" &
1135                             r.e.write_enable &
1136                             r.e.valid &
1137                             f_out.redirect &
1138                             r.busy &
1139                             flush_out;
1140             end if;
1141         end process;
1142         log_out <= log_data;
1143     end generate;
1144 end architecture behaviour;