execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         -- Non-zero to enable log data collection
  17         LOG_LENGTH : natural := 0
  18         );
  19     port (
  20         clk   : in std_ulogic;
  21         rst   : in std_ulogic;
  22
  23         -- asynchronous
  24         flush_out : out std_ulogic;
  25         busy_out : out std_ulogic;
  26
  27         e_in  : in Decode2ToExecute1Type;
  28         l_in  : in Loadstore1ToExecute1Type;
  29
  30         ext_irq_in : std_ulogic;
  31
  32         -- asynchronous
  33         l_out : out Execute1ToLoadstore1Type;
  34         f_out : out Execute1ToFetch1Type;
  35
  36         e_out : out Execute1ToWritebackType;
  37
  38         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  39
  40         icache_inval : out std_ulogic;
  41         terminate_out : out std_ulogic;
  42
  43         log_out : out std_ulogic_vector(14 downto 0);
  44         log_rd_addr : out std_ulogic_vector(31 downto 0);
  45         log_rd_data : in std_ulogic_vector(63 downto 0);
  46         log_wr_addr : in std_ulogic_vector(31 downto 0)
  47         );
  48 end entity execute1;
  49
  50 architecture behaviour of execute1 is
  51     type reg_type is record
  52         e : Execute1ToWritebackType;
  53         f : Execute1ToFetch1Type;
  54         busy: std_ulogic;
  55         terminate: std_ulogic;
  56         lr_update : std_ulogic;
  57         next_lr : std_ulogic_vector(63 downto 0);
  58         mul_in_progress : std_ulogic;
  59         div_in_progress : std_ulogic;
  60         cntz_in_progress : std_ulogic;
  61         slow_op_insn : insn_type_t;
  62         slow_op_dest : gpr_index_t;
  63         slow_op_rc : std_ulogic;
  64         slow_op_oe : std_ulogic;
  65         slow_op_xerc : xer_common_t;
  66         last_nia : std_ulogic_vector(63 downto 0);
  67         log_addr_spr : std_ulogic_vector(31 downto 0);
  68     end record;
  69     constant reg_type_init : reg_type :=
  70         (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
  71          busy => '0', lr_update => '0', terminate => '0',
  72          mul_in_progress => '0', div_in_progress => '0', cntz_in_progress => '0',
  73          slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  74          next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
  75
  76     signal r, rin : reg_type;
  77
  78     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  79     signal cr_in : std_ulogic_vector(31 downto 0);
  80
  81     signal valid_in : std_ulogic;
  82     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  83     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  84     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  85     signal rot_sign_ext: std_ulogic;
  86     signal rotator_result: std_ulogic_vector(63 downto 0);
  87     signal rotator_carry: std_ulogic;
  88     signal logical_result: std_ulogic_vector(63 downto 0);
  89     signal countzero_result: std_ulogic_vector(63 downto 0);
  90
  91     -- multiply signals
  92     signal x_to_multiply: Execute1ToMultiplyType;
  93     signal multiply_to_x: MultiplyToExecute1Type;
  94
  95     -- divider signals
  96     signal x_to_divider: Execute1ToDividerType;
  97     signal divider_to_x: DividerToExecute1Type;
  98
  99     -- signals for logging
 100     signal exception_log : std_ulogic;
 101     signal irq_valid_log : std_ulogic;
 102
 103     type privilege_level is (USER, SUPER);
 104     type op_privilege_array is array(insn_type_t) of privilege_level;
 105     constant op_privilege: op_privilege_array := (
 106         OP_ATTN => SUPER,
 107         OP_MFMSR => SUPER,
 108         OP_MTMSRD => SUPER,
 109         OP_RFID => SUPER,
 110         OP_TLBIE => SUPER,
 111         others => USER
 112         );
 113
 114     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 115         return boolean is
 116     begin
 117         if op_privilege(op) = SUPER then
 118             return true;
 119         elsif op = OP_MFSPR or op = OP_MTSPR then
 120             return insn(20) = '1';
 121         else
 122             return false;
 123         end if;
 124     end;
 125
 126     procedure set_carry(e: inout Execute1ToWritebackType;
 127                         carry32 : in std_ulogic;
 128                         carry : in std_ulogic) is
 129     begin
 130         e.xerc.ca32 := carry32;
 131         e.xerc.ca := carry;
 132         e.write_xerc_enable := '1';
 133     end;
 134
 135     procedure set_ov(e: inout Execute1ToWritebackType;
 136                      ov   : in std_ulogic;
 137                      ov32 : in std_ulogic) is
 138     begin
 139         e.xerc.ov32 := ov32;
 140         e.xerc.ov := ov;
 141         if ov = '1' then
 142             e.xerc.so := '1';
 143         end if;
 144         e.write_xerc_enable := '1';
 145     end;
 146
 147     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 148                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 149     begin
 150         return (ca xor msb_r) and not (msb_a xor msb_b);
 151     end;
 152
 153     function decode_input_carry(ic : carry_in_t;
 154                                 xerc : xer_common_t) return std_ulogic is
 155     begin
 156         case ic is
 157         when ZERO =>
 158             return '0';
 159         when CA =>
 160             return xerc.ca;
 161         when ONE =>
 162             return '1';
 163         end case;
 164     end;
 165
 166     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 167         return std_ulogic_vector is
 168         variable msr_out: std_ulogic_vector(63 downto 0);
 169     begin
 170         -- ISA says this:
 171         --  Defined MSR bits are classified as either full func-
 172         --  tion or partial function. Full function MSR bits are
 173         --  saved in SRR1 or HSRR1 when an interrupt other
 174         --  than a System Call Vectored interrupt occurs and
 175         --  restored by rfscv, rfid, or hrfid, while partial func-
 176         --  tion MSR bits are not saved or restored.
 177         --  Full function MSR bits lie in the range 0:32, 37:41, and
 178         --  48:63, and partial function MSR bits lie in the range
 179         --  33:36 and 42:47. (Note this is IBM bit numbering).
 180         msr_out := (others => '0');
 181         msr_out(63 downto 31) := msr(63 downto 31);
 182         msr_out(26 downto 22) := msr(26 downto 22);
 183         msr_out(15 downto 0)  := msr(15 downto 0);
 184         return msr_out;
 185     end;
 186
 187 begin
 188
 189     rotator_0: entity work.rotator
 190         port map (
 191             rs => c_in,
 192             ra => a_in,
 193             shift => b_in(6 downto 0),
 194             insn => e_in.insn,
 195             is_32bit => e_in.is_32bit,
 196             right_shift => right_shift,
 197             arith => e_in.is_signed,
 198             clear_left => rot_clear_left,
 199             clear_right => rot_clear_right,
 200             sign_ext_rs => rot_sign_ext,
 201             result => rotator_result,
 202             carry_out => rotator_carry
 203             );
 204
 205     logical_0: entity work.logical
 206         port map (
 207             rs => c_in,
 208             rb => b_in,
 209             op => e_in.insn_type,
 210             invert_in => e_in.invert_a,
 211             invert_out => e_in.invert_out,
 212             result => logical_result,
 213             datalen => e_in.data_len
 214             );
 215
 216     countzero_0: entity work.zero_counter
 217         port map (
 218             clk => clk,
 219             rs => c_in,
 220             count_right => e_in.insn(10),
 221             is_32bit => e_in.is_32bit,
 222             result => countzero_result
 223             );
 224
 225     multiply_0: entity work.multiply
 226         port map (
 227             clk => clk,
 228             m_in => x_to_multiply,
 229             m_out => multiply_to_x
 230             );
 231
 232     divider_0: entity work.divider
 233         port map (
 234             clk => clk,
 235             rst => rst,
 236             d_in => x_to_divider,
 237             d_out => divider_to_x
 238             );
 239
 240     dbg_msr_out <= ctrl.msr;
 241     log_rd_addr <= r.log_addr_spr;
 242
 243     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 244     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 245     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 246
 247     busy_out <= l_in.busy or r.busy;
 248     valid_in <= e_in.valid and not busy_out;
 249
 250     terminate_out <= r.terminate;
 251
 252     execute1_0: process(clk)
 253     begin
 254         if rising_edge(clk) then
 255             if rst = '1' then
 256                 r <= reg_type_init;
 257                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 258                 ctrl.irq_state <= WRITE_SRR0;
 259             else
 260                 r <= rin;
 261                 ctrl <= ctrl_tmp;
 262                 assert not (r.lr_update = '1' and valid_in = '1')
 263                     report "LR update collision with valid in EX1"
 264                     severity failure;
 265                 if r.lr_update = '1' then
 266                     report "LR update to " & to_hstring(r.next_lr);
 267                 end if;
 268             end if;
 269         end if;
 270     end process;
 271
 272     execute1_1: process(all)
 273         variable v : reg_type;
 274         variable a_inv : std_ulogic_vector(63 downto 0);
 275         variable result : std_ulogic_vector(63 downto 0);
 276         variable newcrf : std_ulogic_vector(3 downto 0);
 277         variable result_with_carry : std_ulogic_vector(64 downto 0);
 278         variable result_en : std_ulogic;
 279         variable crnum : crnum_t;
 280         variable crbit : integer range 0 to 31;
 281         variable scrnum : crnum_t;
 282         variable lo, hi : integer;
 283         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 284         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 285         variable bo, bi : std_ulogic_vector(4 downto 0);
 286         variable bf, bfa : std_ulogic_vector(2 downto 0);
 287         variable cr_op : std_ulogic_vector(9 downto 0);
 288         variable cr_operands : std_ulogic_vector(1 downto 0);
 289         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 290         variable btnum, banum, bbnum : integer range 0 to 31;
 291         variable crresult : std_ulogic;
 292         variable l : std_ulogic;
 293         variable next_nia : std_ulogic_vector(63 downto 0);
 294         variable carry_32, carry_64 : std_ulogic;
 295         variable sign1, sign2 : std_ulogic;
 296         variable abs1, abs2 : signed(63 downto 0);
 297         variable overflow : std_ulogic;
 298         variable zerohi, zerolo : std_ulogic;
 299         variable msb_a, msb_b : std_ulogic;
 300         variable a_lt : std_ulogic;
 301         variable lv : Execute1ToLoadstore1Type;
 302         variable irq_valid : std_ulogic;
 303         variable exception : std_ulogic;
 304         variable exception_nextpc : std_ulogic;
 305         variable trapval : std_ulogic_vector(4 downto 0);
 306         variable illegal : std_ulogic;
 307         variable is_branch : std_ulogic;
 308         variable taken_branch : std_ulogic;
 309         variable abs_branch : std_ulogic;
 310         variable spr_val : std_ulogic_vector(63 downto 0);
 311     begin
 312         result := (others => '0');
 313         result_with_carry := (others => '0');
 314         result_en := '0';
 315         newcrf := (others => '0');
 316         is_branch := '0';
 317         taken_branch := '0';
 318         abs_branch := '0';
 319
 320         v := r;
 321         v.e := Execute1ToWritebackInit;
 322         lv := Execute1ToLoadstore1Init;
 323         v.f.redirect := '0';
 324
 325         -- XER forwarding. To avoid having to track XER hazards, we
 326         -- use the previously latched value.
 327         --
 328         -- If the XER was modified by a multiply or a divide, those are
 329         -- single issue, we'll get the up to date value from decode2 from
 330         -- the register file.
 331         --
 332         -- If it was modified by an instruction older than the previous
 333         -- one in EX1, it will have also hit writeback and will be up
 334         -- to date in decode2.
 335         --
 336         -- That leaves us with the case where it was updated by the previous
 337         -- instruction in EX1. In that case, we can forward it back here.
 338         --
 339         -- This will break if we allow pipelining of multiply and divide,
 340         -- but ideally, those should go via EX1 anyway and run as a state
 341         -- machine from here.
 342         --
 343         -- One additional hazard to beware of is an XER:SO modifying instruction
 344         -- in EX1 followed immediately by a store conditional. Due to our
 345         -- writeback latency, the store will go down the LSU with the previous
 346         -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
 347         --
 348         -- We will need to handle that if we ever make stcx. not single issue
 349         --
 350         -- We always pass a valid XER value downto writeback even when
 351         -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
 352         -- to work for RC instructions.
 353         --
 354         if r.e.write_xerc_enable = '1' then
 355             v.e.xerc := r.e.xerc;
 356         else
 357             v.e.xerc := e_in.xerc;
 358         end if;
 359
 360         -- CR forwarding
 361         cr_in <= e_in.cr;
 362         if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
 363             for i in 0 to 7 loop
 364                 if r.e.write_cr_mask(i) = '1' then
 365                     cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
 366                 end if;
 367             end loop;
 368         end if;
 369
 370         v.lr_update := '0';
 371         v.mul_in_progress := '0';
 372         v.div_in_progress := '0';
 373         v.cntz_in_progress := '0';
 374
 375         -- signals to multiply and divide units
 376         sign1 := '0';
 377         sign2 := '0';
 378         if e_in.is_signed = '1' then
 379             if e_in.is_32bit = '1' then
 380                 sign1 := a_in(31);
 381                 sign2 := b_in(31);
 382             else
 383                 sign1 := a_in(63);
 384                 sign2 := b_in(63);
 385             end if;
 386         end if;
 387         -- take absolute values
 388         if sign1 = '0' then
 389             abs1 := signed(a_in);
 390         else
 391             abs1 := - signed(a_in);
 392         end if;
 393         if sign2 = '0' then
 394             abs2 := signed(b_in);
 395         else
 396             abs2 := - signed(b_in);
 397         end if;
 398
 399         x_to_multiply <= Execute1ToMultiplyInit;
 400         x_to_multiply.is_32bit <= e_in.is_32bit;
 401
 402         x_to_divider <= Execute1ToDividerInit;
 403         x_to_divider.is_signed <= e_in.is_signed;
 404         x_to_divider.is_32bit <= e_in.is_32bit;
 405         if e_in.insn_type = OP_MOD then
 406             x_to_divider.is_modulus <= '1';
 407         end if;
 408
 409         x_to_multiply.neg_result <= sign1 xor sign2;
 410         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 411         if e_in.is_32bit = '0' then
 412             -- 64-bit forms
 413             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 414             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 415             if e_in.insn_type = OP_DIVE then
 416                 x_to_divider.is_extended <= '1';
 417             end if;
 418             x_to_divider.dividend <= std_ulogic_vector(abs1);
 419             x_to_divider.divisor <= std_ulogic_vector(abs2);
 420         else
 421             -- 32-bit forms
 422             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 423             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 424             x_to_divider.is_extended <= '0';
 425             if e_in.insn_type = OP_DIVE then   -- extended forms
 426                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 427             else
 428                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 429             end if;
 430             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 431         end if;
 432
 433         ctrl_tmp <= ctrl;
 434         -- FIXME: run at 512MHz not core freq
 435         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 436         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 437
 438         irq_valid := '0';
 439         if ctrl.msr(MSR_EE) = '1' then
 440             if ctrl.dec(63) = '1' then
 441                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
 442                 report "IRQ valid: DEC";
 443                 irq_valid := '1';
 444             elsif ext_irq_in = '1' then
 445                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#500#, 64));
 446                 report "IRQ valid: External";
 447                 irq_valid := '1';
 448             end if;
 449         end if;
 450
 451         v.terminate := '0';
 452         icache_inval <= '0';
 453         v.busy := '0';
 454         -- send MSR[IR] and ~MSR[PR] up to fetch1
 455         v.f.virt_mode := ctrl.msr(MSR_IR);
 456         v.f.priv_mode := not ctrl.msr(MSR_PR);
 457
 458         -- Next insn adder used in a couple of places
 459         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 460
 461         -- rotator control signals
 462         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 463         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 464         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 465         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 466
 467         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 468         ctrl_tmp.irq_state <= WRITE_SRR0;
 469         exception := '0';
 470         illegal := '0';
 471         exception_nextpc := '0';
 472         v.e.exc_write_enable := '0';
 473         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 474         v.e.exc_write_data := e_in.nia;
 475         if valid_in = '1' then
 476             v.last_nia := e_in.nia;
 477         end if;
 478
 479         if ctrl.irq_state = WRITE_SRR1 then
 480             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 481             v.e.exc_write_data := ctrl.srr1;
 482             v.e.exc_write_enable := '1';
 483             ctrl_tmp.msr(MSR_SF) <= '1';
 484             ctrl_tmp.msr(MSR_EE) <= '0';
 485             ctrl_tmp.msr(MSR_PR) <= '0';
 486             ctrl_tmp.msr(MSR_IR) <= '0';
 487             ctrl_tmp.msr(MSR_DR) <= '0';
 488             ctrl_tmp.msr(MSR_RI) <= '0';
 489             ctrl_tmp.msr(MSR_LE) <= '1';
 490             v.e.valid := '1';
 491             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 492
 493         elsif irq_valid = '1' and valid_in = '1' then
 494             -- we need two cycles to write srr0 and 1
 495             -- will need more when we have to write HEIR
 496             -- Don't deliver the interrupt until we have a valid instruction
 497             -- coming in, so we have a valid NIA to put in SRR0.
 498             exception := '1';
 499
 500         elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
 501             instr_is_privileged(e_in.insn_type, e_in.insn) then
 502             -- generate a program interrupt
 503             exception := '1';
 504             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 505             -- set bit 45 to indicate privileged instruction type interrupt
 506             ctrl_tmp.srr1(63 - 45) <= '1';
 507             report "privileged instruction";
 508
 509         elsif valid_in = '1' and e_in.unit = ALU then
 510
 511             report "execute nia " & to_hstring(e_in.nia);
 512
 513             v.e.valid := '1';
 514             v.e.write_reg := e_in.write_reg;
 515             v.slow_op_insn := e_in.insn_type;
 516             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 517             v.slow_op_rc := e_in.rc;
 518             v.slow_op_oe := e_in.oe;
 519             v.slow_op_xerc := v.e.xerc;
 520
 521             case_0: case e_in.insn_type is
 522
 523             when OP_ILLEGAL =>
 524                 -- we need two cycles to write srr0 and 1
 525                 -- will need more when we have to write HEIR
 526                 illegal := '1';
 527             when OP_SC =>
 528                 -- check bit 1 of the instruction is 1 so we know this is sc;
 529                 -- 0 would mean scv, so generate an illegal instruction interrupt
 530                 -- we need two cycles to write srr0 and 1
 531                 if e_in.insn(1) = '1' then
 532                     exception := '1';
 533                     exception_nextpc := '1';
 534                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#C00#, 64));
 535                     report "sc";
 536                 else
 537                     illegal := '1';
 538                 end if;
 539             when OP_ATTN =>
 540                 -- check bits 1-10 of the instruction to make sure it's attn
 541                 -- if not then it is illegal
 542                 if e_in.insn(10 downto 1) = "0100000000" then
 543                     v.terminate := '1';
 544                     report "ATTN";
 545                 else
 546                     illegal := '1';
 547                 end if;
 548             when OP_NOP =>
 549                 -- Do nothing
 550             when OP_ADD | OP_CMP | OP_TRAP =>
 551                 if e_in.invert_a = '0' then
 552                     a_inv := a_in;
 553                 else
 554                     a_inv := not a_in;
 555                 end if;
 556                 result_with_carry := ppc_adde(a_inv, b_in,
 557                                               decode_input_carry(e_in.input_carry, v.e.xerc));
 558                 result := result_with_carry(63 downto 0);
 559                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 560                 carry_64 := result_with_carry(64);
 561                 if e_in.insn_type = OP_ADD then
 562                     if e_in.output_carry = '1' then
 563                         set_carry(v.e, carry_32, carry_64);
 564                     end if;
 565                     if e_in.oe = '1' then
 566                         set_ov(v.e,
 567                                calc_ov(a_inv(63), b_in(63), carry_64, result_with_carry(63)),
 568                                calc_ov(a_inv(31), b_in(31), carry_32, result_with_carry(31)));
 569                     end if;
 570                     result_en := '1';
 571                 else
 572                     -- trap, CMP and CMPL instructions
 573                     -- Note, we have done RB - RA, not RA - RB
 574                     if e_in.insn_type = OP_CMP then
 575                         l := insn_l(e_in.insn);
 576                     else
 577                         l := not e_in.is_32bit;
 578                     end if;
 579                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 580                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 581                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 582                         -- values are equal
 583                         trapval := "00100";
 584                     else
 585                         if l = '1' then
 586                             -- 64-bit comparison
 587                             msb_a := a_in(63);
 588                             msb_b := b_in(63);
 589                         else
 590                             -- 32-bit comparison
 591                             msb_a := a_in(31);
 592                             msb_b := b_in(31);
 593                         end if;
 594                         if msb_a /= msb_b then
 595                             -- Subtraction might overflow, but
 596                             -- comparison is clear from MSB difference.
 597                             -- for signed, 0 is greater; for unsigned, 1 is greater
 598                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 599                         else
 600                             -- Subtraction cannot overflow since MSBs are equal.
 601                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 602                             a_lt := (not l and carry_32) or (l and carry_64);
 603                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 604                         end if;
 605                     end if;
 606                     if e_in.insn_type = OP_CMP then
 607                         if e_in.is_signed = '1' then
 608                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 609                         else
 610                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 611                         end if;
 612                         bf := insn_bf(e_in.insn);
 613                         crnum := to_integer(unsigned(bf));
 614                         v.e.write_cr_enable := '1';
 615                         v.e.write_cr_mask := num_to_fxm(crnum);
 616                         for i in 0 to 7 loop
 617                             lo := i*4;
 618                             hi := lo + 3;
 619                             v.e.write_cr_data(hi downto lo) := newcrf;
 620                         end loop;
 621                     else
 622                         -- trap instructions (tw, twi, td, tdi)
 623                         v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 624                         -- set bit 46 to say trap occurred
 625                         ctrl_tmp.srr1(63 - 46) <= '1';
 626                         if or (trapval and insn_to(e_in.insn)) = '1' then
 627                             -- generate trap-type program interrupt
 628                             exception := '1';
 629                             report "trap";
 630                         end if;
 631                     end if;
 632                 end if;
 633             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS =>
 634                 result := logical_result;
 635                 result_en := '1';
 636             when OP_B =>
 637                 is_branch := '1';
 638                 taken_branch := '1';
 639                 abs_branch := insn_aa(e_in.insn);
 640             when OP_BC =>
 641                 -- read_data1 is CTR
 642                 bo := insn_bo(e_in.insn);
 643                 bi := insn_bi(e_in.insn);
 644                 if bo(4-2) = '0' then
 645                     result := std_ulogic_vector(unsigned(a_in) - 1);
 646                     result_en := '1';
 647                     v.e.write_reg := fast_spr_num(SPR_CTR);
 648                 end if;
 649                 is_branch := '1';
 650                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 651                 abs_branch := insn_aa(e_in.insn);
 652             when OP_BCREG =>
 653                 -- read_data1 is CTR
 654                 -- read_data2 is target register (CTR, LR or TAR)
 655                 bo := insn_bo(e_in.insn);
 656                 bi := insn_bi(e_in.insn);
 657                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 658                     result := std_ulogic_vector(unsigned(a_in) - 1);
 659                     result_en := '1';
 660                     v.e.write_reg := fast_spr_num(SPR_CTR);
 661                 end if;
 662                 is_branch := '1';
 663                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 664                 abs_branch := '1';
 665
 666             when OP_RFID =>
 667                 v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
 668                 v.f.priv_mode := not a_in(MSR_PR);
 669                 -- Can't use msr_copy here because the partial function MSR
 670                 -- bits should be left unchanged, not zeroed.
 671                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 672                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 673                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 674                 if a_in(MSR_PR) = '1' then
 675                     ctrl_tmp.msr(MSR_EE) <= '1';
 676                     ctrl_tmp.msr(MSR_IR) <= '1';
 677                     ctrl_tmp.msr(MSR_DR) <= '1';
 678                 end if;
 679                 -- mark this as a branch so CFAR gets updated
 680                 is_branch := '1';
 681                 taken_branch := '1';
 682                 abs_branch := '1';
 683
 684             when OP_CNTZ =>
 685                 v.e.valid := '0';
 686                 v.cntz_in_progress := '1';
 687                 v.busy := '1';
 688             when OP_ISEL =>
 689                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 690                 if cr_in(31-crbit) = '1' then
 691                     result := a_in;
 692                 else
 693                     result := b_in;
 694                 end if;
 695                 result_en := '1';
 696             when OP_CROP =>
 697                 cr_op := insn_cr(e_in.insn);
 698                 report "CR OP " & to_hstring(cr_op);
 699                 if cr_op(0) = '0' then -- MCRF
 700                     bf := insn_bf(e_in.insn);
 701                     bfa := insn_bfa(e_in.insn);
 702                     v.e.write_cr_enable := '1';
 703                     crnum := to_integer(unsigned(bf));
 704                     scrnum := to_integer(unsigned(bfa));
 705                     v.e.write_cr_mask := num_to_fxm(crnum);
 706                     for i in 0 to 7 loop
 707                         lo := (7-i)*4;
 708                         hi := lo + 3;
 709                         if i = scrnum then
 710                             newcrf := cr_in(hi downto lo);
 711                         end if;
 712                     end loop;
 713                     for i in 0 to 7 loop
 714                         lo := i*4;
 715                         hi := lo + 3;
 716                         v.e.write_cr_data(hi downto lo) := newcrf;
 717                     end loop;
 718                 else
 719                     v.e.write_cr_enable := '1';
 720                     bt := insn_bt(e_in.insn);
 721                     ba := insn_ba(e_in.insn);
 722                     bb := insn_bb(e_in.insn);
 723                     btnum := 31 - to_integer(unsigned(bt));
 724                     banum := 31 - to_integer(unsigned(ba));
 725                     bbnum := 31 - to_integer(unsigned(bb));
 726                     -- Bits 5-8 of cr_op give the truth table of the requested
 727                     -- logical operation
 728                     cr_operands := cr_in(banum) & cr_in(bbnum);
 729                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 730                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 731                     for i in 0 to 31 loop
 732                         if i = btnum then
 733                             v.e.write_cr_data(i) := crresult;
 734                         else
 735                             v.e.write_cr_data(i) := cr_in(i);
 736                         end if;
 737                     end loop;
 738                 end if;
 739             when OP_MFMSR =>
 740                 result := ctrl.msr;
 741                 result_en := '1';
 742             when OP_MFSPR =>
 743                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 744                     "=" & to_hstring(a_in);
 745                 result_en := '1';
 746                 if is_fast_spr(e_in.read_reg1) then
 747                     result := a_in;
 748                     if decode_spr_num(e_in.insn) = SPR_XER then
 749                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 750                         result(63 downto 32) := (others => '0');
 751                         result(63-32) := v.e.xerc.so;
 752                         result(63-33) := v.e.xerc.ov;
 753                         result(63-34) := v.e.xerc.ca;
 754                         result(63-35 downto 63-43) := "000000000";
 755                         result(63-44) := v.e.xerc.ov32;
 756                         result(63-45) := v.e.xerc.ca32;
 757                     end if;
 758                 else
 759                     spr_val := c_in;
 760                     case decode_spr_num(e_in.insn) is
 761                     when SPR_TB =>
 762                         spr_val := ctrl.tb;
 763                     when SPR_TBU =>
 764                         spr_val(63 downto 32) := (others => '0');
 765                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 766                     when SPR_DEC =>
 767                         spr_val := ctrl.dec;
 768                     when SPR_CFAR =>
 769                         spr_val := ctrl.cfar;
 770                     when SPR_PVR =>
 771                         spr_val(63 downto 32) := (others => '0');
 772                         spr_val(31 downto 0) := PVR_MICROWATT;
 773                     when 724 =>     -- LOG_ADDR SPR
 774                         spr_val := log_wr_addr & r.log_addr_spr;
 775                     when 725 =>     -- LOG_DATA SPR
 776                         spr_val := log_rd_data;
 777                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 778                     when others =>
 779                         -- mfspr from unimplemented SPRs should be a nop in
 780                         -- supervisor mode and a program interrupt for user mode
 781                         if ctrl.msr(MSR_PR) = '1' then
 782                             illegal := '1';
 783                         end if;
 784                     end case;
 785                     result := spr_val;
 786                 end if;
 787             when OP_MFCR =>
 788                 if e_in.insn(20) = '0' then
 789                     -- mfcr
 790                     result := x"00000000" & cr_in;
 791                 else
 792                     -- mfocrf
 793                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 794                     result := (others => '0');
 795                     for i in 0 to 7 loop
 796                         lo := (7-i)*4;
 797                         hi := lo + 3;
 798                         if crnum = i then
 799                             result(hi downto lo) := cr_in(hi downto lo);
 800                         end if;
 801                     end loop;
 802                 end if;
 803                 result_en := '1';
 804             when OP_MTCRF =>
 805                 v.e.write_cr_enable := '1';
 806                 if e_in.insn(20) = '0' then
 807                     -- mtcrf
 808                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 809                 else
 810                     -- mtocrf: We require one hot priority encoding here
 811                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 812                     v.e.write_cr_mask := num_to_fxm(crnum);
 813                 end if;
 814                 v.e.write_cr_data := c_in(31 downto 0);
 815             when OP_MTMSRD =>
 816                 if e_in.insn(16) = '1' then
 817                     -- just update EE and RI
 818                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 819                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 820                 else
 821                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 822                     -- and 63 (LE) (IBM bit numbering)
 823                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 824                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 825                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 826                     if c_in(MSR_PR) = '1' then
 827                         ctrl_tmp.msr(MSR_EE) <= '1';
 828                         ctrl_tmp.msr(MSR_IR) <= '1';
 829                         ctrl_tmp.msr(MSR_DR) <= '1';
 830                     end if;
 831                 end if;
 832             when OP_MTSPR =>
 833                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 834                     "=" & to_hstring(c_in);
 835                 if is_fast_spr(e_in.write_reg) then
 836                     result := c_in;
 837                     result_en := '1';
 838                     if decode_spr_num(e_in.insn) = SPR_XER then
 839                         v.e.xerc.so := c_in(63-32);
 840                         v.e.xerc.ov := c_in(63-33);
 841                         v.e.xerc.ca := c_in(63-34);
 842                         v.e.xerc.ov32 := c_in(63-44);
 843                         v.e.xerc.ca32 := c_in(63-45);
 844                         v.e.write_xerc_enable := '1';
 845                     end if;
 846                 else
 847                     -- slow spr
 848                     case decode_spr_num(e_in.insn) is
 849                     when SPR_DEC =>
 850                         ctrl_tmp.dec <= c_in;
 851                     when 724 =>     -- LOG_ADDR SPR
 852                         v.log_addr_spr := c_in(31 downto 0);
 853                     when others =>
 854                         -- mtspr to unimplemented SPRs should be a nop in
 855                         -- supervisor mode and a program interrupt for user mode
 856                         if ctrl.msr(MSR_PR) = '1' then
 857                             illegal := '1';
 858                         end if;
 859                     end case;
 860                 end if;
 861             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
 862                 result := rotator_result;
 863                 if e_in.output_carry = '1' then
 864                     set_carry(v.e, rotator_carry, rotator_carry);
 865                 end if;
 866                 result_en := '1';
 867
 868             when OP_ISYNC =>
 869                 v.f.redirect := '1';
 870                 v.f.redirect_nia := next_nia;
 871
 872             when OP_ICBI =>
 873                 icache_inval <= '1';
 874
 875             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
 876                 v.e.valid := '0';
 877                 v.mul_in_progress := '1';
 878                 v.busy := '1';
 879                 x_to_multiply.valid <= '1';
 880
 881             when OP_DIV | OP_DIVE | OP_MOD =>
 882                 v.e.valid := '0';
 883                 v.div_in_progress := '1';
 884                 v.busy := '1';
 885                 x_to_divider.valid <= '1';
 886
 887             when others =>
 888                 v.terminate := '1';
 889                 report "illegal";
 890             end case;
 891
 892             v.e.rc := e_in.rc and valid_in;
 893
 894             -- Mispredicted branches cause a redirect
 895             if is_branch = '1' then
 896                 if taken_branch = '1' then
 897                     ctrl_tmp.cfar <= e_in.nia;
 898                 end if;
 899                 if e_in.br_pred = '0' then
 900                     if abs_branch = '1' then
 901                         v.f.redirect_nia := b_in;
 902                     else
 903                         v.f.redirect_nia := std_ulogic_vector(signed(e_in.nia) + signed(b_in));
 904                     end if;
 905                 else
 906                     v.f.redirect_nia := next_nia;
 907                 end if;
 908                 if taken_branch /= e_in.br_pred then
 909                     v.f.redirect := '1';
 910                 end if;
 911             end if;
 912
 913             -- Update LR on the next cycle after a branch link
 914             -- If we're not writing back anything else, we can write back LR
 915             -- this cycle, otherwise we take an extra cycle.  We use the
 916             -- exc_write path since next_nia is written through that path
 917             -- in other places.
 918             if e_in.lr = '1' then
 919                 if result_en = '0' then
 920                     v.e.exc_write_enable := '1';
 921                     v.e.exc_write_data := next_nia;
 922                     v.e.exc_write_reg := fast_spr_num(SPR_LR);
 923                 else
 924                     v.lr_update := '1';
 925                     v.next_lr := next_nia;
 926                     v.e.valid := '0';
 927                     report "Delayed LR update to " & to_hstring(next_nia);
 928                     v.busy := '1';
 929                 end if;
 930             end if;
 931
 932         elsif valid_in = '1' then
 933             -- instruction for other units, i.e. LDST
 934             if e_in.unit = LDST then
 935                 lv.valid := '1';
 936             end if;
 937
 938         elsif r.f.redirect = '1' then
 939             v.e.valid := '1';
 940         elsif r.lr_update = '1' then
 941             v.e.exc_write_enable := '1';
 942             v.e.exc_write_data := r.next_lr;
 943             v.e.exc_write_reg := fast_spr_num(SPR_LR);
 944             v.e.valid := '1';
 945         elsif r.cntz_in_progress = '1' then
 946             -- cnt[lt]z always takes two cycles
 947             result := countzero_result;
 948             result_en := '1';
 949             v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 950             v.e.rc := v.slow_op_rc;
 951             v.e.xerc := v.slow_op_xerc;
 952             v.e.valid := '1';
 953         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
 954             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
 955                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
 956                 if r.mul_in_progress = '1' then
 957                     overflow := '0';
 958                     case r.slow_op_insn is
 959                         when OP_MUL_H32 =>
 960                             result := multiply_to_x.result(63 downto 32) &
 961                                       multiply_to_x.result(63 downto 32);
 962                         when OP_MUL_H64 =>
 963                             result := multiply_to_x.result(127 downto 64);
 964                         when others =>
 965                             -- i.e. OP_MUL_L64
 966                             result := multiply_to_x.result(63 downto 0);
 967                             overflow := multiply_to_x.overflow;
 968                     end case;
 969                 else
 970                     result := divider_to_x.write_reg_data;
 971                     overflow := divider_to_x.overflow;
 972                 end if;
 973                 result_en := '1';
 974                 v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 975                 v.e.rc := v.slow_op_rc;
 976                 v.e.xerc := v.slow_op_xerc;
 977                 v.e.write_xerc_enable := v.slow_op_oe;
 978                 -- We must test oe because the RC update code in writeback
 979                 -- will use the xerc value to set CR0:SO so we must not clobber
 980                 -- xerc if OE wasn't set.
 981                 if v.slow_op_oe = '1' then
 982                     v.e.xerc.ov := overflow;
 983                     v.e.xerc.ov32 := overflow;
 984                     v.e.xerc.so := v.slow_op_xerc.so or overflow;
 985                 end if;
 986                 v.e.valid := '1';
 987             else
 988                 v.busy := '1';
 989                 v.mul_in_progress := r.mul_in_progress;
 990                 v.div_in_progress := r.div_in_progress;
 991             end if;
 992         end if;
 993
 994         if illegal = '1' then
 995             exception := '1';
 996             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 997             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
 998             -- set bit 44 to indicate we have an illegal
 999             ctrl_tmp.srr1(63 - 44) <= '1';
1000             report "illegal";
1001         end if;
1002         if exception = '1' then
1003             v.e.exc_write_enable := '1';
1004             if exception_nextpc = '1' then
1005                 v.e.exc_write_data := next_nia;
1006             end if;
1007         end if;
1008
1009         v.e.write_data := result;
1010         v.e.write_enable := result_en and not exception;
1011
1012         -- generate DSI or DSegI for load/store exceptions
1013         -- or ISI or ISegI for instruction fetch exceptions
1014         if l_in.exception = '1' then
1015             if l_in.instr_fault = '0' then
1016                 if l_in.segment_fault = '0' then
1017                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
1018                 else
1019                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#380#, 64));
1020                 end if;
1021             else
1022                 if l_in.segment_fault = '0' then
1023                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1024                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1025                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1026                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1027                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#400#, 64));
1028                 else
1029                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#480#, 64));
1030                 end if;
1031             end if;
1032             v.e.exc_write_enable := '1';
1033             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1034             v.e.exc_write_data := r.last_nia;
1035             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1036         end if;
1037
1038         if exception = '1' or l_in.exception = '1' then
1039             ctrl_tmp.irq_state <= WRITE_SRR1;
1040             v.f.redirect := '1';
1041             v.f.virt_mode := '0';
1042             v.f.priv_mode := '1';
1043         end if;
1044
1045         if v.f.redirect = '1' then
1046             v.busy := '1';
1047             v.e.valid := '0';
1048         end if;
1049
1050         -- Outputs to loadstore1 (async)
1051         lv.op := e_in.insn_type;
1052         lv.nia := e_in.nia;
1053         lv.addr1 := a_in;
1054         lv.addr2 := b_in;
1055         lv.data := c_in;
1056         lv.write_reg := gspr_to_gpr(e_in.write_reg);
1057         lv.length := e_in.data_len;
1058         lv.byte_reverse := e_in.byte_reverse;
1059         lv.sign_extend := e_in.sign_extend;
1060         lv.update := e_in.update;
1061         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1062         lv.xerc := v.e.xerc;
1063         lv.reserve := e_in.reserve;
1064         lv.rc := e_in.rc;
1065         lv.insn := e_in.insn;
1066         -- decode l*cix and st*cix instructions here
1067         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1068             e_in.insn(5 downto 1) = "10101" then
1069             lv.ci := '1';
1070         end if;
1071         lv.virt_mode := ctrl.msr(MSR_DR);
1072         lv.priv_mode := not ctrl.msr(MSR_PR);
1073
1074         -- Update registers
1075         rin <= v;
1076
1077         -- update outputs
1078         f_out <= r.f;
1079         l_out <= lv;
1080         e_out <= r.e;
1081         flush_out <= f_out.redirect;
1082
1083         exception_log <= exception;
1084         irq_valid_log <= irq_valid;
1085     end process;
1086
1087     e1_log: if LOG_LENGTH > 0 generate
1088         signal log_data : std_ulogic_vector(14 downto 0);
1089     begin
1090         ex1_log : process(clk)
1091         begin
1092             if rising_edge(clk) then
1093                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1094                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1095                             exception_log &
1096                             irq_valid_log &
1097                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1098                             "000" &
1099                             r.e.write_enable &
1100                             r.e.valid &
1101                             f_out.redirect &
1102                             r.busy &
1103                             flush_out;
1104             end if;
1105         end process;
1106         log_out <= log_data;
1107     end generate;
1108 end architecture behaviour;