execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         HAS_FPU : boolean := true;
  17         -- Non-zero to enable log data collection
  18         LOG_LENGTH : natural := 0
  19         );
  20     port (
  21         clk   : in std_ulogic;
  22         rst   : in std_ulogic;
  23
  24         -- asynchronous
  25         flush_out : out std_ulogic;
  26         busy_out : out std_ulogic;
  27
  28         e_in  : in Decode2ToExecute1Type;
  29         l_in  : in Loadstore1ToExecute1Type;
  30         fp_in : in FPUToExecute1Type;
  31
  32         ext_irq_in : std_ulogic;
  33
  34         -- asynchronous
  35         l_out : out Execute1ToLoadstore1Type;
  36         f_out : out Execute1ToFetch1Type;
  37         fp_out : out Execute1ToFPUType;
  38
  39         e_out : out Execute1ToWritebackType;
  40         bypass_data : out bypass_data_t;
  41
  42         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  43
  44         icache_inval : out std_ulogic;
  45         terminate_out : out std_ulogic;
  46
  47         log_out : out std_ulogic_vector(14 downto 0);
  48         log_rd_addr : out std_ulogic_vector(31 downto 0);
  49         log_rd_data : in std_ulogic_vector(63 downto 0);
  50         log_wr_addr : in std_ulogic_vector(31 downto 0)
  51         );
  52 end entity execute1;
  53
  54 architecture behaviour of execute1 is
  55     type reg_type is record
  56         e : Execute1ToWritebackType;
  57         cur_instr : Decode2ToExecute1Type;
  58         busy: std_ulogic;
  59         terminate: std_ulogic;
  60         fp_exception_next : std_ulogic;
  61         trace_next : std_ulogic;
  62         prev_op : insn_type_t;
  63         next_lr : std_ulogic_vector(63 downto 0);
  64         br_taken : std_ulogic;
  65         mul_in_progress : std_ulogic;
  66         mul_finish : std_ulogic;
  67         div_in_progress : std_ulogic;
  68         cntz_in_progress : std_ulogic;
  69         last_nia : std_ulogic_vector(63 downto 0);
  70         redirect : std_ulogic;
  71         abs_br : std_ulogic;
  72         taken_br : std_ulogic;
  73         br_last : std_ulogic;
  74         do_intr : std_ulogic;
  75         vector : integer range 0 to 16#fff#;
  76         br_offset : std_ulogic_vector(63 downto 0);
  77         redir_mode : std_ulogic_vector(3 downto 0);
  78         log_addr_spr : std_ulogic_vector(31 downto 0);
  79     end record;
  80     constant reg_type_init : reg_type :=
  81         (e => Execute1ToWritebackInit,
  82          cur_instr => Decode2ToExecute1Init,
  83          busy => '0', terminate => '0',
  84          fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL, br_taken => '0',
  85          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  86          next_lr => (others => '0'), last_nia => (others => '0'),
  87          redirect => '0', abs_br => '0', taken_br => '0', br_last => '0', do_intr => '0', vector => 0,
  88          br_offset => (others => '0'), redir_mode => "0000",
  89          others => (others => '0'));
  90
  91     signal r, rin : reg_type;
  92
  93     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  94     signal cr_in : std_ulogic_vector(31 downto 0);
  95
  96     signal valid_in : std_ulogic;
  97     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  98     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  99     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
 100     signal rot_sign_ext: std_ulogic;
 101     signal rotator_result: std_ulogic_vector(63 downto 0);
 102     signal rotator_carry: std_ulogic;
 103     signal logical_result: std_ulogic_vector(63 downto 0);
 104     signal countzero_result: std_ulogic_vector(63 downto 0);
 105     signal alu_result: std_ulogic_vector(63 downto 0);
 106     signal adder_result: std_ulogic_vector(63 downto 0);
 107     signal misc_result: std_ulogic_vector(63 downto 0);
 108     signal muldiv_result: std_ulogic_vector(63 downto 0);
 109     signal spr_result: std_ulogic_vector(63 downto 0);
 110     signal result_mux_sel: std_ulogic_vector(2 downto 0);
 111     signal sub_mux_sel: std_ulogic_vector(2 downto 0);
 112     signal next_nia : std_ulogic_vector(63 downto 0);
 113     signal current: Decode2ToExecute1Type;
 114
 115     -- multiply signals
 116     signal x_to_multiply: MultiplyInputType;
 117     signal multiply_to_x: MultiplyOutputType;
 118
 119     -- divider signals
 120     signal x_to_divider: Execute1ToDividerType;
 121     signal divider_to_x: DividerToExecute1Type;
 122
 123     -- random number generator signals
 124     signal random_raw  : std_ulogic_vector(63 downto 0);
 125     signal random_cond : std_ulogic_vector(63 downto 0);
 126     signal random_err  : std_ulogic;
 127
 128     -- signals for logging
 129     signal exception_log : std_ulogic;
 130     signal irq_valid_log : std_ulogic;
 131
 132     type privilege_level is (USER, SUPER);
 133     type op_privilege_array is array(insn_type_t) of privilege_level;
 134     constant op_privilege: op_privilege_array := (
 135         OP_ATTN => SUPER,
 136         OP_MFMSR => SUPER,
 137         OP_MTMSRD => SUPER,
 138         OP_RFID => SUPER,
 139         OP_TLBIE => SUPER,
 140         others => USER
 141         );
 142
 143     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 144         return boolean is
 145     begin
 146         if op_privilege(op) = SUPER then
 147             return true;
 148         elsif op = OP_MFSPR or op = OP_MTSPR then
 149             return insn(20) = '1';
 150         else
 151             return false;
 152         end if;
 153     end;
 154
 155     procedure set_carry(e: inout Execute1ToWritebackType;
 156                         carry32 : in std_ulogic;
 157                         carry : in std_ulogic) is
 158     begin
 159         e.xerc.ca32 := carry32;
 160         e.xerc.ca := carry;
 161         e.write_xerc_enable := '1';
 162     end;
 163
 164     procedure set_ov(e: inout Execute1ToWritebackType;
 165                      ov   : in std_ulogic;
 166                      ov32 : in std_ulogic) is
 167     begin
 168         e.xerc.ov32 := ov32;
 169         e.xerc.ov := ov;
 170         if ov = '1' then
 171             e.xerc.so := '1';
 172         end if;
 173         e.write_xerc_enable := '1';
 174     end;
 175
 176     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 177                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 178     begin
 179         return (ca xor msb_r) and not (msb_a xor msb_b);
 180     end;
 181
 182     function decode_input_carry(ic : carry_in_t;
 183                                 xerc : xer_common_t) return std_ulogic is
 184     begin
 185         case ic is
 186         when ZERO =>
 187             return '0';
 188         when CA =>
 189             return xerc.ca;
 190         when OV =>
 191             return xerc.ov;
 192         when ONE =>
 193             return '1';
 194         end case;
 195     end;
 196
 197     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 198         return std_ulogic_vector is
 199         variable msr_out: std_ulogic_vector(63 downto 0);
 200     begin
 201         -- ISA says this:
 202         --  Defined MSR bits are classified as either full func-
 203         --  tion or partial function. Full function MSR bits are
 204         --  saved in SRR1 or HSRR1 when an interrupt other
 205         --  than a System Call Vectored interrupt occurs and
 206         --  restored by rfscv, rfid, or hrfid, while partial func-
 207         --  tion MSR bits are not saved or restored.
 208         --  Full function MSR bits lie in the range 0:32, 37:41, and
 209         --  48:63, and partial function MSR bits lie in the range
 210         --  33:36 and 42:47. (Note this is IBM bit numbering).
 211         msr_out := (others => '0');
 212         msr_out(63 downto 31) := msr(63 downto 31);
 213         msr_out(26 downto 22) := msr(26 downto 22);
 214         msr_out(15 downto 0)  := msr(15 downto 0);
 215         return msr_out;
 216     end;
 217
 218     -- Tell vivado to keep the hierarchy for the random module so that the
 219     -- net names in the xdc file match.
 220     attribute keep_hierarchy : string;
 221     attribute keep_hierarchy of random_0 : label is "yes";
 222
 223 begin
 224
 225     rotator_0: entity work.rotator
 226         port map (
 227             rs => c_in,
 228             ra => a_in,
 229             shift => b_in(6 downto 0),
 230             insn => e_in.insn,
 231             is_32bit => e_in.is_32bit,
 232             right_shift => right_shift,
 233             arith => e_in.is_signed,
 234             clear_left => rot_clear_left,
 235             clear_right => rot_clear_right,
 236             sign_ext_rs => rot_sign_ext,
 237             result => rotator_result,
 238             carry_out => rotator_carry
 239             );
 240
 241     logical_0: entity work.logical
 242         port map (
 243             rs => c_in,
 244             rb => b_in,
 245             op => e_in.insn_type,
 246             invert_in => e_in.invert_a,
 247             invert_out => e_in.invert_out,
 248             result => logical_result,
 249             datalen => e_in.data_len
 250             );
 251
 252     countzero_0: entity work.zero_counter
 253         port map (
 254             clk => clk,
 255             rs => c_in,
 256             count_right => e_in.insn(10),
 257             is_32bit => e_in.is_32bit,
 258             result => countzero_result
 259             );
 260
 261     multiply_0: entity work.multiply
 262         port map (
 263             clk => clk,
 264             m_in => x_to_multiply,
 265             m_out => multiply_to_x
 266             );
 267
 268     divider_0: entity work.divider
 269         port map (
 270             clk => clk,
 271             rst => rst,
 272             d_in => x_to_divider,
 273             d_out => divider_to_x
 274             );
 275
 276     random_0: entity work.random
 277         port map (
 278             clk => clk,
 279             data => random_cond,
 280             raw => random_raw,
 281             err => random_err
 282             );
 283
 284     dbg_msr_out <= ctrl.msr;
 285     log_rd_addr <= r.log_addr_spr;
 286
 287     a_in <= e_in.read_data1;
 288     b_in <= e_in.read_data2;
 289     c_in <= e_in.read_data3;
 290
 291     busy_out <= l_in.busy or r.busy or fp_in.busy;
 292     valid_in <= e_in.valid and not busy_out;
 293
 294     terminate_out <= r.terminate;
 295
 296     current <= e_in when r.busy = '0' else r.cur_instr;
 297
 298     -- Result mux
 299     with current.result_sel select alu_result <=
 300         adder_result       when "000",
 301         logical_result     when "001",
 302         rotator_result     when "010",
 303         muldiv_result      when "011",
 304         countzero_result   when "100",
 305         spr_result         when "101",
 306         next_nia           when "110",
 307         misc_result        when others;
 308
 309     execute1_0: process(clk)
 310     begin
 311         if rising_edge(clk) then
 312             if rst = '1' then
 313                 r <= reg_type_init;
 314                 ctrl.tb <= (others => '0');
 315                 ctrl.dec <= (others => '0');
 316                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 317                 ctrl.irq_state <= WRITE_SRR0;
 318             else
 319                 r <= rin;
 320                 ctrl <= ctrl_tmp;
 321                 if valid_in = '1' then
 322                     report "execute " & to_hstring(e_in.nia) & " op=" & insn_type_t'image(e_in.insn_type) &
 323                         " wr=" & to_hstring(rin.e.write_reg) & " we=" & std_ulogic'image(rin.e.write_enable) &
 324                         " tag=" & integer'image(rin.e.instr_tag.tag) & std_ulogic'image(rin.e.instr_tag.valid);
 325                 end if;
 326             end if;
 327         end if;
 328     end process;
 329
 330     execute1_1: process(all)
 331         variable v : reg_type;
 332         variable a_inv : std_ulogic_vector(63 downto 0);
 333         variable b_or_m1 : std_ulogic_vector(63 downto 0);
 334         variable addg6s : std_ulogic_vector(63 downto 0);
 335         variable isel_result : std_ulogic_vector(63 downto 0);
 336         variable darn : std_ulogic_vector(63 downto 0);
 337         variable mfcr_result : std_ulogic_vector(63 downto 0);
 338         variable setb_result : std_ulogic_vector(63 downto 0);
 339         variable newcrf : std_ulogic_vector(3 downto 0);
 340         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 341         variable crnum : crnum_t;
 342         variable crbit : integer range 0 to 31;
 343         variable scrnum : crnum_t;
 344         variable lo, hi : integer;
 345         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 346         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 347         variable bo, bi : std_ulogic_vector(4 downto 0);
 348         variable bf, bfa : std_ulogic_vector(2 downto 0);
 349         variable cr_op : std_ulogic_vector(9 downto 0);
 350         variable cr_operands : std_ulogic_vector(1 downto 0);
 351         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 352         variable btnum, banum, bbnum : integer range 0 to 31;
 353         variable crresult : std_ulogic;
 354         variable l : std_ulogic;
 355         variable carry_32, carry_64 : std_ulogic;
 356         variable sign1, sign2 : std_ulogic;
 357         variable abs1, abs2 : signed(63 downto 0);
 358         variable overflow : std_ulogic;
 359         variable zerohi, zerolo : std_ulogic;
 360         variable msb_a, msb_b : std_ulogic;
 361         variable a_lt : std_ulogic;
 362         variable a_lt_lo : std_ulogic;
 363         variable a_lt_hi : std_ulogic;
 364         variable lv : Execute1ToLoadstore1Type;
 365         variable irq_valid : std_ulogic;
 366         variable exception : std_ulogic;
 367         variable exception_nextpc : std_ulogic;
 368         variable trapval : std_ulogic_vector(4 downto 0);
 369         variable illegal : std_ulogic;
 370         variable is_branch : std_ulogic;
 371         variable is_direct_branch : std_ulogic;
 372         variable taken_branch : std_ulogic;
 373         variable abs_branch : std_ulogic;
 374         variable spr_val : std_ulogic_vector(63 downto 0);
 375         variable addend : std_ulogic_vector(127 downto 0);
 376         variable do_trace : std_ulogic;
 377         variable hold_wr_data : std_ulogic;
 378         variable f : Execute1ToFetch1Type;
 379         variable fv : Execute1ToFPUType;
 380     begin
 381         sum_with_carry := (others => '0');
 382         newcrf := (others => '0');
 383         is_branch := '0';
 384         is_direct_branch := '0';
 385         taken_branch := '0';
 386         abs_branch := '0';
 387         hold_wr_data := '0';
 388
 389         v := r;
 390         v.e := Execute1ToWritebackInit;
 391         v.redirect := '0';
 392         v.abs_br := '0';
 393         v.do_intr := '0';
 394         v.vector := 0;
 395         v.br_offset := (others => '0');
 396         v.redir_mode := ctrl.msr(MSR_IR) & not ctrl.msr(MSR_PR) &
 397                         not ctrl.msr(MSR_LE) & not ctrl.msr(MSR_SF);
 398         v.taken_br := '0';
 399         v.br_last := '0';
 400
 401         lv := Execute1ToLoadstore1Init;
 402         fv := Execute1ToFPUInit;
 403
 404         -- XER forwarding. To avoid having to track XER hazards, we use
 405         -- the previously latched value.  Since the XER common bits
 406         -- (SO, OV[32] and CA[32]) are only modified by instructions that are
 407         -- handled here, we can just forward the result being sent to
 408         -- writeback.
 409         if r.e.write_xerc_enable = '1' or r.busy = '1' then
 410             v.e.xerc := r.e.xerc;
 411         else
 412             v.e.xerc := e_in.xerc;
 413         end if;
 414
 415         -- CR forwarding
 416         cr_in <= e_in.cr;
 417         if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
 418             for i in 0 to 7 loop
 419                 if r.e.write_cr_mask(i) = '1' then
 420                     cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
 421                 end if;
 422             end loop;
 423         end if;
 424
 425         v.mul_in_progress := '0';
 426         v.div_in_progress := '0';
 427         v.cntz_in_progress := '0';
 428         v.mul_finish := '0';
 429
 430         spr_result <= (others => '0');
 431         spr_val := (others => '0');
 432
 433         -- Main adder
 434         if e_in.invert_a = '0' then
 435             a_inv := a_in;
 436         else
 437             a_inv := not a_in;
 438         end if;
 439         if e_in.addm1 = '0' then
 440             b_or_m1 := b_in;
 441         else
 442             b_or_m1 := (others => '1');
 443         end if;
 444         sum_with_carry := ppc_adde(a_inv, b_or_m1,
 445                                    decode_input_carry(e_in.input_carry, v.e.xerc));
 446         adder_result <= sum_with_carry(63 downto 0);
 447         carry_32 := sum_with_carry(32) xor a_inv(32) xor b_in(32);
 448         carry_64 := sum_with_carry(64);
 449
 450         -- signals to multiply and divide units
 451         sign1 := '0';
 452         sign2 := '0';
 453         if e_in.is_signed = '1' then
 454             if e_in.is_32bit = '1' then
 455                 sign1 := a_in(31);
 456                 sign2 := b_in(31);
 457             else
 458                 sign1 := a_in(63);
 459                 sign2 := b_in(63);
 460             end if;
 461         end if;
 462         -- take absolute values
 463         if sign1 = '0' then
 464             abs1 := signed(a_in);
 465         else
 466             abs1 := - signed(a_in);
 467         end if;
 468         if sign2 = '0' then
 469             abs2 := signed(b_in);
 470         else
 471             abs2 := - signed(b_in);
 472         end if;
 473
 474         -- Interface to multiply and divide units
 475         x_to_multiply <= MultiplyInputInit;
 476         x_to_multiply.is_32bit <= e_in.is_32bit;
 477
 478         x_to_divider <= Execute1ToDividerInit;
 479         x_to_divider.is_signed <= e_in.is_signed;
 480         x_to_divider.is_32bit <= e_in.is_32bit;
 481         if e_in.insn_type = OP_MOD then
 482             x_to_divider.is_modulus <= '1';
 483         end if;
 484
 485         addend := (others => '0');
 486         if e_in.insn(26) = '0' then
 487             -- integer multiply-add, major op 4 (if it is a multiply)
 488             addend(63 downto 0) := c_in;
 489             if e_in.is_signed = '1' then
 490                 addend(127 downto 64) := (others => c_in(63));
 491             end if;
 492         end if;
 493         if (sign1 xor sign2) = '1' then
 494             addend := not addend;
 495         end if;
 496
 497         x_to_multiply.not_result <= sign1 xor sign2;
 498         x_to_multiply.addend <= addend;
 499         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 500         if e_in.is_32bit = '0' then
 501             -- 64-bit forms
 502             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 503             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 504             if e_in.insn_type = OP_DIVE then
 505                 x_to_divider.is_extended <= '1';
 506             end if;
 507             x_to_divider.dividend <= std_ulogic_vector(abs1);
 508             x_to_divider.divisor <= std_ulogic_vector(abs2);
 509         else
 510             -- 32-bit forms
 511             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 512             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 513             x_to_divider.is_extended <= '0';
 514             if e_in.insn_type = OP_DIVE then   -- extended forms
 515                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 516             else
 517                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 518             end if;
 519             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 520         end if;
 521
 522         case current.sub_select(1 downto 0) is
 523             when "00" =>
 524                 muldiv_result <= multiply_to_x.result(63 downto 0);
 525             when "01" =>
 526                 muldiv_result <= multiply_to_x.result(127 downto 64);
 527             when "10" =>
 528                 muldiv_result <= multiply_to_x.result(63 downto 32) &
 529                                  multiply_to_x.result(63 downto 32);
 530             when others =>
 531                 muldiv_result <= divider_to_x.write_reg_data;
 532         end case;
 533
 534         -- Compute misc_result
 535         case current.sub_select is
 536             when "000" =>
 537                 misc_result <= (others => '0');
 538             when "001" =>
 539                 -- addg6s
 540                 addg6s := (others => '0');
 541                 for i in 0 to 14 loop
 542                     lo := i * 4;
 543                     hi := (i + 1) * 4;
 544                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 545                         addg6s(lo + 3 downto lo) := "0110";
 546                     end if;
 547                 end loop;
 548                 if sum_with_carry(64) = '0' then
 549                     addg6s(63 downto 60) := "0110";
 550                 end if;
 551                 misc_result <= addg6s;
 552             when "010" =>
 553                 -- isel
 554                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 555                 if cr_in(31-crbit) = '1' then
 556                     isel_result := a_in;
 557                 else
 558                     isel_result := b_in;
 559                 end if;
 560                 misc_result <= isel_result;
 561             when "011" =>
 562                 -- darn
 563                 darn := (others => '1');
 564                 if random_err = '0' then
 565                     case e_in.insn(17 downto 16) is
 566                         when "00" =>
 567                             darn := x"00000000" & random_cond(31 downto 0);
 568                         when "10" =>
 569                             darn := random_raw;
 570                         when others =>
 571                             darn := random_cond;
 572                     end case;
 573                 end if;
 574                 misc_result <= darn;
 575             when "100" =>
 576                 -- mfmsr
 577                 misc_result <= ctrl.msr;
 578             when "101" =>
 579                 if e_in.insn(20) = '0' then
 580                     -- mfcr
 581                     mfcr_result := x"00000000" & cr_in;
 582                 else
 583                     -- mfocrf
 584                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 585                     mfcr_result := (others => '0');
 586                     for i in 0 to 7 loop
 587                         lo := (7-i)*4;
 588                         hi := lo + 3;
 589                         if crnum = i then
 590                             mfcr_result(hi downto lo) := cr_in(hi downto lo);
 591                         end if;
 592                     end loop;
 593                 end if;
 594                 misc_result <= mfcr_result;
 595             when "110" =>
 596                 -- setb
 597                 bfa := insn_bfa(e_in.insn);
 598                 crbit := to_integer(unsigned(bfa)) * 4;
 599                 setb_result := (others => '0');
 600                 if cr_in(31 - crbit) = '1' then
 601                     setb_result := (others => '1');
 602                 elsif cr_in(30 - crbit) = '1' then
 603                     setb_result(0) := '1';
 604                 end if;
 605                 misc_result <= setb_result;
 606             when others =>
 607                 misc_result <= (others => '0');
 608         end case;
 609
 610         -- compute comparison results
 611         -- Note, we have done RB - RA, not RA - RB
 612         if e_in.insn_type = OP_CMP then
 613             l := insn_l(e_in.insn);
 614         else
 615             l := not e_in.is_32bit;
 616         end if;
 617         zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 618         zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 619         if zerolo = '1' and (l = '0' or zerohi = '1') then
 620             -- values are equal
 621             trapval := "00100";
 622         else
 623             a_lt_lo := '0';
 624             a_lt_hi := '0';
 625             if unsigned(a_in(30 downto 0)) < unsigned(b_in(30 downto 0)) then
 626                 a_lt_lo := '1';
 627             end if;
 628             if unsigned(a_in(62 downto 31)) < unsigned(b_in(62 downto 31)) then
 629                 a_lt_hi := '1';
 630             end if;
 631             if l = '1' then
 632                 -- 64-bit comparison
 633                 msb_a := a_in(63);
 634                 msb_b := b_in(63);
 635                 a_lt := a_lt_hi or (zerohi and (a_in(31) xnor b_in(31)) and a_lt_lo);
 636             else
 637                 -- 32-bit comparison
 638                 msb_a := a_in(31);
 639                 msb_b := b_in(31);
 640                 a_lt := a_lt_lo;
 641             end if;
 642             if msb_a /= msb_b then
 643                 -- Comparison is clear from MSB difference.
 644                 -- for signed, 0 is greater; for unsigned, 1 is greater
 645                 trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 646             else
 647                 -- MSBs are equal, so signed and unsigned comparisons give the
 648                 -- same answer.
 649                 trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 650             end if;
 651         end if;
 652
 653         ctrl_tmp <= ctrl;
 654         -- FIXME: run at 512MHz not core freq
 655         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 656         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 657
 658         irq_valid := '0';
 659         if ctrl.msr(MSR_EE) = '1' then
 660             if ctrl.dec(63) = '1' then
 661                 v.vector := 16#900#;
 662                 report "IRQ valid: DEC";
 663                 irq_valid := '1';
 664             elsif ext_irq_in = '1' then
 665                 v.vector := 16#500#;
 666                 report "IRQ valid: External";
 667                 irq_valid := '1';
 668             end if;
 669         end if;
 670
 671         v.terminate := '0';
 672         icache_inval <= '0';
 673         v.busy := '0';
 674
 675         -- Next insn adder used in a couple of places
 676         next_nia <= std_ulogic_vector(unsigned(e_in.nia) + 4);
 677
 678         -- rotator control signals
 679         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 680         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 681         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 682         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 683
 684         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 685         ctrl_tmp.irq_state <= WRITE_SRR0;
 686         exception := '0';
 687         illegal := '0';
 688         exception_nextpc := '0';
 689         v.e.exc_write_enable := '0';
 690         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 691         if valid_in = '1' then
 692             v.e.exc_write_data := e_in.nia;
 693             v.last_nia := e_in.nia;
 694         else
 695             v.e.exc_write_data := r.last_nia;
 696         end if;
 697
 698         v.e.mode_32bit := not ctrl.msr(MSR_SF);
 699         v.e.instr_tag := current.instr_tag;
 700
 701         do_trace := valid_in and ctrl.msr(MSR_SE);
 702         if valid_in = '1' then
 703             v.prev_op := e_in.insn_type;
 704         end if;
 705
 706         -- Determine if there is any exception to be taken
 707         -- before/instead of executing this instruction
 708         if valid_in = '1' and e_in.second = '0' then
 709             if HAS_FPU and r.fp_exception_next = '1' then
 710                 -- This is used for FP-type program interrupts that
 711                 -- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
 712                 exception := '1';
 713                 v.vector := 16#700#;
 714                 ctrl_tmp.srr1(63 - 43) <= '1';
 715                 ctrl_tmp.srr1(63 - 47) <= '1';
 716             elsif r.trace_next = '1' then
 717                 -- Generate a trace interrupt rather than executing the next instruction
 718                 -- or taking any asynchronous interrupt
 719                 exception := '1';
 720                 v.vector := 16#d00#;
 721                 ctrl_tmp.srr1(63 - 33) <= '1';
 722                 if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
 723                     r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
 724                     ctrl_tmp.srr1(63 - 35) <= '1';
 725                 elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
 726                     ctrl_tmp.srr1(63 - 36) <= '1';
 727                 end if;
 728
 729             elsif irq_valid = '1' then
 730                 -- Don't deliver the interrupt until we have a valid instruction
 731                 -- coming in, so we have a valid NIA to put in SRR0.
 732                 exception := '1';
 733
 734             elsif ctrl.msr(MSR_PR) = '1' and instr_is_privileged(e_in.insn_type, e_in.insn) then
 735                 -- generate a program interrupt
 736                 exception := '1';
 737                 v.vector := 16#700#;
 738                 -- set bit 45 to indicate privileged instruction type interrupt
 739                 ctrl_tmp.srr1(63 - 45) <= '1';
 740                 report "privileged instruction";
 741
 742             elsif not HAS_FPU and e_in.fac = FPU then
 743                 -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
 744                 illegal := '1';
 745
 746             elsif HAS_FPU and ctrl.msr(MSR_FP) = '0' and e_in.fac = FPU then
 747                 -- generate a floating-point unavailable interrupt
 748                 exception := '1';
 749                 v.vector := 16#800#;
 750                 report "FP unavailable interrupt";
 751             end if;
 752         end if;
 753
 754         if valid_in = '1' and exception = '0' and illegal = '0' and e_in.unit = ALU then
 755             v.cur_instr := e_in;
 756             v.next_lr := next_nia;
 757             v.e.valid := '1';
 758
 759             case_0: case e_in.insn_type is
 760
 761             when OP_ILLEGAL =>
 762                 -- we need two cycles to write srr0 and 1
 763                 -- will need more when we have to write HEIR
 764                 illegal := '1';
 765             when OP_SC =>
 766                 -- check bit 1 of the instruction is 1 so we know this is sc;
 767                 -- 0 would mean scv, so generate an illegal instruction interrupt
 768                 -- we need two cycles to write srr0 and 1
 769                 if e_in.insn(1) = '1' then
 770                     exception := '1';
 771                     exception_nextpc := '1';
 772                     v.vector := 16#C00#;
 773                     report "sc";
 774                 else
 775                     illegal := '1';
 776                 end if;
 777             when OP_ATTN =>
 778                 -- check bits 1-10 of the instruction to make sure it's attn
 779                 -- if not then it is illegal
 780                 if e_in.insn(10 downto 1) = "0100000000" then
 781                     v.terminate := '1';
 782                     report "ATTN";
 783                 else
 784                     illegal := '1';
 785                 end if;
 786             when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
 787                 -- Do nothing
 788             when OP_ADD =>
 789                 if e_in.output_carry = '1' then
 790                     if e_in.input_carry /= OV then
 791                         set_carry(v.e, carry_32, carry_64);
 792                     else
 793                         v.e.xerc.ov := carry_64;
 794                         v.e.xerc.ov32 := carry_32;
 795                         v.e.write_xerc_enable := '1';
 796                     end if;
 797                 end if;
 798                 if e_in.oe = '1' then
 799                     set_ov(v.e,
 800                            calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
 801                            calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
 802                 end if;
 803             when OP_CMP =>
 804                 -- CMP and CMPL instructions
 805                 if e_in.is_signed = '1' then
 806                     newcrf := trapval(4 downto 2) & v.e.xerc.so;
 807                 else
 808                     newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 809                 end if;
 810                 bf := insn_bf(e_in.insn);
 811                 crnum := to_integer(unsigned(bf));
 812                 v.e.write_cr_enable := '1';
 813                 v.e.write_cr_mask := num_to_fxm(crnum);
 814                 for i in 0 to 7 loop
 815                     lo := i*4;
 816                     hi := lo + 3;
 817                     v.e.write_cr_data(hi downto lo) := newcrf;
 818                 end loop;
 819             when OP_TRAP =>
 820                 -- trap instructions (tw, twi, td, tdi)
 821                 v.vector := 16#700#;
 822                 -- set bit 46 to say trap occurred
 823                 ctrl_tmp.srr1(63 - 46) <= '1';
 824                 if or (trapval and insn_to(e_in.insn)) = '1' then
 825                     -- generate trap-type program interrupt
 826                     exception := '1';
 827                     report "trap";
 828                 end if;
 829             when OP_ADDG6S =>
 830             when OP_CMPRB =>
 831                 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 832                 bf := insn_bf(e_in.insn);
 833                 crnum := to_integer(unsigned(bf));
 834                 v.e.write_cr_enable := '1';
 835                 v.e.write_cr_mask := num_to_fxm(crnum);
 836                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 837                                      newcrf & newcrf & newcrf & newcrf;
 838             when OP_CMPEQB =>
 839                 newcrf := ppc_cmpeqb(a_in, b_in);
 840                 bf := insn_bf(e_in.insn);
 841                 crnum := to_integer(unsigned(bf));
 842                 v.e.write_cr_enable := '1';
 843                 v.e.write_cr_mask := num_to_fxm(crnum);
 844                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 845                                      newcrf & newcrf & newcrf & newcrf;
 846             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 847                     OP_BPERM | OP_BCD =>
 848
 849             when OP_B =>
 850                 is_branch := '1';
 851                 taken_branch := '1';
 852                 is_direct_branch := '1';
 853                 abs_branch := e_in.br_abs;
 854                 if ctrl.msr(MSR_BE) = '1' then
 855                     do_trace := '1';
 856                 end if;
 857             when OP_BC | OP_BCREG =>
 858                 -- read_data1 is CTR
 859                 -- for OP_BCREG, read_data2 is target register (CTR, LR or TAR)
 860                 -- If this instruction updates both CTR and LR, then it is
 861                 -- doubled; the first instruction decrements CTR and determines
 862                 -- whether the branch is taken, and the second does the
 863                 -- redirect and the LR update.
 864                 bo := insn_bo(e_in.insn);
 865                 bi := insn_bi(e_in.insn);
 866                 if e_in.second = '0' then
 867                     taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 868                 else
 869                     taken_branch := r.br_taken;
 870                 end if;
 871                 v.br_taken := taken_branch;
 872                 abs_branch := e_in.br_abs;
 873                 if e_in.repeat = '0' or e_in.second = '1' then
 874                     is_branch := '1';
 875                     if e_in.insn_type = OP_BC then
 876                         is_direct_branch := '1';
 877                     end if;
 878                     if ctrl.msr(MSR_BE) = '1' then
 879                         do_trace := '1';
 880                     end if;
 881                 end if;
 882
 883             when OP_RFID =>
 884                 v.redir_mode := (a_in(MSR_IR) or a_in(MSR_PR)) & not a_in(MSR_PR) &
 885                                 not a_in(MSR_LE) & not a_in(MSR_SF);
 886                 -- Can't use msr_copy here because the partial function MSR
 887                 -- bits should be left unchanged, not zeroed.
 888                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 889                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 890                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 891                 if a_in(MSR_PR) = '1' then
 892                     ctrl_tmp.msr(MSR_EE) <= '1';
 893                     ctrl_tmp.msr(MSR_IR) <= '1';
 894                     ctrl_tmp.msr(MSR_DR) <= '1';
 895                 end if;
 896                 -- mark this as a branch so CFAR gets updated
 897                 is_branch := '1';
 898                 taken_branch := '1';
 899                 abs_branch := '1';
 900                 if HAS_FPU then
 901                     v.fp_exception_next := fp_in.exception and
 902                                            (a_in(MSR_FE0) or a_in(MSR_FE1));
 903                 end if;
 904                 do_trace := '0';
 905
 906             when OP_CNTZ =>
 907                 v.e.valid := '0';
 908                 v.cntz_in_progress := '1';
 909                 v.busy := '1';
 910             when OP_ISEL =>
 911             when OP_CROP =>
 912                 cr_op := insn_cr(e_in.insn);
 913                 if cr_op(0) = '0' then -- MCRF
 914                     bf := insn_bf(e_in.insn);
 915                     bfa := insn_bfa(e_in.insn);
 916                     v.e.write_cr_enable := '1';
 917                     crnum := to_integer(unsigned(bf));
 918                     scrnum := to_integer(unsigned(bfa));
 919                     v.e.write_cr_mask := num_to_fxm(crnum);
 920                     for i in 0 to 7 loop
 921                         lo := (7-i)*4;
 922                         hi := lo + 3;
 923                         if i = scrnum then
 924                             newcrf := cr_in(hi downto lo);
 925                         end if;
 926                     end loop;
 927                     for i in 0 to 7 loop
 928                         lo := i*4;
 929                         hi := lo + 3;
 930                         v.e.write_cr_data(hi downto lo) := newcrf;
 931                     end loop;
 932                 else
 933                     v.e.write_cr_enable := '1';
 934                     bt := insn_bt(e_in.insn);
 935                     ba := insn_ba(e_in.insn);
 936                     bb := insn_bb(e_in.insn);
 937                     btnum := 31 - to_integer(unsigned(bt));
 938                     banum := 31 - to_integer(unsigned(ba));
 939                     bbnum := 31 - to_integer(unsigned(bb));
 940                     -- Bits 5-8 of cr_op give the truth table of the requested
 941                     -- logical operation
 942                     cr_operands := cr_in(banum) & cr_in(bbnum);
 943                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 944                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 945                     for i in 0 to 31 loop
 946                         if i = btnum then
 947                             v.e.write_cr_data(i) := crresult;
 948                         else
 949                             v.e.write_cr_data(i) := cr_in(i);
 950                         end if;
 951                     end loop;
 952                 end if;
 953             when OP_MCRXRX =>
 954                 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
 955                 bf := insn_bf(e_in.insn);
 956                 crnum := to_integer(unsigned(bf));
 957                 v.e.write_cr_enable := '1';
 958                 v.e.write_cr_mask := num_to_fxm(crnum);
 959                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 960                                      newcrf & newcrf & newcrf & newcrf;
 961             when OP_DARN =>
 962             when OP_MFMSR =>
 963             when OP_MFSPR =>
 964                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 965                     "=" & to_hstring(a_in);
 966                 if is_fast_spr(e_in.read_reg1) = '1' then
 967                     spr_val := a_in;
 968                     if decode_spr_num(e_in.insn) = SPR_XER then
 969                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 970                         spr_val(63 downto 32) := (others => '0');
 971                         spr_val(63-32) := v.e.xerc.so;
 972                         spr_val(63-33) := v.e.xerc.ov;
 973                         spr_val(63-34) := v.e.xerc.ca;
 974                         spr_val(63-35 downto 63-43) := "000000000";
 975                         spr_val(63-44) := v.e.xerc.ov32;
 976                         spr_val(63-45) := v.e.xerc.ca32;
 977                     end if;
 978                 else
 979                     spr_val := c_in;
 980                     case decode_spr_num(e_in.insn) is
 981                     when SPR_TB =>
 982                         spr_val := ctrl.tb;
 983                     when SPR_TBU =>
 984                         spr_val(63 downto 32) := (others => '0');
 985                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 986                     when SPR_DEC =>
 987                         spr_val := ctrl.dec;
 988                     when SPR_CFAR =>
 989                         spr_val := ctrl.cfar;
 990                     when SPR_PVR =>
 991                         spr_val(63 downto 32) := (others => '0');
 992                         spr_val(31 downto 0) := PVR_MICROWATT;
 993                     when 724 =>     -- LOG_ADDR SPR
 994                         spr_val := log_wr_addr & r.log_addr_spr;
 995                     when 725 =>     -- LOG_DATA SPR
 996                         spr_val := log_rd_data;
 997                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 998                     when others =>
 999                         -- mfspr from unimplemented SPRs should be a nop in
1000                         -- supervisor mode and a program interrupt for user mode
1001                         if is_fast_spr(e_in.read_reg1) = '0' and ctrl.msr(MSR_PR) = '1' then
1002                             illegal := '1';
1003                         end if;
1004                     end case;
1005                 end if;
1006                 spr_result <= spr_val;
1007
1008             when OP_MFCR =>
1009             when OP_MTCRF =>
1010                 v.e.write_cr_enable := '1';
1011                 if e_in.insn(20) = '0' then
1012                     -- mtcrf
1013                     v.e.write_cr_mask := insn_fxm(e_in.insn);
1014                 else
1015                     -- mtocrf: We require one hot priority encoding here
1016                     crnum := fxm_to_num(insn_fxm(e_in.insn));
1017                     v.e.write_cr_mask := num_to_fxm(crnum);
1018                 end if;
1019                 v.e.write_cr_data := c_in(31 downto 0);
1020             when OP_MTMSRD =>
1021                 if e_in.insn(16) = '1' then
1022                     -- just update EE and RI
1023                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
1024                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
1025                 else
1026                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
1027                     -- and 63 (LE) (IBM bit numbering)
1028                     if e_in.is_32bit = '0' then
1029                         ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
1030                         ctrl_tmp.msr(59 downto 32) <= c_in(59 downto 32);
1031                     end if;
1032                     ctrl_tmp.msr(31 downto 13) <= c_in(31 downto 13);
1033                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
1034                     if c_in(MSR_PR) = '1' then
1035                         ctrl_tmp.msr(MSR_EE) <= '1';
1036                         ctrl_tmp.msr(MSR_IR) <= '1';
1037                         ctrl_tmp.msr(MSR_DR) <= '1';
1038                     end if;
1039                     if HAS_FPU then
1040                         v.fp_exception_next := fp_in.exception and
1041                                                (c_in(MSR_FE0) or c_in(MSR_FE1));
1042                     end if;
1043                 end if;
1044             when OP_MTSPR =>
1045                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
1046                     "=" & to_hstring(c_in);
1047                 if is_fast_spr(e_in.write_reg) then
1048                     if decode_spr_num(e_in.insn) = SPR_XER then
1049                         v.e.xerc.so := c_in(63-32);
1050                         v.e.xerc.ov := c_in(63-33);
1051                         v.e.xerc.ca := c_in(63-34);
1052                         v.e.xerc.ov32 := c_in(63-44);
1053                         v.e.xerc.ca32 := c_in(63-45);
1054                         v.e.write_xerc_enable := '1';
1055                     end if;
1056                 else
1057                     -- slow spr
1058                     case decode_spr_num(e_in.insn) is
1059                     when SPR_DEC =>
1060                         ctrl_tmp.dec <= c_in;
1061                     when 724 =>     -- LOG_ADDR SPR
1062                         v.log_addr_spr := c_in(31 downto 0);
1063                     when others =>
1064                         -- mtspr to unimplemented SPRs should be a nop in
1065                         -- supervisor mode and a program interrupt for user mode
1066                         if ctrl.msr(MSR_PR) = '1' then
1067                             illegal := '1';
1068                         end if;
1069                     end case;
1070                 end if;
1071             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
1072                 if e_in.output_carry = '1' then
1073                     set_carry(v.e, rotator_carry, rotator_carry);
1074                 end if;
1075             when OP_SETB =>
1076
1077             when OP_ISYNC =>
1078                 v.redirect := '1';
1079                 v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1080
1081             when OP_ICBI =>
1082                 icache_inval <= '1';
1083
1084             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1085                 v.e.valid := '0';
1086                 v.mul_in_progress := '1';
1087                 v.busy := '1';
1088                 x_to_multiply.valid <= '1';
1089
1090             when OP_DIV | OP_DIVE | OP_MOD =>
1091                 v.e.valid := '0';
1092                 v.div_in_progress := '1';
1093                 v.busy := '1';
1094                 x_to_divider.valid <= '1';
1095
1096             when others =>
1097                 v.terminate := '1';
1098                 report "illegal";
1099             end case;
1100
1101             -- Mispredicted branches cause a redirect
1102             if is_branch = '1' then
1103                 if taken_branch = '1' then
1104                     ctrl_tmp.cfar <= e_in.nia;
1105                 end if;
1106                 if taken_branch = '1' then
1107                     v.br_offset := b_in;
1108                     v.abs_br := abs_branch;
1109                 else
1110                     v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1111                 end if;
1112                 if taken_branch /= e_in.br_pred then
1113                     v.redirect := '1';
1114                 end if;
1115                 v.br_last := is_direct_branch;
1116                 v.taken_br := taken_branch;
1117             end if;
1118
1119         elsif valid_in = '1' and exception = '0' and illegal = '0' then
1120             -- instruction for other units, i.e. LDST
1121             if e_in.unit = LDST then
1122                 lv.valid := '1';
1123             elsif e_in.unit = NONE then
1124                 illegal := '1';
1125             elsif HAS_FPU and e_in.unit = FPU then
1126                 fv.valid := '1';
1127             end if;
1128             -- Handling an ITLB miss doesn't count as having executed an instruction
1129             if e_in.insn_type = OP_FETCH_FAILED then
1130                 do_trace := '0';
1131             end if;
1132         end if;
1133
1134         -- The following cases all occur when r.busy = 1 and therefore
1135         -- valid_in = 0.  Hence they don't happen in the same cycle as any of
1136         -- the cases above which depend on valid_in = 1.
1137
1138         if ctrl.irq_state = WRITE_SRR1 then
1139             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
1140             v.e.exc_write_data := ctrl.srr1;
1141             v.e.exc_write_enable := '1';
1142             ctrl_tmp.msr(MSR_SF) <= '1';
1143             ctrl_tmp.msr(MSR_EE) <= '0';
1144             ctrl_tmp.msr(MSR_PR) <= '0';
1145             ctrl_tmp.msr(MSR_SE) <= '0';
1146             ctrl_tmp.msr(MSR_BE) <= '0';
1147             ctrl_tmp.msr(MSR_FP) <= '0';
1148             ctrl_tmp.msr(MSR_FE0) <= '0';
1149             ctrl_tmp.msr(MSR_FE1) <= '0';
1150             ctrl_tmp.msr(MSR_IR) <= '0';
1151             ctrl_tmp.msr(MSR_DR) <= '0';
1152             ctrl_tmp.msr(MSR_RI) <= '0';
1153             ctrl_tmp.msr(MSR_LE) <= '1';
1154             v.trace_next := '0';
1155             v.fp_exception_next := '0';
1156             report "Writing SRR1: " & to_hstring(ctrl.srr1);
1157
1158         elsif r.cntz_in_progress = '1' then
1159             -- cnt[lt]z always takes two cycles
1160             v.e.valid := '1';
1161         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1162             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1163                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1164                 if r.mul_in_progress = '1' then
1165                     overflow := '0';
1166                 else
1167                     overflow := divider_to_x.overflow;
1168                 end if;
1169                 if r.mul_in_progress = '1' and current.oe = '1' then
1170                     -- have to wait until next cycle for overflow indication
1171                     v.mul_finish := '1';
1172                     v.busy := '1';
1173                 else
1174                     v.e.write_xerc_enable := current.oe;
1175                     -- We must test oe because the RC update code in writeback
1176                     -- will use the xerc value to set CR0:SO so we must not clobber
1177                     -- xerc if OE wasn't set.
1178                     if current.oe = '1' then
1179                         v.e.xerc.ov := overflow;
1180                         v.e.xerc.ov32 := overflow;
1181                         if overflow = '1' then
1182                             v.e.xerc.so := '1';
1183                         end if;
1184                     end if;
1185                     v.e.valid := '1';
1186                 end if;
1187             else
1188                 v.busy := '1';
1189                 v.mul_in_progress := r.mul_in_progress;
1190                 v.div_in_progress := r.div_in_progress;
1191             end if;
1192         elsif r.mul_finish = '1' then
1193             hold_wr_data := '1';
1194             v.e.write_xerc_enable := current.oe;
1195             v.e.xerc.ov := multiply_to_x.overflow;
1196             v.e.xerc.ov32 := multiply_to_x.overflow;
1197             if multiply_to_x.overflow = '1' then
1198                 v.e.xerc.so := '1';
1199             end if;
1200             v.e.valid := '1';
1201         end if;
1202
1203         -- Generate FP-type program interrupt.  fp_in.interrupt will only
1204         -- be set during the execution of a FP instruction.
1205         -- The case where MSR[FE0,FE1] goes from zero to non-zero is
1206         -- handled above by mtmsrd and rfid setting v.fp_exception_next.
1207         if HAS_FPU and fp_in.interrupt = '1' then
1208             v.vector := 16#700#;
1209             ctrl_tmp.srr1(63 - 43) <= '1';
1210             exception := '1';
1211         end if;
1212
1213         if illegal = '1' or (HAS_FPU and fp_in.illegal = '1') then
1214             exception := '1';
1215             v.vector := 16#700#;
1216             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1217             -- set bit 44 to indicate we have an illegal
1218             ctrl_tmp.srr1(63 - 44) <= '1';
1219             report "illegal";
1220         end if;
1221         if exception = '1' then
1222             v.e.exc_write_enable := '1';
1223             if exception_nextpc = '1' then
1224                 v.e.exc_write_data := next_nia;
1225             end if;
1226         end if;
1227
1228         -- generate DSI or DSegI for load/store exceptions
1229         -- or ISI or ISegI for instruction fetch exceptions
1230         if l_in.exception = '1' then
1231             if l_in.alignment = '1' then
1232                 v.vector := 16#600#;
1233             elsif l_in.instr_fault = '0' then
1234                 if l_in.segment_fault = '0' then
1235                     v.vector := 16#300#;
1236                 else
1237                     v.vector := 16#380#;
1238                 end if;
1239             else
1240                 if l_in.segment_fault = '0' then
1241                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1242                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1243                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1244                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1245                     v.vector := 16#400#;
1246                 else
1247                     v.vector := 16#480#;
1248                 end if;
1249             end if;
1250             v.e.exc_write_enable := '1';
1251             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1252             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1253         end if;
1254
1255         if exception = '1' or l_in.exception = '1' then
1256             ctrl_tmp.irq_state <= WRITE_SRR1;
1257             v.redirect := '1';
1258             v.do_intr := '1';
1259         end if;
1260
1261         if do_trace = '1' then
1262             v.trace_next := '1';
1263         end if;
1264
1265         if hold_wr_data = '0' then
1266             v.e.write_data := alu_result;
1267         else
1268             v.e.write_data := r.e.write_data;
1269         end if;
1270         v.e.write_reg := current.write_reg;
1271         v.e.write_enable := current.write_reg_enable and v.e.valid and not exception;
1272         v.e.rc := current.rc and v.e.valid and not exception;
1273
1274         bypass_data.tag.valid <= current.instr_tag.valid and current.write_reg_enable and v.e.valid;
1275         bypass_data.tag.tag <= current.instr_tag.tag;
1276         bypass_data.data <= v.e.write_data;
1277
1278         -- Defer completion for one cycle when redirecting.
1279         -- This also ensures r.busy = 1 when ctrl.irq_state = WRITE_SRR1
1280         if v.redirect = '1' then
1281             v.busy := '1';
1282             v.e.valid := '0';
1283         end if;
1284         if r.redirect = '1' then
1285             v.e.valid := '1';
1286         end if;
1287
1288         -- Outputs to fetch1
1289         f.redirect := r.redirect;
1290         f.br_nia := r.last_nia;
1291         f.br_last := r.br_last and not r.do_intr;
1292         f.br_taken := r.taken_br;
1293         if r.do_intr = '1' then
1294             f.redirect_nia := std_ulogic_vector(to_unsigned(r.vector, 64));
1295             f.virt_mode := '0';
1296             f.priv_mode := '1';
1297             -- XXX need an interrupt LE bit here, e.g. from LPCR
1298             f.big_endian := '0';
1299             f.mode_32bit := '0';
1300         else
1301             if r.abs_br = '1' then
1302                 f.redirect_nia := r.br_offset;
1303             else
1304                 f.redirect_nia := std_ulogic_vector(unsigned(r.last_nia) + unsigned(r.br_offset));
1305             end if;
1306             -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
1307             f.virt_mode := r.redir_mode(3);
1308             f.priv_mode := r.redir_mode(2);
1309             f.big_endian := r.redir_mode(1);
1310             f.mode_32bit := r.redir_mode(0);
1311         end if;
1312
1313         -- Outputs to loadstore1 (async)
1314         lv.op := e_in.insn_type;
1315         lv.nia := e_in.nia;
1316         lv.instr_tag := e_in.instr_tag;
1317         lv.addr1 := a_in;
1318         lv.addr2 := b_in;
1319         lv.data := c_in;
1320         lv.write_reg := e_in.write_reg;
1321         lv.length := e_in.data_len;
1322         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1323         lv.sign_extend := e_in.sign_extend;
1324         lv.update := e_in.update;
1325         lv.xerc := v.e.xerc;
1326         lv.reserve := e_in.reserve;
1327         lv.rc := e_in.rc;
1328         lv.insn := e_in.insn;
1329         -- decode l*cix and st*cix instructions here
1330         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1331             e_in.insn(5 downto 1) = "10101" then
1332             lv.ci := '1';
1333         end if;
1334         lv.virt_mode := ctrl.msr(MSR_DR);
1335         lv.priv_mode := not ctrl.msr(MSR_PR);
1336         lv.mode_32bit := not ctrl.msr(MSR_SF);
1337         lv.is_32bit := e_in.is_32bit;
1338         lv.repeat := e_in.repeat;
1339         lv.second := e_in.second;
1340
1341         -- Outputs to FPU
1342         fv.op := e_in.insn_type;
1343         fv.nia := e_in.nia;
1344         fv.insn := e_in.insn;
1345         fv.itag := e_in.instr_tag;
1346         fv.single := e_in.is_32bit;
1347         fv.fe_mode := ctrl.msr(MSR_FE0) & ctrl.msr(MSR_FE1);
1348         fv.fra := a_in;
1349         fv.frb := b_in;
1350         fv.frc := c_in;
1351         fv.frt := e_in.write_reg;
1352         fv.rc := e_in.rc;
1353         fv.out_cr := e_in.output_cr;
1354
1355         -- Update registers
1356         rin <= v;
1357
1358         -- update outputs
1359         f_out <= f;
1360         l_out <= lv;
1361         e_out <= r.e;
1362         fp_out <= fv;
1363         flush_out <= f_out.redirect;
1364
1365         exception_log <= exception;
1366         irq_valid_log <= irq_valid;
1367     end process;
1368
1369     e1_log: if LOG_LENGTH > 0 generate
1370         signal log_data : std_ulogic_vector(14 downto 0);
1371     begin
1372         ex1_log : process(clk)
1373         begin
1374             if rising_edge(clk) then
1375                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1376                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1377                             exception_log &
1378                             irq_valid_log &
1379                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1380                             "000" &
1381                             r.e.write_enable &
1382                             r.e.valid &
1383                             f_out.redirect &
1384                             r.busy &
1385                             flush_out;
1386             end if;
1387         end process;
1388         log_out <= log_data;
1389     end generate;
1390 end architecture behaviour;