execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         HAS_FPU : boolean := true;
  17         -- Non-zero to enable log data collection
  18         LOG_LENGTH : natural := 0
  19         );
  20     port (
  21         clk   : in std_ulogic;
  22         rst   : in std_ulogic;
  23
  24         -- asynchronous
  25         flush_out : out std_ulogic;
  26         busy_out : out std_ulogic;
  27
  28         e_in  : in Decode2ToExecute1Type;
  29         l_in  : in Loadstore1ToExecute1Type;
  30         fp_in : in FPUToExecute1Type;
  31
  32         ext_irq_in : std_ulogic;
  33
  34         -- asynchronous
  35         l_out : out Execute1ToLoadstore1Type;
  36         f_out : out Execute1ToFetch1Type;
  37         fp_out : out Execute1ToFPUType;
  38
  39         e_out : out Execute1ToWritebackType;
  40         bypass_data : out bypass_data_t;
  41         bypass_cr_data : out cr_bypass_data_t;
  42
  43         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  44
  45         icache_inval : out std_ulogic;
  46         terminate_out : out std_ulogic;
  47
  48         log_out : out std_ulogic_vector(14 downto 0);
  49         log_rd_addr : out std_ulogic_vector(31 downto 0);
  50         log_rd_data : in std_ulogic_vector(63 downto 0);
  51         log_wr_addr : in std_ulogic_vector(31 downto 0)
  52         );
  53 end entity execute1;
  54
  55 architecture behaviour of execute1 is
  56     type reg_type is record
  57         e : Execute1ToWritebackType;
  58         cur_instr : Decode2ToExecute1Type;
  59         busy: std_ulogic;
  60         terminate: std_ulogic;
  61         fp_exception_next : std_ulogic;
  62         trace_next : std_ulogic;
  63         prev_op : insn_type_t;
  64         next_lr : std_ulogic_vector(63 downto 0);
  65         br_taken : std_ulogic;
  66         mul_in_progress : std_ulogic;
  67         mul_finish : std_ulogic;
  68         div_in_progress : std_ulogic;
  69         cntz_in_progress : std_ulogic;
  70         last_nia : std_ulogic_vector(63 downto 0);
  71         redirect : std_ulogic;
  72         abs_br : std_ulogic;
  73         taken_br : std_ulogic;
  74         br_last : std_ulogic;
  75         do_intr : std_ulogic;
  76         vector : integer range 0 to 16#fff#;
  77         br_offset : std_ulogic_vector(63 downto 0);
  78         redir_mode : std_ulogic_vector(3 downto 0);
  79         log_addr_spr : std_ulogic_vector(31 downto 0);
  80     end record;
  81     constant reg_type_init : reg_type :=
  82         (e => Execute1ToWritebackInit,
  83          cur_instr => Decode2ToExecute1Init,
  84          busy => '0', terminate => '0',
  85          fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL, br_taken => '0',
  86          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  87          next_lr => (others => '0'), last_nia => (others => '0'),
  88          redirect => '0', abs_br => '0', taken_br => '0', br_last => '0', do_intr => '0', vector => 0,
  89          br_offset => (others => '0'), redir_mode => "0000",
  90          others => (others => '0'));
  91
  92     signal r, rin : reg_type;
  93
  94     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  95     signal cr_in : std_ulogic_vector(31 downto 0);
  96     signal xerc_in : xer_common_t;
  97
  98     signal valid_in : std_ulogic;
  99     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
 100     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
 101     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
 102     signal rot_sign_ext: std_ulogic;
 103     signal rotator_result: std_ulogic_vector(63 downto 0);
 104     signal rotator_carry: std_ulogic;
 105     signal logical_result: std_ulogic_vector(63 downto 0);
 106     signal countzero_result: std_ulogic_vector(63 downto 0);
 107     signal alu_result: std_ulogic_vector(63 downto 0);
 108     signal adder_result: std_ulogic_vector(63 downto 0);
 109     signal misc_result: std_ulogic_vector(63 downto 0);
 110     signal muldiv_result: std_ulogic_vector(63 downto 0);
 111     signal spr_result: std_ulogic_vector(63 downto 0);
 112     signal result_mux_sel: std_ulogic_vector(2 downto 0);
 113     signal sub_mux_sel: std_ulogic_vector(2 downto 0);
 114     signal next_nia : std_ulogic_vector(63 downto 0);
 115     signal current: Decode2ToExecute1Type;
 116
 117     signal carry_32 : std_ulogic;
 118     signal carry_64 : std_ulogic;
 119     signal overflow_32 : std_ulogic;
 120     signal overflow_64 : std_ulogic;
 121
 122     signal cmprb_result : std_ulogic_vector(3 downto 0);
 123     signal cmpeqb_result : std_ulogic_vector(3 downto 0);
 124     signal trapval : std_ulogic_vector(4 downto 0);
 125
 126     -- multiply signals
 127     signal x_to_multiply: MultiplyInputType;
 128     signal multiply_to_x: MultiplyOutputType;
 129
 130     -- divider signals
 131     signal x_to_divider: Execute1ToDividerType;
 132     signal divider_to_x: DividerToExecute1Type;
 133
 134     -- random number generator signals
 135     signal random_raw  : std_ulogic_vector(63 downto 0);
 136     signal random_cond : std_ulogic_vector(63 downto 0);
 137     signal random_err  : std_ulogic;
 138
 139     -- signals for logging
 140     signal exception_log : std_ulogic;
 141     signal irq_valid_log : std_ulogic;
 142
 143     type privilege_level is (USER, SUPER);
 144     type op_privilege_array is array(insn_type_t) of privilege_level;
 145     constant op_privilege: op_privilege_array := (
 146         OP_ATTN => SUPER,
 147         OP_MFMSR => SUPER,
 148         OP_MTMSRD => SUPER,
 149         OP_RFID => SUPER,
 150         OP_TLBIE => SUPER,
 151         others => USER
 152         );
 153
 154     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 155         return boolean is
 156     begin
 157         if op_privilege(op) = SUPER then
 158             return true;
 159         elsif op = OP_MFSPR or op = OP_MTSPR then
 160             return insn(20) = '1';
 161         else
 162             return false;
 163         end if;
 164     end;
 165
 166     procedure set_carry(e: inout Execute1ToWritebackType;
 167                         carry32 : in std_ulogic;
 168                         carry : in std_ulogic) is
 169     begin
 170         e.xerc.ca32 := carry32;
 171         e.xerc.ca := carry;
 172         e.write_xerc_enable := '1';
 173     end;
 174
 175     procedure set_ov(e: inout Execute1ToWritebackType;
 176                      ov   : in std_ulogic;
 177                      ov32 : in std_ulogic) is
 178     begin
 179         e.xerc.ov32 := ov32;
 180         e.xerc.ov := ov;
 181         if ov = '1' then
 182             e.xerc.so := '1';
 183         end if;
 184         e.write_xerc_enable := '1';
 185     end;
 186
 187     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 188                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 189     begin
 190         return (ca xor msb_r) and not (msb_a xor msb_b);
 191     end;
 192
 193     function decode_input_carry(ic : carry_in_t;
 194                                 xerc : xer_common_t) return std_ulogic is
 195     begin
 196         case ic is
 197         when ZERO =>
 198             return '0';
 199         when CA =>
 200             return xerc.ca;
 201         when OV =>
 202             return xerc.ov;
 203         when ONE =>
 204             return '1';
 205         end case;
 206     end;
 207
 208     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 209         return std_ulogic_vector is
 210         variable msr_out: std_ulogic_vector(63 downto 0);
 211     begin
 212         -- ISA says this:
 213         --  Defined MSR bits are classified as either full func-
 214         --  tion or partial function. Full function MSR bits are
 215         --  saved in SRR1 or HSRR1 when an interrupt other
 216         --  than a System Call Vectored interrupt occurs and
 217         --  restored by rfscv, rfid, or hrfid, while partial func-
 218         --  tion MSR bits are not saved or restored.
 219         --  Full function MSR bits lie in the range 0:32, 37:41, and
 220         --  48:63, and partial function MSR bits lie in the range
 221         --  33:36 and 42:47. (Note this is IBM bit numbering).
 222         msr_out := (others => '0');
 223         msr_out(63 downto 31) := msr(63 downto 31);
 224         msr_out(26 downto 22) := msr(26 downto 22);
 225         msr_out(15 downto 0)  := msr(15 downto 0);
 226         return msr_out;
 227     end;
 228
 229     -- Tell vivado to keep the hierarchy for the random module so that the
 230     -- net names in the xdc file match.
 231     attribute keep_hierarchy : string;
 232     attribute keep_hierarchy of random_0 : label is "yes";
 233
 234 begin
 235
 236     rotator_0: entity work.rotator
 237         port map (
 238             rs => c_in,
 239             ra => a_in,
 240             shift => b_in(6 downto 0),
 241             insn => e_in.insn,
 242             is_32bit => e_in.is_32bit,
 243             right_shift => right_shift,
 244             arith => e_in.is_signed,
 245             clear_left => rot_clear_left,
 246             clear_right => rot_clear_right,
 247             sign_ext_rs => rot_sign_ext,
 248             result => rotator_result,
 249             carry_out => rotator_carry
 250             );
 251
 252     logical_0: entity work.logical
 253         port map (
 254             rs => c_in,
 255             rb => b_in,
 256             op => e_in.insn_type,
 257             invert_in => e_in.invert_a,
 258             invert_out => e_in.invert_out,
 259             result => logical_result,
 260             datalen => e_in.data_len
 261             );
 262
 263     countzero_0: entity work.zero_counter
 264         port map (
 265             clk => clk,
 266             rs => c_in,
 267             count_right => e_in.insn(10),
 268             is_32bit => e_in.is_32bit,
 269             result => countzero_result
 270             );
 271
 272     multiply_0: entity work.multiply
 273         port map (
 274             clk => clk,
 275             m_in => x_to_multiply,
 276             m_out => multiply_to_x
 277             );
 278
 279     divider_0: entity work.divider
 280         port map (
 281             clk => clk,
 282             rst => rst,
 283             d_in => x_to_divider,
 284             d_out => divider_to_x
 285             );
 286
 287     random_0: entity work.random
 288         port map (
 289             clk => clk,
 290             data => random_cond,
 291             raw => random_raw,
 292             err => random_err
 293             );
 294
 295     dbg_msr_out <= ctrl.msr;
 296     log_rd_addr <= r.log_addr_spr;
 297
 298     a_in <= e_in.read_data1;
 299     b_in <= e_in.read_data2;
 300     c_in <= e_in.read_data3;
 301     cr_in <= e_in.cr;
 302
 303     -- XER forwarding. To avoid having to track XER hazards, we use
 304     -- the previously latched value.  Since the XER common bits
 305     -- (SO, OV[32] and CA[32]) are only modified by instructions that are
 306     -- handled here, we can just forward the result being sent to
 307     -- writeback.
 308     xerc_in <= r.e.xerc when r.e.write_xerc_enable = '1' or r.busy = '1' else e_in.xerc;
 309
 310     busy_out <= l_in.busy or r.busy or fp_in.busy;
 311     valid_in <= e_in.valid and not busy_out;
 312
 313     terminate_out <= r.terminate;
 314
 315     current <= e_in when r.busy = '0' else r.cur_instr;
 316
 317     -- Result mux
 318     with current.result_sel select alu_result <=
 319         adder_result       when "000",
 320         logical_result     when "001",
 321         rotator_result     when "010",
 322         muldiv_result      when "011",
 323         countzero_result   when "100",
 324         spr_result         when "101",
 325         next_nia           when "110",
 326         misc_result        when others;
 327
 328     execute1_0: process(clk)
 329     begin
 330         if rising_edge(clk) then
 331             if rst = '1' then
 332                 r <= reg_type_init;
 333                 ctrl.tb <= (others => '0');
 334                 ctrl.dec <= (others => '0');
 335                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 336                 ctrl.irq_state <= WRITE_SRR0;
 337             else
 338                 r <= rin;
 339                 ctrl <= ctrl_tmp;
 340                 if valid_in = '1' then
 341                     report "execute " & to_hstring(e_in.nia) & " op=" & insn_type_t'image(e_in.insn_type) &
 342                         " wr=" & to_hstring(rin.e.write_reg) & " we=" & std_ulogic'image(rin.e.write_enable) &
 343                         " tag=" & integer'image(rin.e.instr_tag.tag) & std_ulogic'image(rin.e.instr_tag.valid);
 344                 end if;
 345             end if;
 346         end if;
 347     end process;
 348
 349     -- Data path for integer instructions
 350     execute1_dp: process(all)
 351         variable a_inv : std_ulogic_vector(63 downto 0);
 352         variable b_or_m1 : std_ulogic_vector(63 downto 0);
 353         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 354         variable sign1, sign2 : std_ulogic;
 355         variable abs1, abs2 : signed(63 downto 0);
 356         variable addend : std_ulogic_vector(127 downto 0);
 357         variable addg6s : std_ulogic_vector(63 downto 0);
 358         variable crbit : integer range 0 to 31;
 359         variable isel_result : std_ulogic_vector(63 downto 0);
 360         variable darn : std_ulogic_vector(63 downto 0);
 361         variable setb_result : std_ulogic_vector(63 downto 0);
 362         variable mfcr_result : std_ulogic_vector(63 downto 0);
 363         variable crnum : crnum_t;
 364         variable lo, hi : integer;
 365         variable l : std_ulogic;
 366         variable zerohi, zerolo : std_ulogic;
 367         variable msb_a, msb_b : std_ulogic;
 368         variable a_lt : std_ulogic;
 369         variable a_lt_lo : std_ulogic;
 370         variable a_lt_hi : std_ulogic;
 371         variable bfa : std_ulogic_vector(2 downto 0);
 372     begin
 373         -- Main adder
 374         if e_in.invert_a = '0' then
 375             a_inv := a_in;
 376         else
 377             a_inv := not a_in;
 378         end if;
 379         if e_in.addm1 = '0' then
 380             b_or_m1 := b_in;
 381         else
 382             b_or_m1 := (others => '1');
 383         end if;
 384         sum_with_carry := ppc_adde(a_inv, b_or_m1,
 385                                    decode_input_carry(e_in.input_carry, xerc_in));
 386         adder_result <= sum_with_carry(63 downto 0);
 387         carry_32 <= sum_with_carry(32) xor a_inv(32) xor b_in(32);
 388         carry_64 <= sum_with_carry(64);
 389         overflow_32 <= calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31));
 390         overflow_64 <= calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63));
 391
 392         -- signals to multiply and divide units
 393         sign1 := '0';
 394         sign2 := '0';
 395         if e_in.is_signed = '1' then
 396             if e_in.is_32bit = '1' then
 397                 sign1 := a_in(31);
 398                 sign2 := b_in(31);
 399             else
 400                 sign1 := a_in(63);
 401                 sign2 := b_in(63);
 402             end if;
 403         end if;
 404         -- take absolute values
 405         if sign1 = '0' then
 406             abs1 := signed(a_in);
 407         else
 408             abs1 := - signed(a_in);
 409         end if;
 410         if sign2 = '0' then
 411             abs2 := signed(b_in);
 412         else
 413             abs2 := - signed(b_in);
 414         end if;
 415
 416         -- Interface to multiply and divide units
 417         x_to_divider.is_signed <= e_in.is_signed;
 418         x_to_divider.is_32bit <= e_in.is_32bit;
 419         x_to_divider.is_extended <= '0';
 420         x_to_divider.is_modulus <= '0';
 421         if e_in.insn_type = OP_MOD then
 422             x_to_divider.is_modulus <= '1';
 423         end if;
 424
 425         addend := (others => '0');
 426         if e_in.insn(26) = '0' then
 427             -- integer multiply-add, major op 4 (if it is a multiply)
 428             addend(63 downto 0) := c_in;
 429             if e_in.is_signed = '1' then
 430                 addend(127 downto 64) := (others => c_in(63));
 431             end if;
 432         end if;
 433         if (sign1 xor sign2) = '1' then
 434             addend := not addend;
 435         end if;
 436
 437         x_to_multiply.is_32bit <= e_in.is_32bit;
 438         x_to_multiply.not_result <= sign1 xor sign2;
 439         x_to_multiply.addend <= addend;
 440         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 441         if e_in.is_32bit = '0' then
 442             -- 64-bit forms
 443             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 444             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 445             if e_in.insn_type = OP_DIVE then
 446                 x_to_divider.is_extended <= '1';
 447             end if;
 448             x_to_divider.dividend <= std_ulogic_vector(abs1);
 449             x_to_divider.divisor <= std_ulogic_vector(abs2);
 450         else
 451             -- 32-bit forms
 452             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 453             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 454             x_to_divider.is_extended <= '0';
 455             if e_in.insn_type = OP_DIVE then   -- extended forms
 456                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 457             else
 458                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 459             end if;
 460             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 461         end if;
 462
 463         case current.sub_select(1 downto 0) is
 464             when "00" =>
 465                 muldiv_result <= multiply_to_x.result(63 downto 0);
 466             when "01" =>
 467                 muldiv_result <= multiply_to_x.result(127 downto 64);
 468             when "10" =>
 469                 muldiv_result <= multiply_to_x.result(63 downto 32) &
 470                                  multiply_to_x.result(63 downto 32);
 471             when others =>
 472                 muldiv_result <= divider_to_x.write_reg_data;
 473         end case;
 474
 475         -- Compute misc_result
 476         case current.sub_select is
 477             when "000" =>
 478                 misc_result <= (others => '0');
 479             when "001" =>
 480                 -- addg6s
 481                 addg6s := (others => '0');
 482                 for i in 0 to 14 loop
 483                     lo := i * 4;
 484                     hi := (i + 1) * 4;
 485                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 486                         addg6s(lo + 3 downto lo) := "0110";
 487                     end if;
 488                 end loop;
 489                 if sum_with_carry(64) = '0' then
 490                     addg6s(63 downto 60) := "0110";
 491                 end if;
 492                 misc_result <= addg6s;
 493             when "010" =>
 494                 -- isel
 495                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 496                 if cr_in(31-crbit) = '1' then
 497                     isel_result := a_in;
 498                 else
 499                     isel_result := b_in;
 500                 end if;
 501                 misc_result <= isel_result;
 502             when "011" =>
 503                 -- darn
 504                 darn := (others => '1');
 505                 if random_err = '0' then
 506                     case e_in.insn(17 downto 16) is
 507                         when "00" =>
 508                             darn := x"00000000" & random_cond(31 downto 0);
 509                         when "10" =>
 510                             darn := random_raw;
 511                         when others =>
 512                             darn := random_cond;
 513                     end case;
 514                 end if;
 515                 misc_result <= darn;
 516             when "100" =>
 517                 -- mfmsr
 518                 misc_result <= ctrl.msr;
 519             when "101" =>
 520                 if e_in.insn(20) = '0' then
 521                     -- mfcr
 522                     mfcr_result := x"00000000" & cr_in;
 523                 else
 524                     -- mfocrf
 525                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 526                     mfcr_result := (others => '0');
 527                     for i in 0 to 7 loop
 528                         lo := (7-i)*4;
 529                         hi := lo + 3;
 530                         if crnum = i then
 531                             mfcr_result(hi downto lo) := cr_in(hi downto lo);
 532                         end if;
 533                     end loop;
 534                 end if;
 535                 misc_result <= mfcr_result;
 536             when "110" =>
 537                 -- setb
 538                 bfa := insn_bfa(e_in.insn);
 539                 crbit := to_integer(unsigned(bfa)) * 4;
 540                 setb_result := (others => '0');
 541                 if cr_in(31 - crbit) = '1' then
 542                     setb_result := (others => '1');
 543                 elsif cr_in(30 - crbit) = '1' then
 544                     setb_result(0) := '1';
 545                 end if;
 546                 misc_result <= setb_result;
 547             when others =>
 548                 misc_result <= (others => '0');
 549         end case;
 550
 551         -- compute comparison results
 552         -- Note, we have done RB - RA, not RA - RB
 553         if e_in.insn_type = OP_CMP then
 554             l := insn_l(e_in.insn);
 555         else
 556             l := not e_in.is_32bit;
 557         end if;
 558         zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 559         zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 560         if zerolo = '1' and (l = '0' or zerohi = '1') then
 561             -- values are equal
 562             trapval <= "00100";
 563         else
 564             a_lt_lo := '0';
 565             a_lt_hi := '0';
 566             if unsigned(a_in(30 downto 0)) < unsigned(b_in(30 downto 0)) then
 567                 a_lt_lo := '1';
 568             end if;
 569             if unsigned(a_in(62 downto 31)) < unsigned(b_in(62 downto 31)) then
 570                 a_lt_hi := '1';
 571             end if;
 572             if l = '1' then
 573                 -- 64-bit comparison
 574                 msb_a := a_in(63);
 575                 msb_b := b_in(63);
 576                 a_lt := a_lt_hi or (zerohi and (a_in(31) xnor b_in(31)) and a_lt_lo);
 577             else
 578                 -- 32-bit comparison
 579                 msb_a := a_in(31);
 580                 msb_b := b_in(31);
 581                 a_lt := a_lt_lo;
 582             end if;
 583             if msb_a /= msb_b then
 584                 -- Comparison is clear from MSB difference.
 585                 -- for signed, 0 is greater; for unsigned, 1 is greater
 586                 trapval <= msb_a & msb_b & '0' & msb_b & msb_a;
 587             else
 588                 -- MSBs are equal, so signed and unsigned comparisons give the
 589                 -- same answer.
 590                 trapval <= a_lt & not a_lt & '0' & a_lt & not a_lt;
 591             end if;
 592         end if;
 593
 594         cmprb_result <= ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 595         cmpeqb_result <= ppc_cmpeqb(a_in, b_in);
 596     end process;
 597
 598     execute1_1: process(all)
 599         variable v : reg_type;
 600         variable newcrf : std_ulogic_vector(3 downto 0);
 601         variable crnum : crnum_t;
 602         variable scrnum : crnum_t;
 603         variable lo, hi : integer;
 604         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 605         variable bo, bi : std_ulogic_vector(4 downto 0);
 606         variable bf, bfa : std_ulogic_vector(2 downto 0);
 607         variable cr_op : std_ulogic_vector(9 downto 0);
 608         variable cr_operands : std_ulogic_vector(1 downto 0);
 609         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 610         variable btnum, banum, bbnum : integer range 0 to 31;
 611         variable crresult : std_ulogic;
 612         variable overflow : std_ulogic;
 613         variable lv : Execute1ToLoadstore1Type;
 614         variable irq_valid : std_ulogic;
 615         variable exception : std_ulogic;
 616         variable exception_nextpc : std_ulogic;
 617         variable illegal : std_ulogic;
 618         variable is_branch : std_ulogic;
 619         variable is_direct_branch : std_ulogic;
 620         variable taken_branch : std_ulogic;
 621         variable abs_branch : std_ulogic;
 622         variable spr_val : std_ulogic_vector(63 downto 0);
 623         variable do_trace : std_ulogic;
 624         variable hold_wr_data : std_ulogic;
 625         variable f : Execute1ToFetch1Type;
 626         variable fv : Execute1ToFPUType;
 627     begin
 628         newcrf := (others => '0');
 629         is_branch := '0';
 630         is_direct_branch := '0';
 631         taken_branch := '0';
 632         abs_branch := '0';
 633         hold_wr_data := '0';
 634
 635         v := r;
 636         v.e := Execute1ToWritebackInit;
 637         v.redirect := '0';
 638         v.abs_br := '0';
 639         v.do_intr := '0';
 640         v.vector := 0;
 641         v.br_offset := (others => '0');
 642         v.redir_mode := ctrl.msr(MSR_IR) & not ctrl.msr(MSR_PR) &
 643                         not ctrl.msr(MSR_LE) & not ctrl.msr(MSR_SF);
 644         v.taken_br := '0';
 645         v.br_last := '0';
 646         v.e.xerc := xerc_in;
 647
 648         lv := Execute1ToLoadstore1Init;
 649         fv := Execute1ToFPUInit;
 650
 651         x_to_multiply.valid <= '0';
 652         x_to_divider.valid <= '0';
 653         v.mul_in_progress := '0';
 654         v.div_in_progress := '0';
 655         v.cntz_in_progress := '0';
 656         v.mul_finish := '0';
 657
 658         spr_result <= (others => '0');
 659         spr_val := (others => '0');
 660
 661         ctrl_tmp <= ctrl;
 662         -- FIXME: run at 512MHz not core freq
 663         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 664         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 665
 666         irq_valid := '0';
 667         if ctrl.msr(MSR_EE) = '1' then
 668             if ctrl.dec(63) = '1' then
 669                 v.vector := 16#900#;
 670                 report "IRQ valid: DEC";
 671                 irq_valid := '1';
 672             elsif ext_irq_in = '1' then
 673                 v.vector := 16#500#;
 674                 report "IRQ valid: External";
 675                 irq_valid := '1';
 676             end if;
 677         end if;
 678
 679         v.terminate := '0';
 680         icache_inval <= '0';
 681         v.busy := '0';
 682
 683         -- Next insn adder used in a couple of places
 684         next_nia <= std_ulogic_vector(unsigned(e_in.nia) + 4);
 685
 686         -- rotator control signals
 687         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 688         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 689         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 690         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 691
 692         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 693         ctrl_tmp.irq_state <= WRITE_SRR0;
 694         exception := '0';
 695         illegal := '0';
 696         exception_nextpc := '0';
 697         v.e.exc_write_enable := '0';
 698         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 699         if valid_in = '1' then
 700             v.e.exc_write_data := e_in.nia;
 701             v.last_nia := e_in.nia;
 702         else
 703             v.e.exc_write_data := r.last_nia;
 704         end if;
 705
 706         v.e.mode_32bit := not ctrl.msr(MSR_SF);
 707         v.e.instr_tag := current.instr_tag;
 708
 709         do_trace := valid_in and ctrl.msr(MSR_SE);
 710         if valid_in = '1' then
 711             v.prev_op := e_in.insn_type;
 712         end if;
 713
 714         -- Determine if there is any exception to be taken
 715         -- before/instead of executing this instruction
 716         if valid_in = '1' and e_in.second = '0' then
 717             if HAS_FPU and r.fp_exception_next = '1' then
 718                 -- This is used for FP-type program interrupts that
 719                 -- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
 720                 exception := '1';
 721                 v.vector := 16#700#;
 722                 ctrl_tmp.srr1(63 - 43) <= '1';
 723                 ctrl_tmp.srr1(63 - 47) <= '1';
 724             elsif r.trace_next = '1' then
 725                 -- Generate a trace interrupt rather than executing the next instruction
 726                 -- or taking any asynchronous interrupt
 727                 exception := '1';
 728                 v.vector := 16#d00#;
 729                 ctrl_tmp.srr1(63 - 33) <= '1';
 730                 if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
 731                     r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
 732                     ctrl_tmp.srr1(63 - 35) <= '1';
 733                 elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
 734                     ctrl_tmp.srr1(63 - 36) <= '1';
 735                 end if;
 736
 737             elsif irq_valid = '1' then
 738                 -- Don't deliver the interrupt until we have a valid instruction
 739                 -- coming in, so we have a valid NIA to put in SRR0.
 740                 exception := '1';
 741
 742             elsif ctrl.msr(MSR_PR) = '1' and instr_is_privileged(e_in.insn_type, e_in.insn) then
 743                 -- generate a program interrupt
 744                 exception := '1';
 745                 v.vector := 16#700#;
 746                 -- set bit 45 to indicate privileged instruction type interrupt
 747                 ctrl_tmp.srr1(63 - 45) <= '1';
 748                 report "privileged instruction";
 749
 750             elsif not HAS_FPU and e_in.fac = FPU then
 751                 -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
 752                 illegal := '1';
 753
 754             elsif HAS_FPU and ctrl.msr(MSR_FP) = '0' and e_in.fac = FPU then
 755                 -- generate a floating-point unavailable interrupt
 756                 exception := '1';
 757                 v.vector := 16#800#;
 758                 report "FP unavailable interrupt";
 759             end if;
 760         end if;
 761
 762         if valid_in = '1' and exception = '0' and illegal = '0' and e_in.unit = ALU then
 763             v.cur_instr := e_in;
 764             v.next_lr := next_nia;
 765             v.e.valid := '1';
 766
 767             case_0: case e_in.insn_type is
 768
 769             when OP_ILLEGAL =>
 770                 -- we need two cycles to write srr0 and 1
 771                 -- will need more when we have to write HEIR
 772                 illegal := '1';
 773             when OP_SC =>
 774                 -- check bit 1 of the instruction is 1 so we know this is sc;
 775                 -- 0 would mean scv, so generate an illegal instruction interrupt
 776                 -- we need two cycles to write srr0 and 1
 777                 if e_in.insn(1) = '1' then
 778                     exception := '1';
 779                     exception_nextpc := '1';
 780                     v.vector := 16#C00#;
 781                     report "sc";
 782                 else
 783                     illegal := '1';
 784                 end if;
 785             when OP_ATTN =>
 786                 -- check bits 1-10 of the instruction to make sure it's attn
 787                 -- if not then it is illegal
 788                 if e_in.insn(10 downto 1) = "0100000000" then
 789                     v.terminate := '1';
 790                     report "ATTN";
 791                 else
 792                     illegal := '1';
 793                 end if;
 794             when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
 795                 -- Do nothing
 796             when OP_ADD =>
 797                 if e_in.output_carry = '1' then
 798                     if e_in.input_carry /= OV then
 799                         set_carry(v.e, carry_32, carry_64);
 800                     else
 801                         v.e.xerc.ov := carry_64;
 802                         v.e.xerc.ov32 := carry_32;
 803                         v.e.write_xerc_enable := '1';
 804                     end if;
 805                 end if;
 806                 if e_in.oe = '1' then
 807                     set_ov(v.e, overflow_64, overflow_32);
 808                 end if;
 809             when OP_CMP =>
 810                 -- CMP and CMPL instructions
 811                 if e_in.is_signed = '1' then
 812                     newcrf := trapval(4 downto 2) & xerc_in.so;
 813                 else
 814                     newcrf := trapval(1 downto 0) & trapval(2) & xerc_in.so;
 815                 end if;
 816                 bf := insn_bf(e_in.insn);
 817                 crnum := to_integer(unsigned(bf));
 818                 v.e.write_cr_mask := num_to_fxm(crnum);
 819                 for i in 0 to 7 loop
 820                     lo := i*4;
 821                     hi := lo + 3;
 822                     v.e.write_cr_data(hi downto lo) := newcrf;
 823                 end loop;
 824             when OP_TRAP =>
 825                 -- trap instructions (tw, twi, td, tdi)
 826                 v.vector := 16#700#;
 827                 -- set bit 46 to say trap occurred
 828                 ctrl_tmp.srr1(63 - 46) <= '1';
 829                 if or (trapval and insn_to(e_in.insn)) = '1' then
 830                     -- generate trap-type program interrupt
 831                     exception := '1';
 832                     report "trap";
 833                 end if;
 834             when OP_ADDG6S =>
 835             when OP_CMPRB =>
 836                 newcrf := cmprb_result;
 837                 bf := insn_bf(e_in.insn);
 838                 crnum := to_integer(unsigned(bf));
 839                 v.e.write_cr_mask := num_to_fxm(crnum);
 840                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 841                                      newcrf & newcrf & newcrf & newcrf;
 842             when OP_CMPEQB =>
 843                 newcrf := cmpeqb_result;
 844                 bf := insn_bf(e_in.insn);
 845                 crnum := to_integer(unsigned(bf));
 846                 v.e.write_cr_mask := num_to_fxm(crnum);
 847                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 848                                      newcrf & newcrf & newcrf & newcrf;
 849             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 850                     OP_BPERM | OP_BCD =>
 851
 852             when OP_B =>
 853                 is_branch := '1';
 854                 taken_branch := '1';
 855                 is_direct_branch := '1';
 856                 abs_branch := e_in.br_abs;
 857                 if ctrl.msr(MSR_BE) = '1' then
 858                     do_trace := '1';
 859                 end if;
 860             when OP_BC | OP_BCREG =>
 861                 -- read_data1 is CTR
 862                 -- for OP_BCREG, read_data2 is target register (CTR, LR or TAR)
 863                 -- If this instruction updates both CTR and LR, then it is
 864                 -- doubled; the first instruction decrements CTR and determines
 865                 -- whether the branch is taken, and the second does the
 866                 -- redirect and the LR update.
 867                 bo := insn_bo(e_in.insn);
 868                 bi := insn_bi(e_in.insn);
 869                 if e_in.second = '0' then
 870                     taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 871                 else
 872                     taken_branch := r.br_taken;
 873                 end if;
 874                 v.br_taken := taken_branch;
 875                 abs_branch := e_in.br_abs;
 876                 if e_in.repeat = '0' or e_in.second = '1' then
 877                     is_branch := '1';
 878                     if e_in.insn_type = OP_BC then
 879                         is_direct_branch := '1';
 880                     end if;
 881                     if ctrl.msr(MSR_BE) = '1' then
 882                         do_trace := '1';
 883                     end if;
 884                 end if;
 885
 886             when OP_RFID =>
 887                 v.redir_mode := (a_in(MSR_IR) or a_in(MSR_PR)) & not a_in(MSR_PR) &
 888                                 not a_in(MSR_LE) & not a_in(MSR_SF);
 889                 -- Can't use msr_copy here because the partial function MSR
 890                 -- bits should be left unchanged, not zeroed.
 891                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 892                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 893                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 894                 if a_in(MSR_PR) = '1' then
 895                     ctrl_tmp.msr(MSR_EE) <= '1';
 896                     ctrl_tmp.msr(MSR_IR) <= '1';
 897                     ctrl_tmp.msr(MSR_DR) <= '1';
 898                 end if;
 899                 -- mark this as a branch so CFAR gets updated
 900                 is_branch := '1';
 901                 taken_branch := '1';
 902                 abs_branch := '1';
 903                 if HAS_FPU then
 904                     v.fp_exception_next := fp_in.exception and
 905                                            (a_in(MSR_FE0) or a_in(MSR_FE1));
 906                 end if;
 907                 do_trace := '0';
 908
 909             when OP_CNTZ =>
 910                 v.e.valid := '0';
 911                 v.cntz_in_progress := '1';
 912                 v.busy := '1';
 913             when OP_ISEL =>
 914             when OP_CROP =>
 915                 cr_op := insn_cr(e_in.insn);
 916                 if cr_op(0) = '0' then -- MCRF
 917                     bf := insn_bf(e_in.insn);
 918                     bfa := insn_bfa(e_in.insn);
 919                     crnum := to_integer(unsigned(bf));
 920                     scrnum := to_integer(unsigned(bfa));
 921                     v.e.write_cr_mask := num_to_fxm(crnum);
 922                     for i in 0 to 7 loop
 923                         lo := (7-i)*4;
 924                         hi := lo + 3;
 925                         if i = scrnum then
 926                             newcrf := cr_in(hi downto lo);
 927                         end if;
 928                     end loop;
 929                     for i in 0 to 7 loop
 930                         lo := i*4;
 931                         hi := lo + 3;
 932                         v.e.write_cr_data(hi downto lo) := newcrf;
 933                     end loop;
 934                 else
 935                     bt := insn_bt(e_in.insn);
 936                     ba := insn_ba(e_in.insn);
 937                     bb := insn_bb(e_in.insn);
 938                     btnum := 31 - to_integer(unsigned(bt));
 939                     banum := 31 - to_integer(unsigned(ba));
 940                     bbnum := 31 - to_integer(unsigned(bb));
 941                     -- Bits 5-8 of cr_op give the truth table of the requested
 942                     -- logical operation
 943                     cr_operands := cr_in(banum) & cr_in(bbnum);
 944                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 945                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 946                     for i in 0 to 31 loop
 947                         if i = btnum then
 948                             v.e.write_cr_data(i) := crresult;
 949                         else
 950                             v.e.write_cr_data(i) := cr_in(i);
 951                         end if;
 952                     end loop;
 953                 end if;
 954             when OP_MCRXRX =>
 955                 newcrf := xerc_in.ov & xerc_in.ca & xerc_in.ov32 & xerc_in.ca32;
 956                 bf := insn_bf(e_in.insn);
 957                 crnum := to_integer(unsigned(bf));
 958                 v.e.write_cr_mask := num_to_fxm(crnum);
 959                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 960                                      newcrf & newcrf & newcrf & newcrf;
 961             when OP_DARN =>
 962             when OP_MFMSR =>
 963             when OP_MFSPR =>
 964                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 965                     "=" & to_hstring(a_in);
 966                 if is_fast_spr(e_in.read_reg1) = '1' then
 967                     spr_val := a_in;
 968                     if decode_spr_num(e_in.insn) = SPR_XER then
 969                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 970                         spr_val(63 downto 32) := (others => '0');
 971                         spr_val(63-32) := xerc_in.so;
 972                         spr_val(63-33) := xerc_in.ov;
 973                         spr_val(63-34) := xerc_in.ca;
 974                         spr_val(63-35 downto 63-43) := "000000000";
 975                         spr_val(63-44) := xerc_in.ov32;
 976                         spr_val(63-45) := xerc_in.ca32;
 977                     end if;
 978                 else
 979                     spr_val := c_in;
 980                     case decode_spr_num(e_in.insn) is
 981                     when SPR_TB =>
 982                         spr_val := ctrl.tb;
 983                     when SPR_TBU =>
 984                         spr_val(63 downto 32) := (others => '0');
 985                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 986                     when SPR_DEC =>
 987                         spr_val := ctrl.dec;
 988                     when SPR_CFAR =>
 989                         spr_val := ctrl.cfar;
 990                     when SPR_PVR =>
 991                         spr_val(63 downto 32) := (others => '0');
 992                         spr_val(31 downto 0) := PVR_MICROWATT;
 993                     when 724 =>     -- LOG_ADDR SPR
 994                         spr_val := log_wr_addr & r.log_addr_spr;
 995                     when 725 =>     -- LOG_DATA SPR
 996                         spr_val := log_rd_data;
 997                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 998                     when others =>
 999                         -- mfspr from unimplemented SPRs should be a nop in
1000                         -- supervisor mode and a program interrupt for user mode
1001                         if is_fast_spr(e_in.read_reg1) = '0' and ctrl.msr(MSR_PR) = '1' then
1002                             illegal := '1';
1003                         end if;
1004                     end case;
1005                 end if;
1006                 spr_result <= spr_val;
1007
1008             when OP_MFCR =>
1009             when OP_MTCRF =>
1010                 if e_in.insn(20) = '0' then
1011                     -- mtcrf
1012                     v.e.write_cr_mask := insn_fxm(e_in.insn);
1013                 else
1014                     -- mtocrf: We require one hot priority encoding here
1015                     crnum := fxm_to_num(insn_fxm(e_in.insn));
1016                     v.e.write_cr_mask := num_to_fxm(crnum);
1017                 end if;
1018                 v.e.write_cr_data := c_in(31 downto 0);
1019             when OP_MTMSRD =>
1020                 if e_in.insn(16) = '1' then
1021                     -- just update EE and RI
1022                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
1023                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
1024                 else
1025                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
1026                     -- and 63 (LE) (IBM bit numbering)
1027                     if e_in.is_32bit = '0' then
1028                         ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
1029                         ctrl_tmp.msr(59 downto 32) <= c_in(59 downto 32);
1030                     end if;
1031                     ctrl_tmp.msr(31 downto 13) <= c_in(31 downto 13);
1032                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
1033                     if c_in(MSR_PR) = '1' then
1034                         ctrl_tmp.msr(MSR_EE) <= '1';
1035                         ctrl_tmp.msr(MSR_IR) <= '1';
1036                         ctrl_tmp.msr(MSR_DR) <= '1';
1037                     end if;
1038                     if HAS_FPU then
1039                         v.fp_exception_next := fp_in.exception and
1040                                                (c_in(MSR_FE0) or c_in(MSR_FE1));
1041                     end if;
1042                 end if;
1043             when OP_MTSPR =>
1044                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
1045                     "=" & to_hstring(c_in);
1046                 if is_fast_spr(e_in.write_reg) then
1047                     if decode_spr_num(e_in.insn) = SPR_XER then
1048                         v.e.xerc.so := c_in(63-32);
1049                         v.e.xerc.ov := c_in(63-33);
1050                         v.e.xerc.ca := c_in(63-34);
1051                         v.e.xerc.ov32 := c_in(63-44);
1052                         v.e.xerc.ca32 := c_in(63-45);
1053                         v.e.write_xerc_enable := '1';
1054                     end if;
1055                 else
1056                     -- slow spr
1057                     case decode_spr_num(e_in.insn) is
1058                     when SPR_DEC =>
1059                         ctrl_tmp.dec <= c_in;
1060                     when 724 =>     -- LOG_ADDR SPR
1061                         v.log_addr_spr := c_in(31 downto 0);
1062                     when others =>
1063                         -- mtspr to unimplemented SPRs should be a nop in
1064                         -- supervisor mode and a program interrupt for user mode
1065                         if ctrl.msr(MSR_PR) = '1' then
1066                             illegal := '1';
1067                         end if;
1068                     end case;
1069                 end if;
1070             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
1071                 if e_in.output_carry = '1' then
1072                     set_carry(v.e, rotator_carry, rotator_carry);
1073                 end if;
1074             when OP_SETB =>
1075
1076             when OP_ISYNC =>
1077                 v.redirect := '1';
1078                 v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1079
1080             when OP_ICBI =>
1081                 icache_inval <= '1';
1082
1083             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1084                 v.e.valid := '0';
1085                 v.mul_in_progress := '1';
1086                 v.busy := '1';
1087                 x_to_multiply.valid <= '1';
1088
1089             when OP_DIV | OP_DIVE | OP_MOD =>
1090                 v.e.valid := '0';
1091                 v.div_in_progress := '1';
1092                 v.busy := '1';
1093                 x_to_divider.valid <= '1';
1094
1095             when others =>
1096                 v.terminate := '1';
1097                 report "illegal";
1098             end case;
1099
1100             -- Mispredicted branches cause a redirect
1101             if is_branch = '1' then
1102                 if taken_branch = '1' then
1103                     ctrl_tmp.cfar <= e_in.nia;
1104                 end if;
1105                 if taken_branch = '1' then
1106                     v.br_offset := b_in;
1107                     v.abs_br := abs_branch;
1108                 else
1109                     v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1110                 end if;
1111                 if taken_branch /= e_in.br_pred then
1112                     v.redirect := '1';
1113                 end if;
1114                 v.br_last := is_direct_branch;
1115                 v.taken_br := taken_branch;
1116             end if;
1117
1118         elsif valid_in = '1' and exception = '0' and illegal = '0' then
1119             -- instruction for other units, i.e. LDST
1120             if e_in.unit = LDST then
1121                 lv.valid := '1';
1122             elsif e_in.unit = NONE then
1123                 illegal := '1';
1124             elsif HAS_FPU and e_in.unit = FPU then
1125                 fv.valid := '1';
1126             end if;
1127             -- Handling an ITLB miss doesn't count as having executed an instruction
1128             if e_in.insn_type = OP_FETCH_FAILED then
1129                 do_trace := '0';
1130             end if;
1131         end if;
1132
1133         -- The following cases all occur when r.busy = 1 and therefore
1134         -- valid_in = 0.  Hence they don't happen in the same cycle as any of
1135         -- the cases above which depend on valid_in = 1.
1136
1137         if ctrl.irq_state = WRITE_SRR1 then
1138             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
1139             v.e.exc_write_data := ctrl.srr1;
1140             v.e.exc_write_enable := '1';
1141             ctrl_tmp.msr(MSR_SF) <= '1';
1142             ctrl_tmp.msr(MSR_EE) <= '0';
1143             ctrl_tmp.msr(MSR_PR) <= '0';
1144             ctrl_tmp.msr(MSR_SE) <= '0';
1145             ctrl_tmp.msr(MSR_BE) <= '0';
1146             ctrl_tmp.msr(MSR_FP) <= '0';
1147             ctrl_tmp.msr(MSR_FE0) <= '0';
1148             ctrl_tmp.msr(MSR_FE1) <= '0';
1149             ctrl_tmp.msr(MSR_IR) <= '0';
1150             ctrl_tmp.msr(MSR_DR) <= '0';
1151             ctrl_tmp.msr(MSR_RI) <= '0';
1152             ctrl_tmp.msr(MSR_LE) <= '1';
1153             v.trace_next := '0';
1154             v.fp_exception_next := '0';
1155             report "Writing SRR1: " & to_hstring(ctrl.srr1);
1156
1157         elsif r.cntz_in_progress = '1' then
1158             -- cnt[lt]z always takes two cycles
1159             v.e.valid := '1';
1160         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1161             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1162                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1163                 if r.mul_in_progress = '1' then
1164                     overflow := '0';
1165                 else
1166                     overflow := divider_to_x.overflow;
1167                 end if;
1168                 if r.mul_in_progress = '1' and current.oe = '1' then
1169                     -- have to wait until next cycle for overflow indication
1170                     v.mul_finish := '1';
1171                     v.busy := '1';
1172                 else
1173                     v.e.write_xerc_enable := current.oe;
1174                     -- We must test oe because the RC update code in writeback
1175                     -- will use the xerc value to set CR0:SO so we must not clobber
1176                     -- xerc if OE wasn't set.
1177                     if current.oe = '1' then
1178                         v.e.xerc.ov := overflow;
1179                         v.e.xerc.ov32 := overflow;
1180                         if overflow = '1' then
1181                             v.e.xerc.so := '1';
1182                         end if;
1183                     end if;
1184                     v.e.valid := '1';
1185                 end if;
1186             else
1187                 v.busy := '1';
1188                 v.mul_in_progress := r.mul_in_progress;
1189                 v.div_in_progress := r.div_in_progress;
1190             end if;
1191         elsif r.mul_finish = '1' then
1192             hold_wr_data := '1';
1193             v.e.write_xerc_enable := current.oe;
1194             v.e.xerc.ov := multiply_to_x.overflow;
1195             v.e.xerc.ov32 := multiply_to_x.overflow;
1196             if multiply_to_x.overflow = '1' then
1197                 v.e.xerc.so := '1';
1198             end if;
1199             v.e.valid := '1';
1200         end if;
1201
1202         -- Generate FP-type program interrupt.  fp_in.interrupt will only
1203         -- be set during the execution of a FP instruction.
1204         -- The case where MSR[FE0,FE1] goes from zero to non-zero is
1205         -- handled above by mtmsrd and rfid setting v.fp_exception_next.
1206         if HAS_FPU and fp_in.interrupt = '1' then
1207             v.vector := 16#700#;
1208             ctrl_tmp.srr1(63 - 43) <= '1';
1209             exception := '1';
1210         end if;
1211
1212         if illegal = '1' or (HAS_FPU and fp_in.illegal = '1') then
1213             exception := '1';
1214             v.vector := 16#700#;
1215             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1216             -- set bit 44 to indicate we have an illegal
1217             ctrl_tmp.srr1(63 - 44) <= '1';
1218             report "illegal";
1219         end if;
1220         if exception = '1' then
1221             v.e.exc_write_enable := '1';
1222             if exception_nextpc = '1' then
1223                 v.e.exc_write_data := next_nia;
1224             end if;
1225         end if;
1226
1227         -- generate DSI or DSegI for load/store exceptions
1228         -- or ISI or ISegI for instruction fetch exceptions
1229         if l_in.exception = '1' then
1230             if l_in.alignment = '1' then
1231                 v.vector := 16#600#;
1232             elsif l_in.instr_fault = '0' then
1233                 if l_in.segment_fault = '0' then
1234                     v.vector := 16#300#;
1235                 else
1236                     v.vector := 16#380#;
1237                 end if;
1238             else
1239                 if l_in.segment_fault = '0' then
1240                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1241                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1242                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1243                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1244                     v.vector := 16#400#;
1245                 else
1246                     v.vector := 16#480#;
1247                 end if;
1248             end if;
1249             v.e.exc_write_enable := '1';
1250             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1251             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1252         end if;
1253
1254         if exception = '1' or l_in.exception = '1' then
1255             ctrl_tmp.irq_state <= WRITE_SRR1;
1256             v.redirect := '1';
1257             v.do_intr := '1';
1258         end if;
1259
1260         if do_trace = '1' then
1261             v.trace_next := '1';
1262         end if;
1263
1264         if hold_wr_data = '0' then
1265             v.e.write_data := alu_result;
1266         else
1267             v.e.write_data := r.e.write_data;
1268         end if;
1269         v.e.write_reg := current.write_reg;
1270         v.e.write_enable := current.write_reg_enable and v.e.valid and not exception;
1271         v.e.write_cr_enable := current.output_cr and v.e.valid and not exception;
1272         v.e.rc := current.rc and v.e.valid and not exception;
1273
1274         bypass_data.tag.valid <= current.instr_tag.valid and current.write_reg_enable and v.e.valid;
1275         bypass_data.tag.tag <= current.instr_tag.tag;
1276         bypass_data.data <= v.e.write_data;
1277
1278         bypass_cr_data.tag.valid <= current.instr_tag.valid and current.output_cr and v.e.valid;
1279         bypass_cr_data.tag.tag <= current.instr_tag.tag;
1280         for i in 0 to 7 loop
1281             if v.e.write_cr_mask(i) = '1' then
1282                 bypass_cr_data.data(i*4 + 3 downto i*4) <= v.e.write_cr_data(i*4 + 3 downto i*4);
1283             else
1284                 bypass_cr_data.data(i*4 + 3 downto i*4) <= cr_in(i*4 + 3 downto i*4);
1285             end if;
1286         end loop;
1287
1288         -- Defer completion for one cycle when redirecting.
1289         -- This also ensures r.busy = 1 when ctrl.irq_state = WRITE_SRR1
1290         if v.redirect = '1' then
1291             v.busy := '1';
1292             v.e.valid := '0';
1293         end if;
1294         if r.redirect = '1' then
1295             v.e.valid := '1';
1296         end if;
1297
1298         -- Outputs to fetch1
1299         f.redirect := r.redirect;
1300         f.br_nia := r.last_nia;
1301         f.br_last := r.br_last and not r.do_intr;
1302         f.br_taken := r.taken_br;
1303         if r.do_intr = '1' then
1304             f.redirect_nia := std_ulogic_vector(to_unsigned(r.vector, 64));
1305             f.virt_mode := '0';
1306             f.priv_mode := '1';
1307             -- XXX need an interrupt LE bit here, e.g. from LPCR
1308             f.big_endian := '0';
1309             f.mode_32bit := '0';
1310         else
1311             if r.abs_br = '1' then
1312                 f.redirect_nia := r.br_offset;
1313             else
1314                 f.redirect_nia := std_ulogic_vector(unsigned(r.last_nia) + unsigned(r.br_offset));
1315             end if;
1316             -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
1317             f.virt_mode := r.redir_mode(3);
1318             f.priv_mode := r.redir_mode(2);
1319             f.big_endian := r.redir_mode(1);
1320             f.mode_32bit := r.redir_mode(0);
1321         end if;
1322
1323         -- Outputs to loadstore1 (async)
1324         lv.op := e_in.insn_type;
1325         lv.nia := e_in.nia;
1326         lv.instr_tag := e_in.instr_tag;
1327         lv.addr1 := a_in;
1328         lv.addr2 := b_in;
1329         lv.data := c_in;
1330         lv.write_reg := e_in.write_reg;
1331         lv.length := e_in.data_len;
1332         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1333         lv.sign_extend := e_in.sign_extend;
1334         lv.update := e_in.update;
1335         lv.xerc := xerc_in;
1336         lv.reserve := e_in.reserve;
1337         lv.rc := e_in.rc;
1338         lv.insn := e_in.insn;
1339         -- decode l*cix and st*cix instructions here
1340         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1341             e_in.insn(5 downto 1) = "10101" then
1342             lv.ci := '1';
1343         end if;
1344         lv.virt_mode := ctrl.msr(MSR_DR);
1345         lv.priv_mode := not ctrl.msr(MSR_PR);
1346         lv.mode_32bit := not ctrl.msr(MSR_SF);
1347         lv.is_32bit := e_in.is_32bit;
1348         lv.repeat := e_in.repeat;
1349         lv.second := e_in.second;
1350
1351         -- Outputs to FPU
1352         fv.op := e_in.insn_type;
1353         fv.nia := e_in.nia;
1354         fv.insn := e_in.insn;
1355         fv.itag := e_in.instr_tag;
1356         fv.single := e_in.is_32bit;
1357         fv.fe_mode := ctrl.msr(MSR_FE0) & ctrl.msr(MSR_FE1);
1358         fv.fra := a_in;
1359         fv.frb := b_in;
1360         fv.frc := c_in;
1361         fv.frt := e_in.write_reg;
1362         fv.rc := e_in.rc;
1363         fv.out_cr := e_in.output_cr;
1364
1365         -- Update registers
1366         rin <= v;
1367
1368         -- update outputs
1369         f_out <= f;
1370         l_out <= lv;
1371         e_out <= r.e;
1372         fp_out <= fv;
1373         flush_out <= f_out.redirect;
1374
1375         exception_log <= exception;
1376         irq_valid_log <= irq_valid;
1377     end process;
1378
1379     e1_log: if LOG_LENGTH > 0 generate
1380         signal log_data : std_ulogic_vector(14 downto 0);
1381     begin
1382         ex1_log : process(clk)
1383         begin
1384             if rising_edge(clk) then
1385                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1386                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1387                             exception_log &
1388                             irq_valid_log &
1389                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1390                             "000" &
1391                             r.e.write_enable &
1392                             r.e.valid &
1393                             f_out.redirect &
1394                             r.busy &
1395                             flush_out;
1396             end if;
1397         end process;
1398         log_out <= log_data;
1399     end generate;
1400 end architecture behaviour;