execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true
  16         );
  17     port (
  18         clk   : in std_ulogic;
  19         rst   : in std_ulogic;
  20
  21         -- asynchronous
  22         flush_out : out std_ulogic;
  23         stall_out : out std_ulogic;
  24
  25         e_in  : in Decode2ToExecute1Type;
  26         l_in  : in Loadstore1ToExecute1Type;
  27
  28         i_in : in XicsToExecute1Type;
  29
  30         -- asynchronous
  31         l_out : out Execute1ToLoadstore1Type;
  32         f_out : out Execute1ToFetch1Type;
  33
  34         e_out : out Execute1ToWritebackType;
  35
  36         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  37
  38         icache_inval : out std_ulogic;
  39         terminate_out : out std_ulogic
  40         );
  41 end entity execute1;
  42
  43 architecture behaviour of execute1 is
  44     type reg_type is record
  45         e : Execute1ToWritebackType;
  46         lr_update : std_ulogic;
  47         next_lr : std_ulogic_vector(63 downto 0);
  48         mul_in_progress : std_ulogic;
  49         div_in_progress : std_ulogic;
  50         cntz_in_progress : std_ulogic;
  51         slow_op_dest : gpr_index_t;
  52         slow_op_rc : std_ulogic;
  53         slow_op_oe : std_ulogic;
  54         slow_op_xerc : xer_common_t;
  55         ldst_nia : std_ulogic_vector(63 downto 0);
  56     end record;
  57     constant reg_type_init : reg_type :=
  58         (e => Execute1ToWritebackInit, lr_update => '0',
  59          mul_in_progress => '0', div_in_progress => '0', cntz_in_progress => '0',
  60          slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  61          others => (others => '0'));
  62
  63     signal r, rin : reg_type;
  64
  65     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  66
  67     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  68     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  69     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  70     signal rot_sign_ext: std_ulogic;
  71     signal rotator_result: std_ulogic_vector(63 downto 0);
  72     signal rotator_carry: std_ulogic;
  73     signal logical_result: std_ulogic_vector(63 downto 0);
  74     signal countzero_result: std_ulogic_vector(63 downto 0);
  75     signal popcnt_result: std_ulogic_vector(63 downto 0);
  76     signal parity_result: std_ulogic_vector(63 downto 0);
  77
  78     -- multiply signals
  79     signal x_to_multiply: Execute1ToMultiplyType;
  80     signal multiply_to_x: MultiplyToExecute1Type;
  81
  82     -- divider signals
  83     signal x_to_divider: Execute1ToDividerType;
  84     signal divider_to_x: DividerToExecute1Type;
  85
  86     type privilege_level is (USER, SUPER);
  87     type op_privilege_array is array(insn_type_t) of privilege_level;
  88     constant op_privilege: op_privilege_array := (
  89         OP_ATTN => SUPER,
  90         OP_MFMSR => SUPER,
  91         OP_MTMSRD => SUPER,
  92         OP_RFID => SUPER,
  93         OP_TLBIE => SUPER,
  94         others => USER
  95         );
  96
  97     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
  98         return boolean is
  99     begin
 100         if op_privilege(op) = SUPER then
 101             return true;
 102         elsif op = OP_MFSPR or op = OP_MTSPR then
 103             return insn(20) = '1';
 104         else
 105             return false;
 106         end if;
 107     end;
 108
 109     procedure set_carry(e: inout Execute1ToWritebackType;
 110                         carry32 : in std_ulogic;
 111                         carry : in std_ulogic) is
 112     begin
 113         e.xerc.ca32 := carry32;
 114         e.xerc.ca := carry;
 115         e.write_xerc_enable := '1';
 116     end;
 117
 118     procedure set_ov(e: inout Execute1ToWritebackType;
 119                      ov   : in std_ulogic;
 120                      ov32 : in std_ulogic) is
 121     begin
 122         e.xerc.ov32 := ov32;
 123         e.xerc.ov := ov;
 124         if ov = '1' then
 125             e.xerc.so := '1';
 126         end if;
 127         e.write_xerc_enable := '1';
 128     end;
 129
 130     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 131                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 132     begin
 133         return (ca xor msb_r) and not (msb_a xor msb_b);
 134     end;
 135
 136     function decode_input_carry(ic : carry_in_t;
 137                                 xerc : xer_common_t) return std_ulogic is
 138     begin
 139         case ic is
 140         when ZERO =>
 141             return '0';
 142         when CA =>
 143             return xerc.ca;
 144         when ONE =>
 145             return '1';
 146         end case;
 147     end;
 148
 149     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 150         return std_ulogic_vector is
 151         variable msr_out: std_ulogic_vector(63 downto 0);
 152     begin
 153         -- ISA says this:
 154         --  Defined MSR bits are classified as either full func-
 155         --  tion or partial function. Full function MSR bits are
 156         --  saved in SRR1 or HSRR1 when an interrupt other
 157         --  than a System Call Vectored interrupt occurs and
 158         --  restored by rfscv, rfid, or hrfid, while partial func-
 159         --  tion MSR bits are not saved or restored.
 160         --  Full function MSR bits lie in the range 0:32, 37:41, and
 161         --  48:63, and partial function MSR bits lie in the range
 162         --  33:36 and 42:47. (Note this is IBM bit numbering).
 163         msr_out := (others => '0');
 164         msr_out(63 downto 31) := msr(63 downto 31);
 165         msr_out(26 downto 22) := msr(26 downto 22);
 166         msr_out(15 downto 0)  := msr(15 downto 0);
 167         return msr_out;
 168     end;
 169
 170 begin
 171
 172     rotator_0: entity work.rotator
 173         port map (
 174             rs => c_in,
 175             ra => a_in,
 176             shift => b_in(6 downto 0),
 177             insn => e_in.insn,
 178             is_32bit => e_in.is_32bit,
 179             right_shift => right_shift,
 180             arith => e_in.is_signed,
 181             clear_left => rot_clear_left,
 182             clear_right => rot_clear_right,
 183             sign_ext_rs => rot_sign_ext,
 184             result => rotator_result,
 185             carry_out => rotator_carry
 186             );
 187
 188     logical_0: entity work.logical
 189         port map (
 190             rs => c_in,
 191             rb => b_in,
 192             op => e_in.insn_type,
 193             invert_in => e_in.invert_a,
 194             invert_out => e_in.invert_out,
 195             result => logical_result,
 196             datalen => e_in.data_len,
 197             popcnt => popcnt_result,
 198             parity => parity_result
 199             );
 200
 201     countzero_0: entity work.zero_counter
 202         port map (
 203             clk => clk,
 204             rs => c_in,
 205             count_right => e_in.insn(10),
 206             is_32bit => e_in.is_32bit,
 207             result => countzero_result
 208             );
 209
 210     multiply_0: entity work.multiply
 211         port map (
 212             clk => clk,
 213             m_in => x_to_multiply,
 214             m_out => multiply_to_x
 215             );
 216
 217     divider_0: entity work.divider
 218         port map (
 219             clk => clk,
 220             rst => rst,
 221             d_in => x_to_divider,
 222             d_out => divider_to_x
 223             );
 224
 225     dbg_msr_out <= ctrl.msr;
 226
 227     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 228     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 229     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 230
 231     execute1_0: process(clk)
 232     begin
 233         if rising_edge(clk) then
 234             if rst = '1' then
 235                 r <= reg_type_init;
 236                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 237                 ctrl.irq_state <= WRITE_SRR0;
 238             else
 239                 r <= rin;
 240                 ctrl <= ctrl_tmp;
 241                 assert not (r.lr_update = '1' and e_in.valid = '1')
 242                     report "LR update collision with valid in EX1"
 243                     severity failure;
 244                 if r.lr_update = '1' then
 245                     report "LR update to " & to_hstring(r.next_lr);
 246                 end if;
 247             end if;
 248         end if;
 249     end process;
 250
 251     execute1_1: process(all)
 252         variable v : reg_type;
 253         variable a_inv : std_ulogic_vector(63 downto 0);
 254         variable result : std_ulogic_vector(63 downto 0);
 255         variable newcrf : std_ulogic_vector(3 downto 0);
 256         variable result_with_carry : std_ulogic_vector(64 downto 0);
 257         variable result_en : std_ulogic;
 258         variable crnum : crnum_t;
 259         variable crbit : integer range 0 to 31;
 260         variable scrnum : crnum_t;
 261         variable lo, hi : integer;
 262         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 263         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 264         variable bo, bi : std_ulogic_vector(4 downto 0);
 265         variable bf, bfa : std_ulogic_vector(2 downto 0);
 266         variable cr_op : std_ulogic_vector(9 downto 0);
 267         variable cr_operands : std_ulogic_vector(1 downto 0);
 268         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 269         variable btnum, banum, bbnum : integer range 0 to 31;
 270         variable crresult : std_ulogic;
 271         variable l : std_ulogic;
 272         variable next_nia : std_ulogic_vector(63 downto 0);
 273         variable carry_32, carry_64 : std_ulogic;
 274         variable sign1, sign2 : std_ulogic;
 275         variable abs1, abs2 : signed(63 downto 0);
 276         variable overflow : std_ulogic;
 277         variable negative : std_ulogic;
 278         variable zerohi, zerolo : std_ulogic;
 279         variable msb_a, msb_b : std_ulogic;
 280         variable a_lt : std_ulogic;
 281         variable lv : Execute1ToLoadstore1Type;
 282         variable irq_valid : std_ulogic;
 283         variable exception : std_ulogic;
 284         variable exception_nextpc : std_ulogic;
 285         variable trapval : std_ulogic_vector(4 downto 0);
 286         variable illegal : std_ulogic;
 287     begin
 288         result := (others => '0');
 289         result_with_carry := (others => '0');
 290         result_en := '0';
 291         newcrf := (others => '0');
 292
 293         v := r;
 294         v.e := Execute1ToWritebackInit;
 295         lv := Execute1ToLoadstore1Init;
 296
 297         -- XER forwarding. To avoid having to track XER hazards, we
 298         -- use the previously latched value.
 299         --
 300         -- If the XER was modified by a multiply or a divide, those are
 301         -- single issue, we'll get the up to date value from decode2 from
 302         -- the register file.
 303         --
 304         -- If it was modified by an instruction older than the previous
 305         -- one in EX1, it will have also hit writeback and will be up
 306         -- to date in decode2.
 307         --
 308         -- That leaves us with the case where it was updated by the previous
 309         -- instruction in EX1. In that case, we can forward it back here.
 310         --
 311         -- This will break if we allow pipelining of multiply and divide,
 312         -- but ideally, those should go via EX1 anyway and run as a state
 313         -- machine from here.
 314         --
 315         -- One additional hazard to beware of is an XER:SO modifying instruction
 316         -- in EX1 followed immediately by a store conditional. Due to our
 317         -- writeback latency, the store will go down the LSU with the previous
 318         -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
 319         --
 320         -- We will need to handle that if we ever make stcx. not single issue
 321         --
 322         -- We always pass a valid XER value downto writeback even when
 323         -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
 324         -- to work for RC instructions.
 325         --
 326         if r.e.write_xerc_enable = '1' then
 327             v.e.xerc := r.e.xerc;
 328         else
 329             v.e.xerc := e_in.xerc;
 330         end if;
 331
 332         v.lr_update := '0';
 333         v.mul_in_progress := '0';
 334         v.div_in_progress := '0';
 335         v.cntz_in_progress := '0';
 336
 337         -- signals to multiply unit
 338         x_to_multiply <= Execute1ToMultiplyInit;
 339         x_to_multiply.insn_type <= e_in.insn_type;
 340         x_to_multiply.is_32bit <= e_in.is_32bit;
 341
 342         if e_in.is_32bit = '1' then
 343             if e_in.is_signed = '1' then
 344                 x_to_multiply.data1 <= (others => a_in(31));
 345                 x_to_multiply.data1(31 downto 0) <= a_in(31 downto 0);
 346                 x_to_multiply.data2 <= (others => b_in(31));
 347                 x_to_multiply.data2(31 downto 0) <= b_in(31 downto 0);
 348             else
 349                 x_to_multiply.data1 <= '0' & x"00000000" & a_in(31 downto 0);
 350                 x_to_multiply.data2 <= '0' & x"00000000" & b_in(31 downto 0);
 351             end if;
 352         else
 353             if e_in.is_signed = '1' then
 354                 x_to_multiply.data1 <= a_in(63) & a_in;
 355                 x_to_multiply.data2 <= b_in(63) & b_in;
 356             else
 357                 x_to_multiply.data1 <= '0' & a_in;
 358                 x_to_multiply.data2 <= '0' & b_in;
 359             end if;
 360         end if;
 361
 362         -- signals to divide unit
 363         sign1 := '0';
 364         sign2 := '0';
 365         if e_in.is_signed = '1' then
 366             if e_in.is_32bit = '1' then
 367                 sign1 := a_in(31);
 368                 sign2 := b_in(31);
 369             else
 370                 sign1 := a_in(63);
 371                 sign2 := b_in(63);
 372             end if;
 373         end if;
 374         -- take absolute values
 375         if sign1 = '0' then
 376             abs1 := signed(a_in);
 377         else
 378             abs1 := - signed(a_in);
 379         end if;
 380         if sign2 = '0' then
 381             abs2 := signed(b_in);
 382         else
 383             abs2 := - signed(b_in);
 384         end if;
 385
 386         x_to_divider <= Execute1ToDividerInit;
 387         x_to_divider.is_signed <= e_in.is_signed;
 388         x_to_divider.is_32bit <= e_in.is_32bit;
 389         if e_in.insn_type = OP_MOD then
 390             x_to_divider.is_modulus <= '1';
 391         end if;
 392         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 393         if e_in.is_32bit = '0' then
 394             -- 64-bit forms
 395             if e_in.insn_type = OP_DIVE then
 396                 x_to_divider.is_extended <= '1';
 397             end if;
 398             x_to_divider.dividend <= std_ulogic_vector(abs1);
 399             x_to_divider.divisor <= std_ulogic_vector(abs2);
 400         else
 401             -- 32-bit forms
 402             x_to_divider.is_extended <= '0';
 403             if e_in.insn_type = OP_DIVE then   -- extended forms
 404                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 405             else
 406                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 407             end if;
 408             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 409         end if;
 410
 411         ctrl_tmp <= ctrl;
 412         -- FIXME: run at 512MHz not core freq
 413         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 414         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 415
 416         irq_valid := '0';
 417         if ctrl.msr(MSR_EE) = '1' then
 418             if ctrl.dec(63) = '1' then
 419                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#900#, 64));
 420                 report "IRQ valid: DEC";
 421                 irq_valid := '1';
 422             elsif i_in.irq = '1' then
 423                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#500#, 64));
 424                 report "IRQ valid: External";
 425                 irq_valid := '1';
 426             end if;
 427         end if;
 428
 429         terminate_out <= '0';
 430         icache_inval <= '0';
 431         stall_out <= '0';
 432         f_out <= Execute1ToFetch1TypeInit;
 433
 434         -- Next insn adder used in a couple of places
 435         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 436
 437         -- rotator control signals
 438         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 439         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 440         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 441         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 442
 443         ctrl_tmp.irq_state <= WRITE_SRR0;
 444         exception := '0';
 445         illegal := '0';
 446         exception_nextpc := '0';
 447         v.e.exc_write_enable := '0';
 448         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 449         v.e.exc_write_data := e_in.nia;
 450
 451         if ctrl.irq_state = WRITE_SRR1 then
 452             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 453             v.e.exc_write_data := ctrl.srr1;
 454             v.e.exc_write_enable := '1';
 455             ctrl_tmp.msr(MSR_SF) <= '1';
 456             ctrl_tmp.msr(MSR_EE) <= '0';
 457             ctrl_tmp.msr(MSR_PR) <= '0';
 458             ctrl_tmp.msr(MSR_IR) <= '0';
 459             ctrl_tmp.msr(MSR_DR) <= '0';
 460             ctrl_tmp.msr(MSR_RI) <= '0';
 461             ctrl_tmp.msr(MSR_LE) <= '1';
 462             f_out.redirect <= '1';
 463             f_out.redirect_nia <= ctrl.irq_nia;
 464             v.e.valid := e_in.valid;
 465             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 466
 467         elsif irq_valid = '1' and e_in.valid = '1' then
 468             -- we need two cycles to write srr0 and 1
 469             -- will need more when we have to write HEIR
 470             -- Don't deliver the interrupt until we have a valid instruction
 471             -- coming in, so we have a valid NIA to put in SRR0.
 472             exception := '1';
 473             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 474
 475         elsif e_in.valid = '1' and ctrl.msr(MSR_PR) = '1' and
 476             instr_is_privileged(e_in.insn_type, e_in.insn) then
 477             -- generate a program interrupt
 478             exception := '1';
 479             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 480             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 481             -- set bit 45 to indicate privileged instruction type interrupt
 482             ctrl_tmp.srr1(63 - 45) <= '1';
 483             report "privileged instruction";
 484
 485         elsif e_in.valid = '1' and e_in.unit = ALU then
 486
 487             report "execute nia " & to_hstring(e_in.nia);
 488
 489             v.e.valid := '1';
 490             v.e.write_reg := e_in.write_reg;
 491             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 492             v.slow_op_rc := e_in.rc;
 493             v.slow_op_oe := e_in.oe;
 494             v.slow_op_xerc := v.e.xerc;
 495
 496             case_0: case e_in.insn_type is
 497
 498             when OP_ILLEGAL =>
 499                 -- we need two cycles to write srr0 and 1
 500                 -- will need more when we have to write HEIR
 501                 illegal := '1';
 502             when OP_SC =>
 503                 -- check bit 1 of the instruction is 1 so we know this is sc;
 504                 -- 0 would mean scv, so generate an illegal instruction interrupt
 505                 -- we need two cycles to write srr0 and 1
 506                 if e_in.insn(1) = '1' then
 507                     exception := '1';
 508                     exception_nextpc := '1';
 509                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
 510                     ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 511                     report "sc";
 512                 else
 513                     illegal := '1';
 514                 end if;
 515             when OP_ATTN =>
 516                 -- check bits 1-10 of the instruction to make sure it's attn
 517                 -- if not then it is illegal
 518                 if e_in.insn(10 downto 1) = "0100000000" then
 519                     terminate_out <= '1';
 520                     report "ATTN";
 521                 else
 522                     illegal := '1';
 523                 end if;
 524             when OP_NOP =>
 525                 -- Do nothing
 526             when OP_ADD | OP_CMP | OP_TRAP =>
 527                 if e_in.invert_a = '0' then
 528                     a_inv := a_in;
 529                 else
 530                     a_inv := not a_in;
 531                 end if;
 532                 result_with_carry := ppc_adde(a_inv, b_in,
 533                                               decode_input_carry(e_in.input_carry, v.e.xerc));
 534                 result := result_with_carry(63 downto 0);
 535                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 536                 carry_64 := result_with_carry(64);
 537                 if e_in.insn_type = OP_ADD then
 538                     if e_in.output_carry = '1' then
 539                         set_carry(v.e, carry_32, carry_64);
 540                     end if;
 541                     if e_in.oe = '1' then
 542                         set_ov(v.e,
 543                                calc_ov(a_inv(63), b_in(63), carry_64, result_with_carry(63)),
 544                                calc_ov(a_inv(31), b_in(31), carry_32, result_with_carry(31)));
 545                     end if;
 546                     result_en := '1';
 547                 else
 548                     -- trap, CMP and CMPL instructions
 549                     -- Note, we have done RB - RA, not RA - RB
 550                     if e_in.insn_type = OP_CMP then
 551                         l := insn_l(e_in.insn);
 552                     else
 553                         l := not e_in.is_32bit;
 554                     end if;
 555                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 556                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 557                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 558                         -- values are equal
 559                         trapval := "00100";
 560                     else
 561                         if l = '1' then
 562                             -- 64-bit comparison
 563                             msb_a := a_in(63);
 564                             msb_b := b_in(63);
 565                         else
 566                             -- 32-bit comparison
 567                             msb_a := a_in(31);
 568                             msb_b := b_in(31);
 569                         end if;
 570                         if msb_a /= msb_b then
 571                             -- Subtraction might overflow, but
 572                             -- comparison is clear from MSB difference.
 573                             -- for signed, 0 is greater; for unsigned, 1 is greater
 574                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 575                         else
 576                             -- Subtraction cannot overflow since MSBs are equal.
 577                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 578                             a_lt := (not l and carry_32) or (l and carry_64);
 579                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 580                         end if;
 581                     end if;
 582                     if e_in.insn_type = OP_CMP then
 583                         if e_in.is_signed = '1' then
 584                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 585                         else
 586                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 587                         end if;
 588                         bf := insn_bf(e_in.insn);
 589                         crnum := to_integer(unsigned(bf));
 590                         v.e.write_cr_enable := '1';
 591                         v.e.write_cr_mask := num_to_fxm(crnum);
 592                         for i in 0 to 7 loop
 593                             lo := i*4;
 594                             hi := lo + 3;
 595                             v.e.write_cr_data(hi downto lo) := newcrf;
 596                         end loop;
 597                     else
 598                         -- trap instructions (tw, twi, td, tdi)
 599                         if or (trapval and insn_to(e_in.insn)) = '1' then
 600                             -- generate trap-type program interrupt
 601                             exception := '1';
 602                             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 603                             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 604                             -- set bit 46 to say trap occurred
 605                             ctrl_tmp.srr1(63 - 46) <= '1';
 606                             report "trap";
 607                         end if;
 608                     end if;
 609                 end if;
 610             when OP_AND | OP_OR | OP_XOR =>
 611                 result := logical_result;
 612                 result_en := '1';
 613             when OP_B =>
 614                 f_out.redirect <= '1';
 615                 if (insn_aa(e_in.insn)) then
 616                     f_out.redirect_nia <= b_in;
 617                 else
 618                     f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
 619                 end if;
 620             when OP_BC =>
 621                 -- read_data1 is CTR
 622                 bo := insn_bo(e_in.insn);
 623                 bi := insn_bi(e_in.insn);
 624                 if bo(4-2) = '0' then
 625                     result := std_ulogic_vector(unsigned(a_in) - 1);
 626                     result_en := '1';
 627                     v.e.write_reg := fast_spr_num(SPR_CTR);
 628                 end if;
 629                 if ppc_bc_taken(bo, bi, e_in.cr, a_in) = 1 then
 630                     f_out.redirect <= '1';
 631                     if (insn_aa(e_in.insn)) then
 632                         f_out.redirect_nia <= b_in;
 633                     else
 634                         f_out.redirect_nia <= std_ulogic_vector(signed(e_in.nia) + signed(b_in));
 635                     end if;
 636                 end if;
 637             when OP_BCREG =>
 638                 -- read_data1 is CTR
 639                 -- read_data2 is target register (CTR, LR or TAR)
 640                 bo := insn_bo(e_in.insn);
 641                 bi := insn_bi(e_in.insn);
 642                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 643                     result := std_ulogic_vector(unsigned(a_in) - 1);
 644                     result_en := '1';
 645                     v.e.write_reg := fast_spr_num(SPR_CTR);
 646                 end if;
 647                 if ppc_bc_taken(bo, bi, e_in.cr, a_in) = 1 then
 648                     f_out.redirect <= '1';
 649                     f_out.redirect_nia <= b_in(63 downto 2) & "00";
 650                 end if;
 651
 652             when OP_RFID =>
 653                 f_out.redirect <= '1';
 654                 f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
 655                 -- Can't use msr_copy here because the partial function MSR
 656                 -- bits should be left unchanged, not zeroed.
 657                 ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31);
 658                 ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22);
 659                 ctrl_tmp.msr(15 downto 0)  <= b_in(15 downto 0);
 660                 if b_in(MSR_PR) = '1' then
 661                     ctrl_tmp.msr(MSR_EE) <= '1';
 662                     ctrl_tmp.msr(MSR_IR) <= '1';
 663                     ctrl_tmp.msr(MSR_DR) <= '1';
 664                 end if;
 665
 666             when OP_CMPB =>
 667                 result := ppc_cmpb(c_in, b_in);
 668                 result_en := '1';
 669             when OP_CNTZ =>
 670                 v.e.valid := '0';
 671                 v.cntz_in_progress := '1';
 672                 stall_out <= '1';
 673             when OP_EXTS =>
 674                 -- note data_len is a 1-hot encoding
 675                 negative := (e_in.data_len(0) and c_in(7)) or
 676                             (e_in.data_len(1) and c_in(15)) or
 677                             (e_in.data_len(2) and c_in(31));
 678                 result := (others => negative);
 679                 if e_in.data_len(2) = '1' then
 680                     result(31 downto 16) := c_in(31 downto 16);
 681                 end if;
 682                 if e_in.data_len(2) = '1' or e_in.data_len(1) = '1' then
 683                     result(15 downto 8) := c_in(15 downto 8);
 684                 end if;
 685                 result(7 downto 0) := c_in(7 downto 0);
 686                 result_en := '1';
 687             when OP_ISEL =>
 688                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 689                 if e_in.cr(31-crbit) = '1' then
 690                     result := a_in;
 691                 else
 692                     result := b_in;
 693                 end if;
 694                 result_en := '1';
 695             when OP_CROP =>
 696                 cr_op := insn_cr(e_in.insn);
 697                 report "CR OP " & to_hstring(cr_op);
 698                 if cr_op(0) = '0' then -- MCRF
 699                     bf := insn_bf(e_in.insn);
 700                     bfa := insn_bfa(e_in.insn);
 701                     v.e.write_cr_enable := '1';
 702                     crnum := to_integer(unsigned(bf));
 703                     scrnum := to_integer(unsigned(bfa));
 704                     v.e.write_cr_mask := num_to_fxm(crnum);
 705                     for i in 0 to 7 loop
 706                         lo := (7-i)*4;
 707                         hi := lo + 3;
 708                         if i = scrnum then
 709                             newcrf := e_in.cr(hi downto lo);
 710                         end if;
 711                     end loop;
 712                     for i in 0 to 7 loop
 713                         lo := i*4;
 714                         hi := lo + 3;
 715                         v.e.write_cr_data(hi downto lo) := newcrf;
 716                     end loop;
 717                 else
 718                     v.e.write_cr_enable := '1';
 719                     bt := insn_bt(e_in.insn);
 720                     ba := insn_ba(e_in.insn);
 721                     bb := insn_bb(e_in.insn);
 722                     btnum := 31 - to_integer(unsigned(bt));
 723                     banum := 31 - to_integer(unsigned(ba));
 724                     bbnum := 31 - to_integer(unsigned(bb));
 725                     -- Bits 5-8 of cr_op give the truth table of the requested
 726                     -- logical operation
 727                     cr_operands := e_in.cr(banum) & e_in.cr(bbnum);
 728                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 729                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 730                     for i in 0 to 31 loop
 731                         if i = btnum then
 732                             v.e.write_cr_data(i) := crresult;
 733                         else
 734                             v.e.write_cr_data(i) := e_in.cr(i);
 735                         end if;
 736                     end loop;
 737                 end if;
 738             when OP_MFMSR =>
 739                 result := ctrl.msr;
 740                 result_en := '1';
 741             when OP_MFSPR =>
 742                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 743                     "=" & to_hstring(a_in);
 744                 result_en := '1';
 745                 if is_fast_spr(e_in.read_reg1) then
 746                     result := a_in;
 747                     if decode_spr_num(e_in.insn) = SPR_XER then
 748                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 749                         result(63 downto 32) := (others => '0');
 750                         result(63-32) := v.e.xerc.so;
 751                         result(63-33) := v.e.xerc.ov;
 752                         result(63-34) := v.e.xerc.ca;
 753                         result(63-35 downto 63-43) := "000000000";
 754                         result(63-44) := v.e.xerc.ov32;
 755                         result(63-45) := v.e.xerc.ca32;
 756                     end if;
 757                 else
 758                     case decode_spr_num(e_in.insn) is
 759                     when SPR_TB =>
 760                         result := ctrl.tb;
 761                     when SPR_DEC =>
 762                         result := ctrl.dec;
 763                     when others =>
 764                         -- mfspr from unimplemented SPRs should be a nop in
 765                         -- supervisor mode and a program interrupt for user mode
 766                         result := c_in;
 767                         if ctrl.msr(MSR_PR) = '1' then
 768                             illegal := '1';
 769                         end if;
 770                     end case;
 771                 end if;
 772             when OP_MFCR =>
 773                 if e_in.insn(20) = '0' then
 774                     -- mfcr
 775                     result := x"00000000" & e_in.cr;
 776                 else
 777                     -- mfocrf
 778                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 779                     result := (others => '0');
 780                     for i in 0 to 7 loop
 781                         lo := (7-i)*4;
 782                         hi := lo + 3;
 783                         if crnum = i then
 784                             result(hi downto lo) := e_in.cr(hi downto lo);
 785                         end if;
 786                     end loop;
 787                 end if;
 788                 result_en := '1';
 789             when OP_MTCRF =>
 790                 v.e.write_cr_enable := '1';
 791                 if e_in.insn(20) = '0' then
 792                     -- mtcrf
 793                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 794                 else
 795                     -- mtocrf: We require one hot priority encoding here
 796                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 797                     v.e.write_cr_mask := num_to_fxm(crnum);
 798                 end if;
 799                 v.e.write_cr_data := c_in(31 downto 0);
 800             when OP_MTMSRD =>
 801                 if e_in.insn(16) = '1' then
 802                     -- just update EE and RI
 803                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 804                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 805                 else
 806                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 807                     -- and 63 (LE) (IBM bit numbering)
 808                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 809                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 810                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 811                     if c_in(MSR_PR) = '1' then
 812                         ctrl_tmp.msr(MSR_EE) <= '1';
 813                         ctrl_tmp.msr(MSR_IR) <= '1';
 814                         ctrl_tmp.msr(MSR_DR) <= '1';
 815                     end if;
 816                 end if;
 817             when OP_MTSPR =>
 818                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 819                     "=" & to_hstring(c_in);
 820                 if is_fast_spr(e_in.write_reg) then
 821                     result := c_in;
 822                     result_en := '1';
 823                     if decode_spr_num(e_in.insn) = SPR_XER then
 824                         v.e.xerc.so := c_in(63-32);
 825                         v.e.xerc.ov := c_in(63-33);
 826                         v.e.xerc.ca := c_in(63-34);
 827                         v.e.xerc.ov32 := c_in(63-44);
 828                         v.e.xerc.ca32 := c_in(63-45);
 829                         v.e.write_xerc_enable := '1';
 830                     end if;
 831                 else
 832                     -- slow spr
 833                     case decode_spr_num(e_in.insn) is
 834                     when SPR_DEC =>
 835                         ctrl_tmp.dec <= c_in;
 836                     when others =>
 837                         -- mtspr to unimplemented SPRs should be a nop in
 838                         -- supervisor mode and a program interrupt for user mode
 839                         if ctrl.msr(MSR_PR) = '1' then
 840                             illegal := '1';
 841                         end if;
 842                     end case;
 843                 end if;
 844             when OP_POPCNT =>
 845                 result := popcnt_result;
 846                 result_en := '1';
 847             when OP_PRTY =>
 848                 result := parity_result;
 849                 result_en := '1';
 850             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
 851                 result := rotator_result;
 852                 if e_in.output_carry = '1' then
 853                     set_carry(v.e, rotator_carry, rotator_carry);
 854                 end if;
 855                 result_en := '1';
 856
 857             when OP_ISYNC =>
 858                 f_out.redirect <= '1';
 859                 f_out.redirect_nia <= next_nia;
 860
 861             when OP_ICBI =>
 862                 icache_inval <= '1';
 863
 864             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
 865                 v.e.valid := '0';
 866                 v.mul_in_progress := '1';
 867                 stall_out <= '1';
 868                 x_to_multiply.valid <= '1';
 869
 870             when OP_DIV | OP_DIVE | OP_MOD =>
 871                 v.e.valid := '0';
 872                 v.div_in_progress := '1';
 873                 stall_out <= '1';
 874                 x_to_divider.valid <= '1';
 875
 876             when others =>
 877                 terminate_out <= '1';
 878                 report "illegal";
 879             end case;
 880
 881             v.e.rc := e_in.rc and e_in.valid;
 882
 883             -- Update LR on the next cycle after a branch link
 884             --
 885             -- WARNING: The LR update isn't tracked by our hazard tracker. This
 886             --          will work (well I hope) because it only happens on branches
 887             --          which will flush all decoded instructions. By the time
 888             --          fetch catches up, we'll have the new LR. This will
 889             --          *not* work properly however if we have a branch predictor,
 890             --          in which case the solution would probably be to keep a
 891             --          local cache of the updated LR in execute1 (flushed on
 892             --          exceptions) that is used instead of the value from
 893             --          decode when its content is valid.
 894             if e_in.lr = '1' then
 895                 v.lr_update := '1';
 896                 v.next_lr := next_nia;
 897                 v.e.valid := '0';
 898                 report "Delayed LR update to " & to_hstring(next_nia);
 899                 stall_out <= '1';
 900             end if;
 901
 902         elsif e_in.valid = '1' then
 903             -- instruction for other units, i.e. LDST
 904             v.ldst_nia := e_in.nia;
 905             v.e.valid := '0';
 906             if e_in.unit = LDST then
 907                 lv.valid := '1';
 908             end if;
 909
 910         elsif r.lr_update = '1' then
 911             result_en := '1';
 912             result := r.next_lr;
 913             v.e.write_reg := fast_spr_num(SPR_LR);
 914             v.e.valid := '1';
 915         elsif r.cntz_in_progress = '1' then
 916             -- cnt[lt]z always takes two cycles
 917             result := countzero_result;
 918             result_en := '1';
 919             v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 920             v.e.rc := v.slow_op_rc;
 921             v.e.xerc := v.slow_op_xerc;
 922             v.e.valid := '1';
 923         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
 924             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
 925                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
 926                 if r.mul_in_progress = '1' then
 927                     result := multiply_to_x.write_reg_data;
 928                     overflow := multiply_to_x.overflow;
 929                 else
 930                     result := divider_to_x.write_reg_data;
 931                     overflow := divider_to_x.overflow;
 932                 end if;
 933                 result_en := '1';
 934                 v.e.write_reg := gpr_to_gspr(v.slow_op_dest);
 935                 v.e.rc := v.slow_op_rc;
 936                 v.e.xerc := v.slow_op_xerc;
 937                 v.e.write_xerc_enable := v.slow_op_oe;
 938                 -- We must test oe because the RC update code in writeback
 939                 -- will use the xerc value to set CR0:SO so we must not clobber
 940                 -- xerc if OE wasn't set.
 941                 if v.slow_op_oe = '1' then
 942                     v.e.xerc.ov := overflow;
 943                     v.e.xerc.ov32 := overflow;
 944                     v.e.xerc.so := v.slow_op_xerc.so or overflow;
 945                 end if;
 946                 v.e.valid := '1';
 947             else
 948                 stall_out <= '1';
 949                 v.mul_in_progress := r.mul_in_progress;
 950                 v.div_in_progress := r.div_in_progress;
 951             end if;
 952         end if;
 953
 954         if illegal = '1' then
 955             exception := '1';
 956             ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 957             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 958             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
 959             -- set bit 44 to indicate we have an illegal
 960             ctrl_tmp.srr1(63 - 44) <= '1';
 961             report "illegal";
 962         end if;
 963         if exception = '1' then
 964             v.e.exc_write_enable := '1';
 965             if exception_nextpc = '1' then
 966                 v.e.exc_write_data := next_nia;
 967             end if;
 968             ctrl_tmp.irq_state <= WRITE_SRR1;
 969             v.e.valid := '1';
 970         end if;
 971
 972         v.e.write_data := result;
 973         v.e.write_enable := result_en;
 974
 975         -- generate DSI for load/store exceptions
 976         if l_in.exception = '1' then
 977             if l_in.segment_fault = '0' then
 978                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#300#, 64));
 979             else
 980                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#380#, 64));
 981             end if;
 982             ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 983             v.e.exc_write_enable := '1';
 984             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 985             v.e.exc_write_data := r.ldst_nia;
 986             ctrl_tmp.irq_state <= WRITE_SRR1;
 987             v.e.valid := '1';   -- complete the original load or store
 988         end if;
 989
 990         -- Outputs to loadstore1 (async)
 991         lv.op := e_in.insn_type;
 992         lv.addr1 := a_in;
 993         lv.addr2 := b_in;
 994         lv.data := c_in;
 995         lv.write_reg := gspr_to_gpr(e_in.write_reg);
 996         lv.length := e_in.data_len;
 997         lv.byte_reverse := e_in.byte_reverse;
 998         lv.sign_extend := e_in.sign_extend;
 999         lv.update := e_in.update;
1000         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1001         lv.xerc := v.e.xerc;
1002         lv.reserve := e_in.reserve;
1003         lv.rc := e_in.rc;
1004         lv.spr_num := decode_spr_num(e_in.insn);
1005         -- decode l*cix and st*cix instructions here
1006         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1007             e_in.insn(5 downto 1) = "10101" then
1008             lv.ci := '1';
1009         end if;
1010         lv.virt_mode := ctrl.msr(MSR_DR);
1011         lv.priv_mode := not ctrl.msr(MSR_PR);
1012
1013         -- Update registers
1014         rin <= v;
1015
1016         -- update outputs
1017         --f_out <= r.f;
1018         l_out <= lv;
1019         e_out <= r.e;
1020         flush_out <= f_out.redirect;
1021     end process;
1022 end architecture behaviour;