experiments10_verilog/Makefile

   1
   2         LOGICAL_SYNTHESIS = Yosys
   3        PHYSICAL_SYNTHESIS = Coriolis
   4                DESIGN_KIT = cmos45
   5             YOSYS_FLATTEN = No
   6                      CHIP = chip
   7                      CORE = add
   8             USE_CLOCKTREE = Yes
   9                 USE_DEBUG = No
  10                  USE_KITE = No
  11                   RM_CHIP = Yes
  12
  13                  NETLISTS = $(shell cat netlists.txt)
  14 #                PATTERNS = add_r
  15
  16
  17  include ./mk/design-flow.mk
  18
  19 # generate verilog file from python nmigen command
  20 add.v: add.py
  21         python3 add.py
  22
  23 chip_r.vst: add.vst
  24         -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
  25
  26 chip_r.ap: chip_r.vst
  27
  28
  29 blif:      add.blif
  30 vst:       add.vst
  31
  32 lvx:       lvx-chip_r
  33 druc:      druc-chip_r
  34 dreal:     dreal-chip_r
  35 flatph:    flatph-chip_r
  36 view:      cgt-chip_r
  37
  38 layout:    chip_r.ap
  39 gds:       chip_r.gds
  40 gds_flat:  chip_r_flat.gds
  41 cif:       chip_r.cif
  42
  43 view:      cgt-chip_r
  44 sim:       asimut-add_r