experiments7/Status.rst

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   3 Status Report on Block Building
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   7 April 04, 2020 -- Optimized Placement
   8 =====================================
   9
  10 The placement of the ALU16 as been optimized.
  11
  12 * The gates of the top level netlist that form a regular array (datapath)
  13   have been manually placed between the add & sub blocks.
  14
  15 * The connectors of the add & sub blocks have been put face to face to have
  16   as much as possible straight lines.
  17
  18 * The connector of the add & sub block have been placed in a "slice"
  19   way: that is a(x), b(x) & o(x) all in the same slice. A slice is one
  20   horizontal row of standard cells.
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  22 As a comparison, an alternate version of the script "doAlu16Flat.py" has
  23 been created to make an area comparison if everything is left to the
  24 automaic P&R. For such a small example, they clearly win. Have to confirm
  25 that on bigger ones.
  26
  27 .. note:: **Never rotate a block**. The routing directions are defined
  28           for all the chip area. And the connectors will be in the
  29           wrong layers, generating impossible routing configurations.
  30             This may be possible, but at the cost of *wrapping* the
  31           block in a small corona (has yet to be devellopped).
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  33
  34 Open/Remaining Questions
  35 ~~~~~~~~~~~~~~~~~~~~~~~~
  36
  37 * The placement is manual, but the routing is automatic for the center
  38   part. The router still makes some "bad choices", so it would be
  39   interesting to do a manual routing too.
  40
  41 * The layout is not completely finished: the filler cells are missing
  42   at top level. Have to separate and export that lone feature from
  43   Etesian (placer).
  44
  45 * The way to "rebuild" the datapath information is not robust. It relies
  46   on the way Yosys/ABC synthesis the mux+DFF, if it changes, it will fail.
  47
  48 * Corollary: it may make senses to directly describe some part of the
  49   design at cell level and not let it synthesis by Yosys, but in this
  50   case how to "import" at nMigen level.
  51
  52 * The place_datapath() and match_instance() method may be moved down to
  53   the Module class.
  54
  55 * Policy about how soon to convert into DbU.
  56
  57 * Specify the semantic of Module. Is it an instance or a model, can they
  58   be re-used in multiple blocks (should they?).