experiments9/coriolis2/settings.py

   1 # -*- Mode:Python -*-
   2
   3 import Cfg
   4 from   Hurricane import DataBase, Cell, Instance, Net
   5 from   CRL     import AllianceFramework, RoutingLayerGauge
   6 import CRL
   7 import Viewer
   8 from   helpers.overlay import CfgCache
   9 from   helpers   import overlay, l, u, n
  10 import symbolic.cmos45  # do not remove
  11 import os
  12
  13 import LibreSOCMem, pll
  14 LibreSOCMem.setup()
  15 pll.setup()
  16
  17 if os.environ.has_key('CELLS_TOP'):
  18     cellsTop = os.environ['CELLS_TOP']
  19 else:
  20     cellsTop = '../../../alliance-check-toolkit/cells'
  21
  22 db = DataBase.getDB()
  23 af = AllianceFramework.get()
  24
  25
  26 def createPLLBlackbox ():
  27     global db, af
  28     print( '  o  Creating PLL blackboxes for "ls180" design.' )
  29     rootlib  = db.getRootLibrary()
  30     lib      = rootlib.getLibrary( 'pll' )
  31     pllName = 'pll'
  32     pll     = lib.getCell( pllName )
  33     if not pll:
  34         raise ErrorMessage( 1, 'settings.createPLLBlackBox(): '
  35                                 'PLL Cell "{}" not found.' \
  36                                .format(pllName) )
  37     pll.setAbstractedSupply( True )
  38     blackboxName = 'real_pll'
  39     cell     = Cell.create( lib, blackboxName )
  40     instance = Instance.create( cell, 'real_pll', pll )
  41     state    = af.getCatalog().getState( blackboxName, True )
  42     state.setCell( cell )
  43     state.setLogical( True )
  44     state.setInMemory( True )
  45     print( '     - {}.'.format(cell) )
  46     for masterNet in pll.getNets():
  47         if not masterNet.isExternal():
  48             continue
  49         net = Net.create( cell, masterNet.getName() )
  50         net.setDirection( masterNet.getDirection() )
  51         net.setType( masterNet.getType() )
  52         net.setExternal( True )
  53         net.setGlobal( masterNet.isGlobal() )
  54         if masterNet.isSupply():
  55             continue
  56         plug = instance.getPlug( masterNet )
  57         plug.setNet( net )
  58
  59 def createSramBlackbox ():
  60     global db, af
  61     print( '  o  Creating SRAM blackboxes for "ls180" design.' )
  62     rootlib  = db.getRootLibrary()
  63     lib      = rootlib.getLibrary( 'LibreSOCMem' )
  64     sramName = 'spblock_512w64b8w'
  65     sram     = lib.getCell( sramName )
  66     if not sram:
  67         raise ErrorMessage( 1, 'settings.createSramBlocks(): '
  68                                 'SRAM Cell "{}" not found.' \
  69                                .format(sramName) )
  70     sram.setAbstractedSupply( True )
  71     blackboxeNames = [ 'spblock_512w64b8w_0',
  72                        'spblock_512w64b8w_1',
  73                        'spblock_512w64b8w_2',
  74                        'spblock_512w64b8w_3',
  75                      ]
  76     for blackboxName in blackboxeNames:
  77         cell     = Cell.create( lib, blackboxName )
  78         instance = Instance.create( cell, 'real_sram', sram )
  79         state    = af.getCatalog().getState( blackboxName, True )
  80         state.setCell( cell )
  81         state.setLogical( True )
  82         state.setInMemory( True )
  83         print( '     - {}.'.format(cell) )
  84         for masterNet in sram.getNets():
  85             if not masterNet.isExternal():
  86                 continue
  87             net = Net.create( cell, masterNet.getName() )
  88             net.setDirection( masterNet.getDirection() )
  89             net.setType( masterNet.getType() )
  90             net.setExternal( True )
  91             net.setGlobal( masterNet.isGlobal() )
  92             if masterNet.isSupply():
  93                 continue
  94             plug = instance.getPlug( masterNet )
  95             plug.setNet( net )
  96
  97
  98 with CfgCache('', priority=Cfg.Parameter.Priority.UserFile) as cfg:
  99     cfg.misc.catchCore               = False
 100     cfg.misc.info                    = False
 101     cfg.misc.paranoid                = False
 102     cfg.misc.bug                     = False
 103     cfg.misc.logMode                 = True
 104     cfg.misc.verboseLevel1           = True
 105     cfg.misc.verboseLevel2           = True
 106     cfg.anabatic.edgeLenght          = 24
 107     cfg.anabatic.edgeWidth           = 8
 108     cfg.anabatic.topRoutingLayer     = 'METAL5'
 109     cfg.etesian.graphics             = 3
 110
 111     #cfg.katana.searchHalo           = 30
 112     #cfg.katana.eventsLimit          = 1000000
 113     #cfg.katana.hTracksReservedLocal = 7
 114
 115     # Run 2 (make-cgt-2.log)
 116     #cfg.etesian.effort              = 2
 117     #cfg.etesian.uniformDensity      = True
 118     #cfg.etesian.spaceMargin         = 0.05
 119     #cfg.etesian.aspectRatio         = 1.0
 120     #cfg.katana.vTracksReservedLocal = 4
 121     #cfg.katana.hTracksReservedLocal = 4
 122
 123     # Run 3 (make-cgt-3.log)
 124     #cfg.etesian.effort              = 2
 125     #cfg.etesian.uniformDensity      = False
 126     #cfg.etesian.spaceMargin         = 0.05
 127     #cfg.etesian.aspectRatio         = 1.0
 128     #cfg.katana.vTracksReservedLocal = 5
 129     #cfg.katana.hTracksReservedLocal = 5
 130
 131     # Run 4 (make-cgt-4.log)
 132     #cfg.etesian.effort              = 2
 133     #cfg.etesian.uniformDensity      = True
 134     #cfg.etesian.spaceMargin         = 0.05
 135     #cfg.etesian.aspectRatio         = 1.0
 136
 137     # Run 5 (make-cgt-5.log)
 138     cfg.etesian.effort               = 2
 139     cfg.etesian.uniformDensity       = True
 140     cfg.etesian.spaceMargin          = 0.05
 141     cfg.etesian.aspectRatio          = 1.0
 142     cfg.katana.useGlobalEstimate     = False
 143     cfg.katana.vTracksReservedLocal  = 7
 144     cfg.katana.hTracksReservedLocal  = 6
 145     cfg.katana.bloatOverloadAdd      = 4
 146     cfg.conductor.stopLevel          = 0
 147     cfg.conductor.maxPlaceIterations = 2
 148     cfg.conductor.useFixedAbHeight   = False
 149
 150     env = CRL.AllianceFramework.get().getEnvironment()
 151     env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' )
 152     env.addSYSTEM_LIBRARY(library=cellsTop+'/niolib',
 153                            mode=CRL.Environment.Prepend )
 154     env.addSYSTEM_LIBRARY(library=cellsTop+'/nsxlib',
 155                           mode=CRL.Environment.Prepend )
 156     env.setPOWER ('vdd')
 157     env.setGROUND('vss')
 158
 159 Viewer.Graphics.setStyle('Alliance.Classic [black]')
 160
 161 # XXX cannot run this in non-NDA'd mode because there is no
 162 # equivalent to NDA.node180.tsmc_c018.LibreSOCMem (or PLL)
 163 # TODO: create a fake one
 164 with overlay.UpdateSession():
 165     createSramBlackbox()
 166     createPLLBlackbox()
 167
 168 print( '  o  Successfully run "<>/coriolis2/settings.py".' )
 169 print( '     - CELLS_TOP = "{}"'.format(cellsTop) )
 170