fetch1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity fetch1 is
   9         generic(
  10                 RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0')
  11         );
  12         port(
  13                 clk           : in std_ulogic;
  14                 rst           : in std_ulogic;
  15
  16                 -- Control inputs:
  17                 stall_in      : in std_ulogic;
  18                 flush_in      : in std_ulogic;
  19
  20                 -- redirect from execution unit
  21                 e_in          : in Execute1ToFetch1Type;
  22
  23                 -- fetch data out
  24                 f_out         : out Fetch1ToFetch2Type
  25         );
  26 end entity fetch1;
  27
  28 architecture behaviour of fetch1 is
  29         type reg_internal_type is record
  30                 nia_next : std_ulogic_vector(63 downto 0);
  31         end record;
  32         signal r_int, rin_int : reg_internal_type;
  33         signal r, rin : Fetch1ToFetch2Type;
  34 begin
  35         regs : process(clk)
  36         begin
  37                 if rising_edge(clk) then
  38                         r <= rin;
  39                         r_int <= rin_int;
  40                 end if;
  41         end process;
  42
  43         comb : process(all)
  44                 variable v     : Fetch1ToFetch2Type;
  45                 variable v_int : reg_internal_type;
  46         begin
  47                 v := r;
  48                 v_int := r_int;
  49
  50                 if stall_in = '0' then
  51                         v.nia := r_int.nia_next;
  52                         v_int.nia_next := std_logic_vector(unsigned(r_int.nia_next) + 4);
  53                 end if;
  54
  55                 if e_in.redirect = '1' then
  56                         v.nia := e_in.redirect_nia;
  57                         v_int.nia_next := std_logic_vector(unsigned(e_in.redirect_nia) + 4);
  58                 end if;
  59
  60                 if rst = '1' then
  61                         v.nia := RESET_ADDRESS;
  62                         v_int.nia_next := std_logic_vector(unsigned(RESET_ADDRESS) + 4);
  63                 end if;
  64
  65                 -- Update registers
  66                 rin <= v;
  67                 rin_int <= v_int;
  68
  69                 -- Update outputs
  70                 f_out <= r;
  71
  72                 report "fetch1 R:" & std_ulogic'image(e_in.redirect) & " v.nia:" & to_hstring(v.nia) & " f_out.nia:" & to_hstring(f_out.nia);
  73         end process;
  74
  75 end architecture behaviour;