fpga/acorn-cle-215.xdc

   1 ################################################################################
   2 # clkin, reset, uart pins...
   3 ################################################################################
   4 # clk200:0.p
   5 set_property LOC J19 [get_ports {clk200_p}]
   6 set_property IOSTANDARD DIFF_SSTL15 [get_ports {clk200_p}]
   7
   8 # clk200:0.n
   9 set_property LOC H19 [get_ports {clk200_n}]
  10 set_property IOSTANDARD DIFF_SSTL15 [get_ports {clk200_n}]
  11
  12 ################################################################################
  13 # P2 header used as UART
  14 ################################################################################
  15
  16 #set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { p2_io1_n }];
  17 #set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { p2_io1_p }];
  18 # AIO2_N
  19 set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { uart_tx }];
  20 # AIO2_P
  21 set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { uart_rx }];
  22
  23 ################################################################################
  24 # DRAM
  25 ################################################################################
  26
  27 # ddram:0.a
  28 set_property LOC M15 [get_ports {ddram_a[0]}]
  29 set_property SLEW FAST [get_ports {ddram_a[0]}]
  30 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[0]}]
  31
  32 # ddram:0.a
  33 set_property LOC L21 [get_ports {ddram_a[1]}]
  34 set_property SLEW FAST [get_ports {ddram_a[1]}]
  35 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[1]}]
  36
  37 # ddram:0.a
  38 set_property LOC M16 [get_ports {ddram_a[2]}]
  39 set_property SLEW FAST [get_ports {ddram_a[2]}]
  40 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[2]}]
  41
  42 # ddram:0.a
  43 set_property LOC L18 [get_ports {ddram_a[3]}]
  44 set_property SLEW FAST [get_ports {ddram_a[3]}]
  45 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[3]}]
  46
  47 # ddram:0.a
  48 set_property LOC K21 [get_ports {ddram_a[4]}]
  49 set_property SLEW FAST [get_ports {ddram_a[4]}]
  50 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[4]}]
  51
  52 # ddram:0.a
  53 set_property LOC M18 [get_ports {ddram_a[5]}]
  54 set_property SLEW FAST [get_ports {ddram_a[5]}]
  55 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[5]}]
  56
  57 # ddram:0.a
  58 set_property LOC M21 [get_ports {ddram_a[6]}]
  59 set_property SLEW FAST [get_ports {ddram_a[6]}]
  60 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[6]}]
  61
  62 # ddram:0.a
  63 set_property LOC N20 [get_ports {ddram_a[7]}]
  64 set_property SLEW FAST [get_ports {ddram_a[7]}]
  65 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[7]}]
  66
  67 # ddram:0.a
  68 set_property LOC M20 [get_ports {ddram_a[8]}]
  69 set_property SLEW FAST [get_ports {ddram_a[8]}]
  70 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[8]}]
  71
  72 # ddram:0.a
  73 set_property LOC N19 [get_ports {ddram_a[9]}]
  74 set_property SLEW FAST [get_ports {ddram_a[9]}]
  75 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[9]}]
  76
  77 # ddram:0.a
  78 set_property LOC J21 [get_ports {ddram_a[10]}]
  79 set_property SLEW FAST [get_ports {ddram_a[10]}]
  80 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[10]}]
  81
  82 # ddram:0.a
  83 set_property LOC M22 [get_ports {ddram_a[11]}]
  84 set_property SLEW FAST [get_ports {ddram_a[11]}]
  85 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[11]}]
  86
  87 # ddram:0.a
  88 set_property LOC K22 [get_ports {ddram_a[12]}]
  89 set_property SLEW FAST [get_ports {ddram_a[12]}]
  90 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[12]}]
  91
  92 # ddram:0.a
  93 set_property LOC N18 [get_ports {ddram_a[13]}]
  94 set_property SLEW FAST [get_ports {ddram_a[13]}]
  95 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[13]}]
  96
  97 # ddram:0.a
  98 set_property LOC N22 [get_ports {ddram_a[14]}]
  99 set_property SLEW FAST [get_ports {ddram_a[14]}]
 100 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[14]}]
 101
 102 # ddram:0.a
 103 set_property LOC J22 [get_ports {ddram_a[15]}]
 104 set_property SLEW FAST [get_ports {ddram_a[15]}]
 105 set_property IOSTANDARD SSTL15 [get_ports {ddram_a[15]}]
 106
 107 # ddram:0.ba
 108 set_property LOC L19 [get_ports {ddram_ba[0]}]
 109 set_property SLEW FAST [get_ports {ddram_ba[0]}]
 110 set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[0]}]
 111
 112 # ddram:0.ba
 113 set_property LOC J20 [get_ports {ddram_ba[1]}]
 114 set_property SLEW FAST [get_ports {ddram_ba[1]}]
 115 set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[1]}]
 116
 117 # ddram:0.ba
 118 set_property LOC L20 [get_ports {ddram_ba[2]}]
 119 set_property SLEW FAST [get_ports {ddram_ba[2]}]
 120 set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[2]}]
 121
 122 # ddram:0.ras_n
 123 set_property LOC H20 [get_ports {ddram_ras_n}]
 124 set_property SLEW FAST [get_ports {ddram_ras_n}]
 125 set_property IOSTANDARD SSTL15 [get_ports {ddram_ras_n}]
 126
 127 # ddram:0.cas_n
 128 set_property LOC K18 [get_ports {ddram_cas_n}]
 129 set_property SLEW FAST [get_ports {ddram_cas_n}]
 130 set_property IOSTANDARD SSTL15 [get_ports {ddram_cas_n}]
 131
 132 # ddram:0.we_n
 133 set_property LOC L16 [get_ports {ddram_we_n}]
 134 set_property SLEW FAST [get_ports {ddram_we_n}]
 135 set_property IOSTANDARD SSTL15 [get_ports {ddram_we_n}]
 136
 137 # ddram:0.dm
 138 set_property LOC A19 [get_ports {ddram_dm[0]}]
 139 set_property SLEW FAST [get_ports {ddram_dm[0]}]
 140 set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[0]}]
 141
 142 # ddram:0.dm
 143 set_property LOC G22 [get_ports {ddram_dm[1]}]
 144 set_property SLEW FAST [get_ports {ddram_dm[1]}]
 145 set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[1]}]
 146
 147 # ddram:0.dq
 148 set_property LOC D19 [get_ports {ddram_dq[0]}]
 149 set_property SLEW FAST [get_ports {ddram_dq[0]}]
 150 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[0]}]
 151 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[0]}]
 152
 153 # ddram:0.dq
 154 set_property LOC B20 [get_ports {ddram_dq[1]}]
 155 set_property SLEW FAST [get_ports {ddram_dq[1]}]
 156 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[1]}]
 157 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[1]}]
 158
 159 # ddram:0.dq
 160 set_property LOC E19 [get_ports {ddram_dq[2]}]
 161 set_property SLEW FAST [get_ports {ddram_dq[2]}]
 162 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[2]}]
 163 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[2]}]
 164
 165 # ddram:0.dq
 166 set_property LOC A20 [get_ports {ddram_dq[3]}]
 167 set_property SLEW FAST [get_ports {ddram_dq[3]}]
 168 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[3]}]
 169 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[3]}]
 170
 171 # ddram:0.dq
 172 set_property LOC F19 [get_ports {ddram_dq[4]}]
 173 set_property SLEW FAST [get_ports {ddram_dq[4]}]
 174 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[4]}]
 175 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[4]}]
 176
 177 # ddram:0.dq
 178 set_property LOC C19 [get_ports {ddram_dq[5]}]
 179 set_property SLEW FAST [get_ports {ddram_dq[5]}]
 180 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[5]}]
 181 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[5]}]
 182
 183 # ddram:0.dq
 184 set_property LOC F20 [get_ports {ddram_dq[6]}]
 185 set_property SLEW FAST [get_ports {ddram_dq[6]}]
 186 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[6]}]
 187 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[6]}]
 188
 189 # ddram:0.dq
 190 set_property LOC C18 [get_ports {ddram_dq[7]}]
 191 set_property SLEW FAST [get_ports {ddram_dq[7]}]
 192 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[7]}]
 193 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[7]}]
 194
 195 # ddram:0.dq
 196 set_property LOC E22 [get_ports {ddram_dq[8]}]
 197 set_property SLEW FAST [get_ports {ddram_dq[8]}]
 198 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[8]}]
 199 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[8]}]
 200
 201 # ddram:0.dq
 202 set_property LOC G21 [get_ports {ddram_dq[9]}]
 203 set_property SLEW FAST [get_ports {ddram_dq[9]}]
 204 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[9]}]
 205 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[9]}]
 206
 207 # ddram:0.dq
 208 set_property LOC D20 [get_ports {ddram_dq[10]}]
 209 set_property SLEW FAST [get_ports {ddram_dq[10]}]
 210 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[10]}]
 211 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[10]}]
 212
 213 # ddram:0.dq
 214 set_property LOC E21 [get_ports {ddram_dq[11]}]
 215 set_property SLEW FAST [get_ports {ddram_dq[11]}]
 216 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[11]}]
 217 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[11]}]
 218
 219 # ddram:0.dq
 220 set_property LOC C22 [get_ports {ddram_dq[12]}]
 221 set_property SLEW FAST [get_ports {ddram_dq[12]}]
 222 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[12]}]
 223 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[12]}]
 224
 225 # ddram:0.dq
 226 set_property LOC D21 [get_ports {ddram_dq[13]}]
 227 set_property SLEW FAST [get_ports {ddram_dq[13]}]
 228 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[13]}]
 229 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[13]}]
 230
 231 # ddram:0.dq
 232 set_property LOC B22 [get_ports {ddram_dq[14]}]
 233 set_property SLEW FAST [get_ports {ddram_dq[14]}]
 234 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[14]}]
 235 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[14]}]
 236
 237 # ddram:0.dq
 238 set_property LOC D22 [get_ports {ddram_dq[15]}]
 239 set_property SLEW FAST [get_ports {ddram_dq[15]}]
 240 set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[15]}]
 241 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[15]}]
 242
 243 # ddram:0.dqs_p
 244 set_property LOC F18 [get_ports {ddram_dqs_p[0]}]
 245 set_property SLEW FAST [get_ports {ddram_dqs_p[0]}]
 246 set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[0]}]
 247
 248 # ddram:0.dqs_p
 249 set_property LOC B21 [get_ports {ddram_dqs_p[1]}]
 250 set_property SLEW FAST [get_ports {ddram_dqs_p[1]}]
 251 set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[1]}]
 252
 253 # ddram:0.dqs_n
 254 set_property LOC E18 [get_ports {ddram_dqs_n[0]}]
 255 set_property SLEW FAST [get_ports {ddram_dqs_n[0]}]
 256 set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[0]}]
 257
 258 # ddram:0.dqs_n
 259 set_property LOC A21 [get_ports {ddram_dqs_n[1]}]
 260 set_property SLEW FAST [get_ports {ddram_dqs_n[1]}]
 261 set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[1]}]
 262
 263 # ddram:0.clk_p
 264 set_property LOC K17 [get_ports {ddram_clk_p}]
 265 set_property SLEW FAST [get_ports {ddram_clk_p}]
 266 set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_p}]
 267
 268 # ddram:0.clk_n
 269 set_property LOC J17 [get_ports {ddram_clk_n}]
 270 set_property SLEW FAST [get_ports {ddram_clk_n}]
 271 set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_n}]
 272
 273 # ddram:0.cke
 274 set_property LOC H22 [get_ports {ddram_cke}]
 275 set_property SLEW FAST [get_ports {ddram_cke}]
 276 set_property IOSTANDARD SSTL15 [get_ports {ddram_cke}]
 277
 278 # ddram:0.odt
 279 set_property LOC K19 [get_ports {ddram_odt}]
 280 set_property SLEW FAST [get_ports {ddram_odt}]
 281 set_property IOSTANDARD SSTL15 [get_ports {ddram_odt}]
 282
 283 # ddram:0.reset_n
 284 set_property LOC K16 [get_ports {ddram_reset_n}]
 285 set_property SLEW FAST [get_ports {ddram_reset_n}]
 286 set_property IOSTANDARD LVCMOS15 [get_ports {ddram_reset_n}]
 287
 288 ################################################################################
 289 # LEDs
 290 ################################################################################
 291
 292 set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { led0 }];
 293 set_property -dict { PACKAGE_PIN H3 IOSTANDARD LVCMOS33 } [get_ports { led1 }];
 294 set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { led2 }];
 295 set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { led3 }];
 296
 297 ###############################################################################
 298 # SPI Flash
 299 ###############################################################################
 300
 301 set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_cs_n }];
 302 set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_mosi }];
 303 set_property -dict { PACKAGE_PIN R22 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_miso }];
 304 set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_wp_n }];
 305 set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_hold_n }];
 306
 307
 308 ################################################################################
 309 # Design constraints
 310 ################################################################################
 311
 312 set_property INTERNAL_VREF 0.750 [get_iobanks 34]
 313 set_property CONFIG_MODE SPIx4 [current_design]
 314 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
 315 set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]
 316 set_property CONFIG_VOLTAGE 3.3 [current_design]
 317 set_property CFGBVS VCCO [current_design]
 318 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
 319 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
 320 set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Div-1 [current_design]
 321
 322 ################################################################################
 323 # Clock constraints
 324 ################################################################################
 325
 326
 327 create_clock -name clk200_p -period 5.0 [get_nets clk200_p]
 328
 329 ################################################################################
 330 # False path constraints
 331 ################################################################################
 332
 333
 334 set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}]
 335
 336 set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
 337
 338 set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]