fpga/clk_gen_ecp5.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 entity clock_generator is
   5     generic (
   6         CLK_INPUT_HZ  : positive := 12000000;
   7         CLK_OUTPUT_HZ : positive := 50000000
   8         );
   9
  10     port (
  11         ext_clk        : in  std_logic;
  12         pll_rst_in   : in  std_logic;
  13         pll_clk_out : out std_logic;
  14         pll_locked_out : out std_logic
  15         );
  16
  17 end entity clock_generator;
  18
  19 architecture bypass of clock_generator is
  20
  21     -- prototype of ECP5 PLL
  22     component EHXPLLL is
  23         generic (
  24             CLKI_DIV : integer := 1;
  25             CLKFB_DIV : integer := 1;
  26             CLKOP_DIV : integer := 8;
  27             CLKOS_DIV : integer := 8;
  28             CLKOS2_DIV : integer := 8;
  29             CLKOS3_DIV : integer := 8;
  30             CLKOP_ENABLE : string := "ENABLED";
  31             CLKOS_ENABLE : string := "DISABLED";
  32             CLKOS2_ENABLE : string := "DISABLED";
  33             CLKOS3_ENABLE : string := "DISABLED";
  34             CLKOP_CPHASE : integer := 0;
  35             CLKOS_CPHASE : integer := 0;
  36             CLKOS2_CPHASE : integer := 0;
  37             CLKOS3_CPHASE : integer := 0;
  38             CLKOP_FPHASE : integer := 0;
  39             CLKOS_FPHASE : integer := 0;
  40             CLKOS2_FPHASE : integer := 0;
  41             CLKOS3_FPHASE : integer := 0;
  42             FEEDBK_PATH : string := "CLKOP";
  43             CLKOP_TRIM_POL : string := "RISING";
  44             CLKOP_TRIM_DELAY : integer := 0;
  45             CLKOS_TRIM_POL : string := "RISING";
  46             CLKOS_TRIM_DELAY : integer := 0;
  47             OUTDIVIDER_MUXA : string := "DIVA";
  48             OUTDIVIDER_MUXB : string := "DIVB";
  49             OUTDIVIDER_MUXC : string := "DIVC";
  50             OUTDIVIDER_MUXD : string := "DIVD";
  51             PLL_LOCK_MODE : integer := 0;
  52             PLL_LOCK_DELAY : integer := 200;
  53             STDBY_ENABLE : string := "DISABLED";
  54             REFIN_RESET : string := "DISABLED";
  55             SYNC_ENABLE : string := "DISABLED";
  56             INT_LOCK_STICKY : string := "ENABLED";
  57             DPHASE_SOURCE : string := "DISABLED";
  58             PLLRST_ENA : string := "DISABLED";
  59             INTFB_WAKE : string := "DISABLED"  );
  60         port (
  61             CLKI :   in  std_logic;
  62             CLKFB :   in  std_logic;
  63             PHASESEL1 :   in  std_logic;
  64             PHASESEL0 :   in  std_logic;
  65             PHASEDIR :   in  std_logic;
  66             PHASESTEP :   in  std_logic;
  67             PHASELOADREG :   in  std_logic;
  68             STDBY :   in  std_logic;
  69             PLLWAKESYNC :   in  std_logic;
  70             RST :   in  std_logic;
  71             ENCLKOP :   in  std_logic;
  72             ENCLKOS :   in  std_logic;
  73             ENCLKOS2 :   in  std_logic;
  74             ENCLKOS3 :   in  std_logic;
  75             CLKOP :   out  std_logic;
  76             CLKOS :   out  std_logic;
  77             CLKOS2 :   out  std_logic;
  78             CLKOS3 :   out  std_logic;
  79             LOCK :   out  std_logic;
  80             INTLOCK :   out  std_logic;
  81             REFCLK :   out  std_logic;
  82             CLKINTFB :   out  std_logic  );
  83     end component;
  84
  85     signal clkop : std_logic;
  86     signal lock : std_logic;
  87
  88     -- PLL constants based on prjtrellis example
  89     constant PLL_IN : natural :=    2000000;
  90     constant PLL_OUT : natural := 600000000;
  91
  92     -- Configration for ECP5 PLL
  93     constant PLL_CLKOP_DIV : natural := PLL_OUT/CLK_OUTPUT_HZ;
  94     constant PLL_CLKFB_DIV : natural := CLK_OUTPUT_HZ/PLL_IN;
  95     constant PLL_CLKI_DIV  : natural := CLK_INPUT_HZ/PLL_IN;
  96
  97 begin
  98     pll_clk_out <= clkop;
  99     pll_locked_out <= not lock; -- FIXME: EHXPLLL lock signal active low?!?
 100
 101     clkgen: EHXPLLL
 102         generic map(
 103             CLKOP_CPHASE => 11, -- FIXME: Copied from prjtrells.
 104             CLKOP_DIV => PLL_CLKOP_DIV,
 105             CLKFB_DIV => PLL_CLKFB_DIV,
 106             CLKI_DIV  => PLL_CLKI_DIV
 107         )
 108         port map (
 109             CLKI => ext_clk,
 110             CLKOP => clkop,
 111             CLKFB => clkop,
 112             LOCK => lock,
 113             RST => pll_rst_in,
 114             PHASESEL1 => '0',
 115             PHASESEL0 => '0',
 116             PHASEDIR => '0',
 117             PHASESTEP => '0',
 118             PHASELOADREG => '0',
 119             STDBY => '0',
 120             PLLWAKESYNC => '0',
 121             ENCLKOP => '0',
 122             ENCLKOS => '0',
 123             ENCLKOS2 => '0',
 124             ENCLKOS3 => '0'
 125     );
 126
 127 end architecture bypass;