fpga/cmod_a7-35.xdc

   1 ## Clock signal 12 MHz
   2 set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
   3 create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {ext_clk}];
   4
   5 set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }];
   6 set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd  }];
   7
   8 set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { ext_rst }];
   9
  10 set_property CONFIG_VOLTAGE 3.3 [current_design]
  11 set_property CFGBVS VCCO [current_design]
  12
  13 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
  14 set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
  15 set_property CONFIG_MODE SPIx4 [current_design]