fpga/top-arty.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library unisim;
   6 use unisim.vcomponents.all;
   7
   8 library work;
   9 use work.wishbone_types.all;
  10
  11 entity toplevel is
  12     generic (
  13         MEMORY_SIZE        : integer  := 16384;
  14         RAM_INIT_FILE      : string   := "firmware.hex";
  15         RESET_LOW          : boolean  := true;
  16         CLK_FREQUENCY      : positive := 100000000;
  17         HAS_FPU            : boolean  := true;
  18         HAS_BTC            : boolean  := true;
  19         USE_LITEDRAM       : boolean  := false;
  20         NO_BRAM            : boolean  := false;
  21         DISABLE_FLATTEN_CORE : boolean := false;
  22         SCLK_STARTUPE2     : boolean := false;
  23         SPI_FLASH_OFFSET   : integer := 4194304;
  24         SPI_FLASH_DEF_CKDV : natural := 1;
  25         SPI_FLASH_DEF_QUAD : boolean := true;
  26         LOG_LENGTH         : natural := 512;
  27         USE_LITEETH        : boolean  := false;
  28         USE_TERCEL         : boolean  := false;
  29         UART_IS_16550      : boolean  := false;
  30         HAS_UART1          : boolean  := true
  31         );
  32     port(
  33         ext_clk   : in  std_ulogic;
  34         ext_rst_n : in  std_ulogic;
  35
  36         -- UART0 signals:
  37         uart_main_tx : out std_ulogic;
  38         uart_main_rx : in  std_ulogic;
  39
  40         -- UART1 signals:
  41         uart_pmod_tx    : out std_ulogic;
  42         uart_pmod_rx    : in std_ulogic;
  43         uart_pmod_cts_n : in std_ulogic;
  44         uart_pmod_rts_n : out std_ulogic;
  45
  46         -- LEDs
  47         led0_b  : out std_ulogic;
  48         led0_g  : out std_ulogic;
  49         led0_r  : out std_ulogic;
  50         led4    : out std_ulogic;
  51         led5    : out std_ulogic;
  52         led6    : out std_ulogic;
  53         led7    : out std_ulogic;
  54
  55         -- SPI
  56         spi_flash_cs_n   : out std_ulogic;
  57         spi_flash_clk    : out std_ulogic;
  58         spi_flash_mosi   : inout std_ulogic;
  59         spi_flash_miso   : inout std_ulogic;
  60         spi_flash_wp_n   : inout std_ulogic;
  61         spi_flash_hold_n : inout std_ulogic;
  62
  63         -- Ethernet
  64         eth_ref_clk      : out std_ulogic;
  65         eth_clocks_tx    : in std_ulogic;
  66         eth_clocks_rx    : in std_ulogic;
  67         eth_rst_n        : out std_ulogic;
  68         eth_mdio         : inout std_ulogic;
  69         eth_mdc          : out std_ulogic;
  70         eth_rx_dv        : in std_ulogic;
  71         eth_rx_er        : in std_ulogic;
  72         eth_rx_data      : in std_ulogic_vector(3 downto 0);
  73         eth_tx_en        : out std_ulogic;
  74         eth_tx_data      : out std_ulogic_vector(3 downto 0);
  75         eth_col          : in std_ulogic;
  76         eth_crs          : in std_ulogic;
  77
  78         -- DRAM wires
  79         ddram_a       : out std_ulogic_vector(13 downto 0);
  80         ddram_ba      : out std_ulogic_vector(2 downto 0);
  81         ddram_ras_n   : out std_ulogic;
  82         ddram_cas_n   : out std_ulogic;
  83         ddram_we_n    : out std_ulogic;
  84         ddram_cs_n    : out std_ulogic;
  85         ddram_dm      : out std_ulogic_vector(1 downto 0);
  86         ddram_dq      : inout std_ulogic_vector(15 downto 0);
  87         ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
  88         ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
  89         ddram_clk_p   : out std_ulogic_vector(0 downto 0);
  90         ddram_clk_n   : out std_ulogic_vector(0 downto 0);
  91         ddram_cke     : out std_ulogic;
  92         ddram_odt     : out std_ulogic;
  93         ddram_reset_n : out std_ulogic
  94         );
  95 end entity toplevel;
  96
  97 architecture behaviour of toplevel is
  98
  99     -- Reset signals:
 100     signal soc_rst : std_ulogic;
 101     signal pll_rst : std_ulogic;
 102
 103     -- Internal clock signals:
 104     signal system_clk        : std_ulogic;
 105     signal system_clk_locked : std_ulogic;
 106     signal eth_clk_locked    : std_ulogic;
 107
 108     -- External IOs from the SoC
 109     signal wb_ext_io_in        : wb_io_master_out;
 110     signal wb_ext_io_out       : wb_io_slave_out;
 111     signal wb_ext_is_dram_csr  : std_ulogic;
 112     signal wb_ext_is_dram_init : std_ulogic;
 113     signal wb_ext_is_eth       : std_ulogic;
 114     signal wb_ext_is_tercel    : std_ulogic;
 115
 116     -- DRAM main data wishbone connection
 117     signal wb_dram_in          : wishbone_master_out;
 118     signal wb_dram_out         : wishbone_slave_out;
 119
 120     -- DRAM control wishbone connection
 121     signal wb_dram_ctrl_out    : wb_io_slave_out := wb_io_slave_out_init;
 122
 123     -- LiteEth connection
 124     signal ext_irq_eth         : std_ulogic;
 125     signal wb_eth_out          : wb_io_slave_out := wb_io_slave_out_init;
 126
 127     -- Control/status
 128     signal core_alt_reset : std_ulogic;
 129
 130     -- Status LED
 131     signal led0_b_pwm : std_ulogic;
 132     signal led0_r_pwm : std_ulogic;
 133     signal led0_g_pwm : std_ulogic;
 134
 135     -- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise
 136     signal pwm_counter  : std_ulogic_vector(8 downto 0);
 137
 138     -- SPI flash
 139     signal spi_sck     : std_ulogic;
 140     signal spi_cs_n    : std_ulogic;
 141     signal spi_sdat_o  : std_ulogic_vector(3 downto 0);
 142     signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
 143     signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
 144
 145     -- SPI main data wishbone connection
 146     signal wb_spiflash_in      : wb_io_master_out;
 147     signal wb_spiflash_out     : wb_io_slave_out;
 148
 149     -- Fixup various memory sizes based on generics
 150     function get_bram_size return natural is
 151     begin
 152         if USE_LITEDRAM and NO_BRAM then
 153             return 0;
 154         else
 155             return MEMORY_SIZE;
 156         end if;
 157     end function;
 158
 159     function get_payload_size return natural is
 160     begin
 161         if USE_LITEDRAM and NO_BRAM then
 162             return MEMORY_SIZE;
 163         else
 164             return 0;
 165         end if;
 166     end function;
 167
 168     constant BRAM_SIZE    : natural := get_bram_size;
 169     constant PAYLOAD_SIZE : natural := get_payload_size;
 170 begin
 171
 172     -- Main SoC
 173     soc0: entity work.soc
 174         generic map(
 175             MEMORY_SIZE        => BRAM_SIZE,
 176             RAM_INIT_FILE      => RAM_INIT_FILE,
 177             SIM                => false,
 178             CLK_FREQ           => CLK_FREQUENCY,
 179             HAS_FPU            => HAS_FPU,
 180             HAS_BTC            => HAS_BTC,
 181             HAS_DRAM           => USE_LITEDRAM,
 182             DRAM_SIZE          => 256 * 1024 * 1024,
 183             DRAM_INIT_SIZE     => PAYLOAD_SIZE,
 184             DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
 185             HAS_SPI_FLASH      => true,
 186             SPI_FLASH_DLINES   => 4,
 187             SPI_FLASH_OFFSET   => SPI_FLASH_OFFSET,
 188             SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
 189             SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
 190             LOG_LENGTH         => LOG_LENGTH,
 191             HAS_LITEETH        => USE_LITEETH,
 192             UART0_IS_16550     => UART_IS_16550,
 193             HAS_UART1          => HAS_UART1
 194             )
 195         port map (
 196             -- System signals
 197             system_clk        => system_clk,
 198             rst               => soc_rst,
 199
 200             -- UART signals
 201             uart0_txd         => uart_main_tx,
 202             uart0_rxd         => uart_main_rx,
 203
 204             -- UART1 signals
 205             uart1_txd         => uart_pmod_tx,
 206             uart1_rxd         => uart_pmod_rx,
 207
 208             -- External interrupts
 209             ext_irq_eth       => ext_irq_eth,
 210
 211             -- DRAM wishbone
 212             wb_dram_in           => wb_dram_in,
 213             wb_dram_out          => wb_dram_out,
 214             wb_ext_io_in         => wb_ext_io_in,
 215             wb_ext_io_out        => wb_ext_io_out,
 216             wb_ext_is_dram_csr   => wb_ext_is_dram_csr,
 217             wb_ext_is_dram_init  => wb_ext_is_dram_init,
 218             wb_ext_is_eth        => wb_ext_is_eth,
 219             wb_ext_is_tercel     => wb_ext_is_tercel,
 220             alt_reset            => core_alt_reset,
 221
 222             -- SPI wishbone
 223             wb_spiflash_in       => wb_spiflash_in,
 224             wb_spiflash_out      => wb_spiflash_out
 225             );
 226
 227     uart_pmod_rts_n <= '0';
 228
 229     -- SPI Flash
 230     --
 231     -- Note: Unlike many other boards, the SPI flash on the Arty has
 232     -- an actual pin to generate the clock and doesn't require to use
 233     -- the STARTUPE2 primitive.
 234     --
 235     spi_flash_cs_n   <= spi_cs_n;
 236     spi_flash_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
 237     spi_flash_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
 238     spi_flash_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
 239     spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
 240     spi_sdat_i(0)    <= spi_flash_mosi;
 241     spi_sdat_i(1)    <= spi_flash_miso;
 242     spi_sdat_i(2)    <= spi_flash_wp_n;
 243     spi_sdat_i(3)    <= spi_flash_hold_n;
 244
 245     spi_sclk_startupe2: if SCLK_STARTUPE2 generate
 246         spi_flash_clk    <= 'Z';
 247
 248         STARTUPE2_INST: STARTUPE2
 249             port map (
 250                 CLK => '0',
 251                 GSR => '0',
 252                 GTS => '0',
 253                 KEYCLEARB => '0',
 254                 PACK => '0',
 255                 USRCCLKO => spi_sck,
 256                 USRCCLKTS => '0',
 257                 USRDONEO => '1',
 258                 USRDONETS => '0'
 259                 );
 260     end generate;
 261
 262     spi_direct_sclk: if not SCLK_STARTUPE2 generate
 263         spi_flash_clk    <= spi_sck;
 264     end generate;
 265
 266     nodram: if not USE_LITEDRAM generate
 267         signal ddram_clk_dummy : std_ulogic;
 268     begin
 269         reset_controller: entity work.soc_reset
 270             generic map(
 271                 RESET_LOW => RESET_LOW
 272                 )
 273             port map(
 274                 ext_clk => ext_clk,
 275                 pll_clk => system_clk,
 276                 pll_locked_in => system_clk_locked and eth_clk_locked,
 277                 ext_rst_in => ext_rst_n,
 278                 pll_rst_out => pll_rst,
 279                 rst_out => soc_rst
 280                 );
 281
 282         clkgen: entity work.clock_generator
 283             generic map(
 284                 CLK_INPUT_HZ => 100000000,
 285                 CLK_OUTPUT_HZ => CLK_FREQUENCY
 286                 )
 287             port map(
 288                 ext_clk => ext_clk,
 289                 pll_rst_in => pll_rst,
 290                 pll_clk_out => system_clk,
 291                 pll_locked_out => system_clk_locked
 292                 );
 293
 294         led0_b_pwm <= '1';
 295         led0_r_pwm <= '1';
 296         led0_g_pwm <= '0';
 297         core_alt_reset <= '0';
 298
 299         -- Vivado barfs on those differential signals if left
 300         -- unconnected. So instanciate a diff. buffer and feed
 301         -- it a constant '0'.
 302         dummy_dram_clk: OBUFDS
 303             port map (
 304                 O => ddram_clk_p,
 305                 OB => ddram_clk_n,
 306                 I => ddram_clk_dummy
 307                 );
 308         ddram_clk_dummy <= '0';
 309
 310     end generate;
 311
 312     has_dram: if USE_LITEDRAM generate
 313         signal dram_init_done  : std_ulogic;
 314         signal dram_init_error : std_ulogic;
 315         signal dram_sys_rst    : std_ulogic;
 316         signal rst_gen_rst     : std_ulogic;
 317     begin
 318
 319         -- Eventually dig out the frequency from the generator
 320         -- but for now, assert it's 100Mhz
 321         assert CLK_FREQUENCY = 100000000;
 322
 323         reset_controller: entity work.soc_reset
 324             generic map(
 325                 RESET_LOW => RESET_LOW,
 326                 PLL_RESET_BITS => 18,
 327                 SOC_RESET_BITS => 1
 328                 )
 329             port map(
 330                 ext_clk => ext_clk,
 331                 pll_clk => system_clk,
 332                 pll_locked_in => eth_clk_locked,
 333                 ext_rst_in => ext_rst_n,
 334                 pll_rst_out => pll_rst,
 335                 rst_out => rst_gen_rst
 336                 );
 337
 338         -- Generate SoC reset
 339         soc_rst_gen: process(system_clk)
 340         begin
 341             if ext_rst_n = '0' then
 342                 soc_rst <= '1';
 343             elsif rising_edge(system_clk) then
 344                 soc_rst <= dram_sys_rst or not eth_clk_locked or not system_clk_locked;
 345             end if;
 346         end process;
 347
 348         dram: entity work.litedram_wrapper
 349             generic map(
 350                 DRAM_ABITS => 24,
 351                 DRAM_ALINES => 14,
 352                 DRAM_DLINES => 16,
 353                 DRAM_CKLINES => 1,
 354                 DRAM_PORT_WIDTH => 128,
 355                 PAYLOAD_FILE => RAM_INIT_FILE,
 356                 PAYLOAD_SIZE => PAYLOAD_SIZE
 357                 )
 358             port map(
 359                 clk_in          => ext_clk,
 360                 rst             => pll_rst,
 361                 system_clk      => system_clk,
 362                 system_reset    => dram_sys_rst,
 363                 core_alt_reset  => core_alt_reset,
 364                 pll_locked      => system_clk_locked,
 365
 366                 wb_in           => wb_dram_in,
 367                 wb_out          => wb_dram_out,
 368                 wb_ctrl_in      => wb_ext_io_in,
 369                 wb_ctrl_out     => wb_dram_ctrl_out,
 370                 wb_ctrl_is_csr  => wb_ext_is_dram_csr,
 371                 wb_ctrl_is_init => wb_ext_is_dram_init,
 372
 373                 init_done       => dram_init_done,
 374                 init_error      => dram_init_error,
 375
 376                 ddram_a         => ddram_a,
 377                 ddram_ba        => ddram_ba,
 378                 ddram_ras_n     => ddram_ras_n,
 379                 ddram_cas_n     => ddram_cas_n,
 380                 ddram_we_n      => ddram_we_n,
 381                 ddram_cs_n      => ddram_cs_n,
 382                 ddram_dm        => ddram_dm,
 383                 ddram_dq        => ddram_dq,
 384                 ddram_dqs_p     => ddram_dqs_p,
 385                 ddram_dqs_n     => ddram_dqs_n,
 386                 ddram_clk_p     => ddram_clk_p,
 387                 ddram_clk_n     => ddram_clk_n,
 388                 ddram_cke       => ddram_cke,
 389                 ddram_odt       => ddram_odt,
 390                 ddram_reset_n   => ddram_reset_n
 391                 );
 392
 393         led0_b_pwm <= not dram_init_done;
 394         led0_r_pwm <= dram_init_error;
 395         led0_g_pwm <= dram_init_done and not dram_init_error;
 396
 397     end generate;
 398
 399     has_liteeth : if USE_LITEETH generate
 400
 401         component liteeth_core port (
 402             sys_clock           : in std_ulogic;
 403             sys_reset           : in std_ulogic;
 404             mii_eth_clocks_tx   : in std_ulogic;
 405             mii_eth_clocks_rx   : in std_ulogic;
 406             mii_eth_rst_n       : out std_ulogic;
 407             mii_eth_mdio        : in std_ulogic;
 408             mii_eth_mdc         : out std_ulogic;
 409             mii_eth_rx_dv       : in std_ulogic;
 410             mii_eth_rx_er       : in std_ulogic;
 411             mii_eth_rx_data     : in std_ulogic_vector(3 downto 0);
 412             mii_eth_tx_en       : out std_ulogic;
 413             mii_eth_tx_data     : out std_ulogic_vector(3 downto 0);
 414             mii_eth_col         : in std_ulogic;
 415             mii_eth_crs         : in std_ulogic;
 416             wishbone_adr        : in std_ulogic_vector(29 downto 0);
 417             wishbone_dat_w      : in std_ulogic_vector(31 downto 0);
 418             wishbone_dat_r      : out std_ulogic_vector(31 downto 0);
 419             wishbone_sel        : in std_ulogic_vector(3 downto 0);
 420             wishbone_cyc        : in std_ulogic;
 421             wishbone_stb        : in std_ulogic;
 422             wishbone_ack        : out std_ulogic;
 423             wishbone_we         : in std_ulogic;
 424             wishbone_cti        : in std_ulogic_vector(2 downto 0);
 425             wishbone_bte        : in std_ulogic_vector(1 downto 0);
 426             wishbone_err        : out std_ulogic;
 427             interrupt           : out std_ulogic
 428             );
 429         end component;
 430
 431         signal wb_eth_cyc     : std_ulogic;
 432         signal wb_eth_adr     : std_ulogic_vector(29 downto 0);
 433
 434         -- Change this to use a PLL instead of a BUFR to generate the 25Mhz
 435         -- reference clock to the PHY.
 436         constant USE_PLL : boolean := false;
 437     begin
 438         eth_use_pll: if USE_PLL generate
 439             signal eth_clk_25     : std_ulogic;
 440             signal eth_clkfb      : std_ulogic;
 441         begin
 442             pll_eth : PLLE2_BASE
 443                 generic map (
 444                     BANDWIDTH          => "OPTIMIZED",
 445                     CLKFBOUT_MULT      => 16,
 446                     CLKIN1_PERIOD      => 10.0,
 447                     CLKOUT0_DIVIDE     => 64,
 448                     DIVCLK_DIVIDE      => 1,
 449                     STARTUP_WAIT       => "FALSE")
 450                 port map (
 451                     CLKOUT0  => eth_clk_25,
 452                     CLKOUT1  => open,
 453                     CLKOUT2  => open,
 454                     CLKOUT3  => open,
 455                     CLKOUT4  => open,
 456                     CLKOUT5  => open,
 457                     CLKFBOUT => eth_clkfb,
 458                     LOCKED   => eth_clk_locked,
 459                     CLKIN1   => ext_clk,
 460                     PWRDWN   => '0',
 461                     RST      => pll_rst,
 462                     CLKFBIN  => eth_clkfb);
 463
 464             eth_clk_buf: BUFG
 465                 port map (
 466                     I => eth_clk_25,
 467                     O => eth_ref_clk
 468                     );
 469         end generate;
 470
 471         eth_use_bufr: if not USE_PLL generate
 472             eth_clk_div: BUFR
 473                 generic map (
 474                     BUFR_DIVIDE => "4"
 475                     )
 476                 port map (
 477                     I => system_clk,
 478                     O => eth_ref_clk,
 479                     CE => '1',
 480                     CLR => '0'
 481                     );
 482             eth_clk_locked <= '1';
 483         end generate;
 484
 485         liteeth :  liteeth_core
 486             port map(
 487                 sys_clock         => system_clk,
 488                 sys_reset         => soc_rst,
 489                 mii_eth_clocks_tx => eth_clocks_tx,
 490                 mii_eth_clocks_rx => eth_clocks_rx,
 491                 mii_eth_rst_n     => eth_rst_n,
 492                 mii_eth_mdio      => eth_mdio,
 493                 mii_eth_mdc       => eth_mdc,
 494                 mii_eth_rx_dv     => eth_rx_dv,
 495                 mii_eth_rx_er     => eth_rx_er,
 496                 mii_eth_rx_data   => eth_rx_data,
 497                 mii_eth_tx_en     => eth_tx_en,
 498                 mii_eth_tx_data   => eth_tx_data,
 499                 mii_eth_col       => eth_col,
 500                 mii_eth_crs       => eth_crs,
 501                 wishbone_adr      => wb_eth_adr,
 502                 wishbone_dat_w    => wb_ext_io_in.dat,
 503                 wishbone_dat_r    => wb_eth_out.dat,
 504                 wishbone_sel      => wb_ext_io_in.sel,
 505                 wishbone_cyc      => wb_eth_cyc,
 506                 wishbone_stb      => wb_ext_io_in.stb,
 507                 wishbone_ack      => wb_eth_out.ack,
 508                 wishbone_we       => wb_ext_io_in.we,
 509                 wishbone_cti      => "000",
 510                 wishbone_bte      => "00",
 511                 wishbone_err      => open,
 512                 interrupt         => ext_irq_eth
 513                 );
 514
 515         -- Gate cyc with "chip select" from soc
 516         wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth;
 517
 518         -- Remove top address bits as liteeth decoder doesn't know about them
 519         wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(16 downto 2);
 520
 521         -- LiteETH isn't pipelined
 522         wb_eth_out.stall <= not wb_eth_out.ack;
 523
 524     end generate;
 525
 526     no_liteeth : if not USE_LITEETH generate
 527         eth_clk_locked <= '1';
 528         ext_irq_eth    <= '0';
 529     end generate;
 530
 531     has_tercel : if USE_TERCEL generate
 532
 533         component tercel_core port (
 534             sys_clk_freq        : in std_ulogic_vector(31 downto 0);
 535
 536             peripheral_clock    : in std_ulogic;
 537             peripheral_reset    : in std_ulogic;
 538
 539             spi_clock           : out std_ulogic;
 540             spi_d_out           : out std_ulogic_vector(3 downto 0);
 541             spi_d_direction     : out std_ulogic_vector(3 downto 0);
 542             spi_d_in            : in std_ulogic_vector(3 downto 0);
 543             spi_ss_n            : out std_ulogic;
 544
 545             wishbone_adr        : in std_ulogic_vector(29 downto 0);
 546             wishbone_dat_w      : in std_ulogic_vector(31 downto 0);
 547             wishbone_dat_r      : out std_ulogic_vector(31 downto 0);
 548             wishbone_sel        : in std_ulogic_vector(3 downto 0);
 549             wishbone_cyc        : in std_ulogic;
 550             wishbone_stb        : in std_ulogic;
 551             wishbone_ack        : out std_ulogic;
 552             wishbone_we         : in std_ulogic;
 553             wishbone_err        : out std_ulogic;
 554
 555             cfg_wishbone_adr    : in std_ulogic_vector(29 downto 0);
 556             cfg_wishbone_dat_w  : in std_ulogic_vector(31 downto 0);
 557             cfg_wishbone_dat_r  : out std_ulogic_vector(31 downto 0);
 558             cfg_wishbone_sel    : in std_ulogic_vector(3 downto 0);
 559             cfg_wishbone_cyc    : in std_ulogic;
 560             cfg_wishbone_stb    : in std_ulogic;
 561             cfg_wishbone_ack    : out std_ulogic;
 562             cfg_wishbone_we     : in std_ulogic;
 563             cfg_wishbone_err    : out std_ulogic
 564             );
 565         end component;
 566
 567         signal wb_tercel_cyc     : std_ulogic;
 568
 569     begin
 570         tercel :  tercel_core
 571             port map(
 572                 sys_clk_freq        => std_logic_vector(to_unsigned(CLK_FREQUENCY, 32)),
 573
 574                 peripheral_clock    => system_clk,
 575                 peripheral_reset    => soc_rst,
 576
 577                 spi_clock           => spi_sck,
 578                 spi_d_out           => spi_sdat_o,
 579                 spi_d_direction     => spi_sdat_oe,
 580                 spi_d_in            => spi_sdat_i,
 581                 spi_ss_n            => spi_cs_n,
 582
 583                 wishbone_adr        => wb_spiflash_in.adr,
 584                 wishbone_dat_w      => wb_spiflash_in.dat,
 585                 wishbone_dat_r      => wb_spiflash_out.dat,
 586                 wishbone_sel        => wb_spiflash_in.sel,
 587                 wishbone_cyc        => wb_spiflash_in.cyc,
 588                 wishbone_stb        => wb_spiflash_in.stb,
 589                 wishbone_ack        => wb_spiflash_out.ack,
 590                 wishbone_we         => wb_spiflash_in.we,
 591                 wishbone_err        => open,
 592
 593                 cfg_wishbone_adr    => wb_ext_io_in.adr,
 594                 cfg_wishbone_dat_w  => wb_ext_io_in.dat,
 595                 cfg_wishbone_dat_r  => wb_tercel_out.dat,
 596                 cfg_wishbone_sel    => wb_ext_io_in.sel,
 597                 cfg_wishbone_cyc    => wb_tercel_cyc,
 598                 cfg_wishbone_stb    => wb_ext_io_in.stb,
 599                 cfg_wishbone_ack    => wb_tercel_out.ack,
 600                 cfg_wishbone_we     => wb_ext_io_in.we,
 601                 cfg_wishbone_err    => open
 602                 );
 603
 604         -- Gate cyc with "chip select" from soc
 605         wb_tercel_cyc <= wb_ext_io_in.cyc and wb_ext_is_tercel;
 606
 607         -- Tercel isn't pipelined
 608         wb_tercel_out.stall <= not wb_tercel_out.ack;
 609
 610     end generate;
 611
 612     -- Mux WB response on the IO bus
 613     wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else
 614                      wb_tercel_out when wb_ext_is_tercel = '1' else
 615                      wb_dram_ctrl_out;
 616
 617     leds_pwm : process(system_clk)
 618     begin
 619         if rising_edge(system_clk) then
 620             pwm_counter <= std_ulogic_vector(signed(pwm_counter) + 1);
 621             if pwm_counter(8 downto 4) = "00000" then
 622                 led0_b <= led0_b_pwm;
 623                 led0_r <= led0_r_pwm;
 624                 led0_g <= led0_g_pwm;
 625             else
 626                 led0_b <= '0';
 627                 led0_r <= '0';
 628                 led0_g <= '0';
 629             end if;
 630         end if;
 631     end process;
 632
 633     led4 <= system_clk_locked;
 634     led5 <= eth_clk_locked;
 635     led6 <= not soc_rst;
 636     led7 <= not spi_flash_cs_n;
 637
 638 end architecture behaviour;