2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use unisim.vcomponents.all;
9 use work.wishbone_types.all;
13 MEMORY_SIZE : integer := 16384;
14 RAM_INIT_FILE : string := "firmware.hex";
15 RESET_LOW : boolean := true;
16 CLK_FREQUENCY : positive := 100000000;
17 HAS_FPU : boolean := true;
18 HAS_BTC : boolean := true;
19 USE_LITEDRAM : boolean := false;
20 NO_BRAM : boolean := false;
21 DISABLE_FLATTEN_CORE : boolean := false;
22 SCLK_STARTUPE2 : boolean := false;
23 SPI_FLASH_OFFSET : integer := 4194304;
24 SPI_FLASH_DEF_CKDV : natural := 1;
25 SPI_FLASH_DEF_QUAD : boolean := true;
26 LOG_LENGTH : natural := 512;
27 USE_LITEETH : boolean := false;
28 UART_IS_16550 : boolean := false;
29 HAS_UART1 : boolean := true
32 ext_clk : in std_ulogic;
33 ext_rst_n : in std_ulogic;
36 uart_main_tx : out std_ulogic;
37 uart_main_rx : in std_ulogic;
40 uart_pmod_tx : out std_ulogic;
41 uart_pmod_rx : in std_ulogic;
42 uart_pmod_cts_n : in std_ulogic;
43 uart_pmod_rts_n : out std_ulogic;
46 led0_b : out std_ulogic;
47 led0_g : out std_ulogic;
48 led0_r : out std_ulogic;
49 led4 : out std_ulogic;
50 led5 : out std_ulogic;
51 led6 : out std_ulogic;
52 led7 : out std_ulogic;
55 spi_flash_cs_n : out std_ulogic;
56 spi_flash_clk : out std_ulogic;
57 spi_flash_mosi : inout std_ulogic;
58 spi_flash_miso : inout std_ulogic;
59 spi_flash_wp_n : inout std_ulogic;
60 spi_flash_hold_n : inout std_ulogic;
63 eth_ref_clk : out std_ulogic;
64 eth_clocks_tx : in std_ulogic;
65 eth_clocks_rx : in std_ulogic;
66 eth_rst_n : out std_ulogic;
67 eth_mdio : inout std_ulogic;
68 eth_mdc : out std_ulogic;
69 eth_rx_dv : in std_ulogic;
70 eth_rx_er : in std_ulogic;
71 eth_rx_data : in std_ulogic_vector(3 downto 0);
72 eth_tx_en : out std_ulogic;
73 eth_tx_data : out std_ulogic_vector(3 downto 0);
74 eth_col : in std_ulogic;
75 eth_crs : in std_ulogic;
78 ddram_a : out std_ulogic_vector(13 downto 0);
79 ddram_ba : out std_ulogic_vector(2 downto 0);
80 ddram_ras_n : out std_ulogic;
81 ddram_cas_n : out std_ulogic;
82 ddram_we_n : out std_ulogic;
83 ddram_cs_n : out std_ulogic;
84 ddram_dm : out std_ulogic_vector(1 downto 0);
85 ddram_dq : inout std_ulogic_vector(15 downto 0);
86 ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
87 ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
88 ddram_clk_p : out std_ulogic;
89 ddram_clk_n : out std_ulogic;
90 ddram_cke : out std_ulogic;
91 ddram_odt : out std_ulogic;
92 ddram_reset_n : out std_ulogic
96 architecture behaviour of toplevel is
99 signal soc_rst : std_ulogic;
100 signal pll_rst : std_ulogic;
102 -- Internal clock signals:
103 signal system_clk : std_ulogic;
104 signal system_clk_locked : std_ulogic;
105 signal eth_clk_locked : std_ulogic;
107 -- External IOs from the SoC
108 signal wb_ext_io_in : wb_io_master_out;
109 signal wb_ext_io_out : wb_io_slave_out;
110 signal wb_ext_is_dram_csr : std_ulogic;
111 signal wb_ext_is_dram_init : std_ulogic;
112 signal wb_ext_is_eth : std_ulogic;
114 -- DRAM main data wishbone connection
115 signal wb_dram_in : wishbone_master_out;
116 signal wb_dram_out : wishbone_slave_out;
118 -- DRAM control wishbone connection
119 signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init;
121 -- LiteEth connection
122 signal ext_irq_eth : std_ulogic;
123 signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init;
126 signal core_alt_reset : std_ulogic;
129 signal led0_b_pwm : std_ulogic;
130 signal led0_r_pwm : std_ulogic;
131 signal led0_g_pwm : std_ulogic;
133 -- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise
134 signal pwm_counter : std_ulogic_vector(8 downto 0);
137 signal spi_sck : std_ulogic;
138 signal spi_cs_n : std_ulogic;
139 signal spi_sdat_o : std_ulogic_vector(3 downto 0);
140 signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
141 signal spi_sdat_i : std_ulogic_vector(3 downto 0);
143 -- Fixup various memory sizes based on generics
144 function get_bram_size return natural is
146 if USE_LITEDRAM and NO_BRAM then
153 function get_payload_size return natural is
155 if USE_LITEDRAM and NO_BRAM then
162 constant BRAM_SIZE : natural := get_bram_size;
163 constant PAYLOAD_SIZE : natural := get_payload_size;
167 soc0: entity work.soc
169 MEMORY_SIZE => BRAM_SIZE,
170 RAM_INIT_FILE => RAM_INIT_FILE,
172 CLK_FREQ => CLK_FREQUENCY,
175 HAS_DRAM => USE_LITEDRAM,
176 DRAM_SIZE => 256 * 1024 * 1024,
177 DRAM_INIT_SIZE => PAYLOAD_SIZE,
178 DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
179 HAS_SPI_FLASH => true,
180 SPI_FLASH_DLINES => 4,
181 SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
182 SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
183 SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
184 LOG_LENGTH => LOG_LENGTH,
185 HAS_LITEETH => USE_LITEETH,
186 UART0_IS_16550 => UART_IS_16550,
187 HAS_UART1 => HAS_UART1
191 system_clk => system_clk,
195 uart0_txd => uart_main_tx,
196 uart0_rxd => uart_main_rx,
199 uart1_txd => uart_pmod_tx,
200 uart1_rxd => uart_pmod_rx,
203 spi_flash_sck => spi_sck,
204 spi_flash_cs_n => spi_cs_n,
205 spi_flash_sdat_o => spi_sdat_o,
206 spi_flash_sdat_oe => spi_sdat_oe,
207 spi_flash_sdat_i => spi_sdat_i,
209 -- External interrupts
210 ext_irq_eth => ext_irq_eth,
213 wb_dram_in => wb_dram_in,
214 wb_dram_out => wb_dram_out,
215 wb_ext_io_in => wb_ext_io_in,
216 wb_ext_io_out => wb_ext_io_out,
217 wb_ext_is_dram_csr => wb_ext_is_dram_csr,
218 wb_ext_is_dram_init => wb_ext_is_dram_init,
219 wb_ext_is_eth => wb_ext_is_eth,
220 alt_reset => core_alt_reset
223 uart_pmod_rts_n <= '0';
227 -- Note: Unlike many other boards, the SPI flash on the Arty has
228 -- an actual pin to generate the clock and doesn't require to use
229 -- the STARTUPE2 primitive.
231 spi_flash_cs_n <= spi_cs_n;
232 spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
233 spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
234 spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
235 spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
236 spi_sdat_i(0) <= spi_flash_mosi;
237 spi_sdat_i(1) <= spi_flash_miso;
238 spi_sdat_i(2) <= spi_flash_wp_n;
239 spi_sdat_i(3) <= spi_flash_hold_n;
241 spi_sclk_startupe2: if SCLK_STARTUPE2 generate
242 spi_flash_clk <= 'Z';
244 STARTUPE2_INST: STARTUPE2
258 spi_direct_sclk: if not SCLK_STARTUPE2 generate
259 spi_flash_clk <= spi_sck;
262 nodram: if not USE_LITEDRAM generate
263 signal ddram_clk_dummy : std_ulogic;
265 reset_controller: entity work.soc_reset
267 RESET_LOW => RESET_LOW
271 pll_clk => system_clk,
272 pll_locked_in => system_clk_locked and eth_clk_locked,
273 ext_rst_in => ext_rst_n,
274 pll_rst_out => pll_rst,
278 clkgen: entity work.clock_generator
280 CLK_INPUT_HZ => 100000000,
281 CLK_OUTPUT_HZ => CLK_FREQUENCY
285 pll_rst_in => pll_rst,
286 pll_clk_out => system_clk,
287 pll_locked_out => system_clk_locked
293 core_alt_reset <= '0';
295 -- Vivado barfs on those differential signals if left
296 -- unconnected. So instanciate a diff. buffer and feed
297 -- it a constant '0'.
298 dummy_dram_clk: OBUFDS
304 ddram_clk_dummy <= '0';
308 has_dram: if USE_LITEDRAM generate
309 signal dram_init_done : std_ulogic;
310 signal dram_init_error : std_ulogic;
311 signal dram_sys_rst : std_ulogic;
312 signal rst_gen_rst : std_ulogic;
315 -- Eventually dig out the frequency from the generator
316 -- but for now, assert it's 100Mhz
317 assert CLK_FREQUENCY = 100000000;
319 reset_controller: entity work.soc_reset
321 RESET_LOW => RESET_LOW,
322 PLL_RESET_BITS => 18,
327 pll_clk => system_clk,
328 pll_locked_in => eth_clk_locked,
329 ext_rst_in => ext_rst_n,
330 pll_rst_out => pll_rst,
331 rst_out => rst_gen_rst
334 -- Generate SoC reset
335 soc_rst_gen: process(system_clk)
337 if ext_rst_n = '0' then
339 elsif rising_edge(system_clk) then
340 soc_rst <= dram_sys_rst or not eth_clk_locked or not system_clk_locked;
344 dram: entity work.litedram_wrapper
349 DRAM_PORT_WIDTH => 128,
350 PAYLOAD_FILE => RAM_INIT_FILE,
351 PAYLOAD_SIZE => PAYLOAD_SIZE
356 system_clk => system_clk,
357 system_reset => dram_sys_rst,
358 core_alt_reset => core_alt_reset,
359 pll_locked => system_clk_locked,
362 wb_out => wb_dram_out,
363 wb_ctrl_in => wb_ext_io_in,
364 wb_ctrl_out => wb_dram_ctrl_out,
365 wb_ctrl_is_csr => wb_ext_is_dram_csr,
366 wb_ctrl_is_init => wb_ext_is_dram_init,
368 init_done => dram_init_done,
369 init_error => dram_init_error,
372 ddram_ba => ddram_ba,
373 ddram_ras_n => ddram_ras_n,
374 ddram_cas_n => ddram_cas_n,
375 ddram_we_n => ddram_we_n,
376 ddram_cs_n => ddram_cs_n,
377 ddram_dm => ddram_dm,
378 ddram_dq => ddram_dq,
379 ddram_dqs_p => ddram_dqs_p,
380 ddram_dqs_n => ddram_dqs_n,
381 ddram_clk_p => ddram_clk_p,
382 ddram_clk_n => ddram_clk_n,
383 ddram_cke => ddram_cke,
384 ddram_odt => ddram_odt,
385 ddram_reset_n => ddram_reset_n
388 led0_b_pwm <= not dram_init_done;
389 led0_r_pwm <= dram_init_error;
390 led0_g_pwm <= dram_init_done and not dram_init_error;
394 has_liteeth : if USE_LITEETH generate
396 component liteeth_core port (
397 sys_clock : in std_ulogic;
398 sys_reset : in std_ulogic;
399 mii_eth_clocks_tx : in std_ulogic;
400 mii_eth_clocks_rx : in std_ulogic;
401 mii_eth_rst_n : out std_ulogic;
402 mii_eth_mdio : in std_ulogic;
403 mii_eth_mdc : out std_ulogic;
404 mii_eth_rx_dv : in std_ulogic;
405 mii_eth_rx_er : in std_ulogic;
406 mii_eth_rx_data : in std_ulogic_vector(3 downto 0);
407 mii_eth_tx_en : out std_ulogic;
408 mii_eth_tx_data : out std_ulogic_vector(3 downto 0);
409 mii_eth_col : in std_ulogic;
410 mii_eth_crs : in std_ulogic;
411 wishbone_adr : in std_ulogic_vector(29 downto 0);
412 wishbone_dat_w : in std_ulogic_vector(31 downto 0);
413 wishbone_dat_r : out std_ulogic_vector(31 downto 0);
414 wishbone_sel : in std_ulogic_vector(3 downto 0);
415 wishbone_cyc : in std_ulogic;
416 wishbone_stb : in std_ulogic;
417 wishbone_ack : out std_ulogic;
418 wishbone_we : in std_ulogic;
419 wishbone_cti : in std_ulogic_vector(2 downto 0);
420 wishbone_bte : in std_ulogic_vector(1 downto 0);
421 wishbone_err : out std_ulogic;
422 interrupt : out std_ulogic
426 signal wb_eth_cyc : std_ulogic;
427 signal wb_eth_adr : std_ulogic_vector(29 downto 0);
429 -- Change this to use a PLL instead of a BUFR to generate the 25Mhz
430 -- reference clock to the PHY.
431 constant USE_PLL : boolean := false;
433 eth_use_pll: if USE_PLL generate
434 signal eth_clk_25 : std_ulogic;
435 signal eth_clkfb : std_ulogic;
439 BANDWIDTH => "OPTIMIZED",
441 CLKIN1_PERIOD => 10.0,
442 CLKOUT0_DIVIDE => 64,
444 STARTUP_WAIT => "FALSE")
446 CLKOUT0 => eth_clk_25,
452 CLKFBOUT => eth_clkfb,
453 LOCKED => eth_clk_locked,
457 CLKFBIN => eth_clkfb);
466 eth_use_bufr: if not USE_PLL generate
477 eth_clk_locked <= '1';
480 liteeth : liteeth_core
482 sys_clock => system_clk,
483 sys_reset => soc_rst,
484 mii_eth_clocks_tx => eth_clocks_tx,
485 mii_eth_clocks_rx => eth_clocks_rx,
486 mii_eth_rst_n => eth_rst_n,
487 mii_eth_mdio => eth_mdio,
488 mii_eth_mdc => eth_mdc,
489 mii_eth_rx_dv => eth_rx_dv,
490 mii_eth_rx_er => eth_rx_er,
491 mii_eth_rx_data => eth_rx_data,
492 mii_eth_tx_en => eth_tx_en,
493 mii_eth_tx_data => eth_tx_data,
494 mii_eth_col => eth_col,
495 mii_eth_crs => eth_crs,
496 wishbone_adr => wb_eth_adr,
497 wishbone_dat_w => wb_ext_io_in.dat,
498 wishbone_dat_r => wb_eth_out.dat,
499 wishbone_sel => wb_ext_io_in.sel,
500 wishbone_cyc => wb_eth_cyc,
501 wishbone_stb => wb_ext_io_in.stb,
502 wishbone_ack => wb_eth_out.ack,
503 wishbone_we => wb_ext_io_in.we,
504 wishbone_cti => "000",
505 wishbone_bte => "00",
506 wishbone_err => open,
507 interrupt => ext_irq_eth
510 -- Gate cyc with "chip select" from soc
511 wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth;
513 -- Remove top address bits as liteeth decoder doesn't know about them
514 wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(16 downto 2);
516 -- LiteETH isn't pipelined
517 wb_eth_out.stall <= not wb_eth_out.ack;
521 no_liteeth : if not USE_LITEETH generate
522 eth_clk_locked <= '1';
526 -- Mux WB response on the IO bus
527 wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else wb_dram_ctrl_out;
529 leds_pwm : process(system_clk)
531 if rising_edge(system_clk) then
532 pwm_counter <= std_ulogic_vector(signed(pwm_counter) + 1);
533 if pwm_counter(8 downto 4) = "00000" then
534 led0_b <= led0_b_pwm;
535 led0_r <= led0_r_pwm;
536 led0_g <= led0_g_pwm;
545 led4 <= system_clk_locked;
546 led5 <= eth_clk_locked;
548 led7 <= not spi_flash_cs_n;
550 end architecture behaviour;