fpga/top-generic.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.wishbone_types.all;
   6
   7 entity toplevel is
   8     generic (
   9         MEMORY_SIZE   : positive := (384*1024);
  10         RAM_INIT_FILE : string   := "firmware.hex";
  11         RESET_LOW     : boolean  := true;
  12         CLK_INPUT     : positive := 100000000;
  13         CLK_FREQUENCY : positive := 100000000;
  14         HAS_FPU       : boolean  := true;
  15         HAS_BTC       : boolean  := false;
  16         LOG_LENGTH    : natural := 512;
  17         DISABLE_FLATTEN_CORE : boolean := false;
  18         UART_IS_16550 : boolean  := true
  19         );
  20     port(
  21         ext_clk   : in  std_ulogic;
  22         ext_rst   : in  std_ulogic;
  23
  24         -- UART0 signals:
  25         uart0_txd : out std_ulogic;
  26         uart0_rxd : in  std_ulogic
  27         );
  28 end entity toplevel;
  29
  30 architecture behaviour of toplevel is
  31
  32     -- Reset signals:
  33     signal soc_rst : std_ulogic;
  34     signal pll_rst : std_ulogic;
  35
  36     -- Internal clock signals:
  37     signal system_clk : std_ulogic;
  38     signal system_clk_locked : std_ulogic;
  39
  40 begin
  41
  42     reset_controller: entity work.soc_reset
  43         generic map(
  44             RESET_LOW => RESET_LOW
  45             )
  46         port map(
  47             ext_clk => ext_clk,
  48             pll_clk => system_clk,
  49             pll_locked_in => system_clk_locked,
  50             ext_rst_in => ext_rst,
  51             pll_rst_out => pll_rst,
  52             rst_out => soc_rst
  53             );
  54
  55     clkgen: entity work.clock_generator
  56         generic map(
  57             CLK_INPUT_HZ => CLK_INPUT,
  58             CLK_OUTPUT_HZ => CLK_FREQUENCY
  59             )
  60         port map(
  61             ext_clk => ext_clk,
  62             pll_rst_in => pll_rst,
  63             pll_clk_out => system_clk,
  64             pll_locked_out => system_clk_locked
  65             );
  66
  67     -- Main SoC
  68     soc0: entity work.soc
  69         generic map(
  70             MEMORY_SIZE   => MEMORY_SIZE,
  71             RAM_INIT_FILE => RAM_INIT_FILE,
  72             SIM           => false,
  73             CLK_FREQ      => CLK_FREQUENCY,
  74             HAS_FPU       => HAS_FPU,
  75             HAS_BTC       => HAS_BTC,
  76             LOG_LENGTH    => LOG_LENGTH,
  77             DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
  78             UART0_IS_16550     => UART_IS_16550
  79             )
  80         port map (
  81             system_clk        => system_clk,
  82             rst               => soc_rst,
  83             uart0_txd         => uart0_txd,
  84             uart0_rxd         => uart0_rxd
  85             );
  86
  87 end architecture behaviour;