1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 enum { vsz_none
, vsz_set
, vsz_reset
} vsz
; /* vector size control */
135 i386_cpu_flags enable
; /* cpu feature enable flags */
136 i386_cpu_flags disable
; /* cpu feature disable flags */
140 static void update_code_flag (int, int);
141 static void s_insn (int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
151 static void pe_directive_secidx (int);
153 static void signed_cons (int);
154 static char *output_invalid (int c
);
155 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
157 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
159 static int i386_att_operand (char *);
160 static int i386_intel_operand (char *, int);
161 static int i386_intel_simplify (expressionS
*);
162 static int i386_intel_parse_name (const char *, expressionS
*);
163 static const reg_entry
*parse_register (const char *, char **);
164 static const char *parse_insn (const char *, char *, bool);
165 static char *parse_operands (char *, const char *);
166 static void swap_operands (void);
167 static void swap_2_operands (unsigned int, unsigned int);
168 static enum i386_flag_code
i386_addressing_mode (void);
169 static void optimize_imm (void);
170 static bool optimize_disp (const insn_template
*t
);
171 static const insn_template
*match_template (char);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const reg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
190 /* GNU_PROPERTY_X86_ISA_1_USED. */
191 static unsigned int x86_isa_1_used
;
192 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
193 static unsigned int x86_feature_2_used
;
194 /* Generate x86 used ISA and feature properties. */
195 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
198 static const char *default_arch
= DEFAULT_ARCH
;
200 /* parse_register() returns this when a register alias cannot be used. */
201 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
202 { Dw2Inval
, Dw2Inval
} };
204 static const reg_entry
*reg_eax
;
205 static const reg_entry
*reg_ds
;
206 static const reg_entry
*reg_es
;
207 static const reg_entry
*reg_ss
;
208 static const reg_entry
*reg_st0
;
209 static const reg_entry
*reg_k0
;
214 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
215 unsigned char bytes
[4];
217 /* Destination or source register specifier. */
218 const reg_entry
*register_specifier
;
221 /* 'md_assemble ()' gathers together information and puts it into a
228 const reg_entry
*regs
;
233 no_error
, /* Must be first. */
234 operand_size_mismatch
,
235 operand_type_mismatch
,
236 register_type_mismatch
,
237 number_of_operands_mismatch
,
238 invalid_instruction_suffix
,
240 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 invalid_dest_and_src_register_set
,
250 unsupported_vector_index_register
,
251 unsupported_broadcast
,
254 mask_not_on_destination
,
257 invalid_register_operand
,
263 /* TM holds the template for the insn were currently assembling. */
266 /* SUFFIX holds the instruction size suffix for byte, word, dword
267 or qword, if given. */
270 /* OPCODE_LENGTH holds the number of base opcode bytes. */
271 unsigned char opcode_length
;
273 /* OPERANDS gives the number of given operands. */
274 unsigned int operands
;
276 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
277 of given register, displacement, memory operands and immediate
279 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
281 /* TYPES [i] is the type (see above #defines) which tells us how to
282 use OP[i] for the corresponding operand. */
283 i386_operand_type types
[MAX_OPERANDS
];
285 /* Displacement expression, immediate expression, or register for each
287 union i386_op op
[MAX_OPERANDS
];
289 /* Flags for operands. */
290 unsigned int flags
[MAX_OPERANDS
];
291 #define Operand_PCrel 1
292 #define Operand_Mem 2
293 #define Operand_Signed 4 /* .insn only */
295 /* Relocation type for operand */
296 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
298 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
299 the base index byte below. */
300 const reg_entry
*base_reg
;
301 const reg_entry
*index_reg
;
302 unsigned int log2_scale_factor
;
304 /* SEG gives the seg_entries of this insn. They are zero unless
305 explicit segment overrides are given. */
306 const reg_entry
*seg
[2];
308 /* PREFIX holds all the given prefix opcodes (usually null).
309 PREFIXES is the number of prefix opcodes. */
310 unsigned int prefixes
;
311 unsigned char prefix
[MAX_PREFIXES
];
313 /* .insn allows for reserved opcode spaces. */
314 unsigned char insn_opcode_space
;
316 /* .insn also allows (requires) specifying immediate size. */
317 unsigned char imm_bits
[MAX_OPERANDS
];
319 /* Register is in low 3 bits of opcode. */
322 /* The operand to a branch insn indicates an absolute branch. */
325 /* The operand to a branch insn indicates a far branch. */
328 /* There is a memory operand of (%dx) which should be only used
329 with input/output instructions. */
330 bool input_output_operand
;
332 /* Extended states. */
340 xstate_ymm
= 1 << 2 | xstate_xmm
,
342 xstate_zmm
= 1 << 3 | xstate_ymm
,
345 /* Use MASK state. */
349 /* Has GOTPC or TLS relocation. */
350 bool has_gotpc_tls_reloc
;
352 /* RM and SIB are the modrm byte and the sib byte where the
353 addressing modes of this insn are encoded. */
360 /* Masking attributes.
362 The struct describes masking, applied to OPERAND in the instruction.
363 REG is a pointer to the corresponding mask register. ZEROING tells
364 whether merging or zeroing mask is used. */
365 struct Mask_Operation
367 const reg_entry
*reg
;
368 unsigned int zeroing
;
369 /* The operand where this operation is associated. */
370 unsigned int operand
;
373 /* Rounding control and SAE attributes. */
385 /* In Intel syntax the operand modifier form is supposed to be used, but
386 we continue to accept the immediate forms as well. */
390 /* Broadcasting attributes.
392 The struct describes broadcasting, applied to OPERAND. TYPE is
393 expresses the broadcast factor. */
394 struct Broadcast_Operation
396 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
399 /* Index of broadcasted operand. */
400 unsigned int operand
;
402 /* Number of bytes to broadcast. */
406 /* Compressed disp8*N attribute. */
407 unsigned int memshift
;
409 /* Prefer load or store in encoding. */
412 dir_encoding_default
= 0,
418 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
421 disp_encoding_default
= 0,
427 /* Prefer the REX byte in encoding. */
430 /* Disable instruction size optimization. */
433 /* How to encode vector instructions. */
436 vex_encoding_default
= 0,
440 vex_encoding_evex512
,
445 const char *rep_prefix
;
448 const char *hle_prefix
;
450 /* Have BND prefix. */
451 const char *bnd_prefix
;
453 /* Have NOTRACK prefix. */
454 const char *notrack_prefix
;
457 enum i386_error error
;
460 typedef struct _i386_insn i386_insn
;
462 /* Link RC type with corresponding string, that'll be looked for in
471 static const struct RC_name RC_NamesTable
[] =
473 { rne
, STRING_COMMA_LEN ("rn-sae") },
474 { rd
, STRING_COMMA_LEN ("rd-sae") },
475 { ru
, STRING_COMMA_LEN ("ru-sae") },
476 { rz
, STRING_COMMA_LEN ("rz-sae") },
477 { saeonly
, STRING_COMMA_LEN ("sae") },
480 /* To be indexed by segment register number. */
481 static const unsigned char i386_seg_prefixes
[] = {
490 /* List of chars besides those in app.c:symbol_chars that can start an
491 operand. Used to prevent the scrubber eating vital white-space. */
492 const char extra_symbol_chars
[] = "*%-([{}"
501 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
502 && !defined (TE_GNU) \
503 && !defined (TE_LINUX) \
504 && !defined (TE_Haiku) \
505 && !defined (TE_FreeBSD) \
506 && !defined (TE_DragonFly) \
507 && !defined (TE_NetBSD))
508 /* This array holds the chars that always start a comment. If the
509 pre-processor is disabled, these aren't very useful. The option
510 --divide will remove '/' from this list. */
511 const char *i386_comment_chars
= "#/";
512 #define SVR4_COMMENT_CHARS 1
513 #define PREFIX_SEPARATOR '\\'
516 const char *i386_comment_chars
= "#";
517 #define PREFIX_SEPARATOR '/'
520 /* This array holds the chars that only start a comment at the beginning of
521 a line. If the line seems to have the form '# 123 filename'
522 .line and .file directives will appear in the pre-processed output.
523 Note that input_file.c hand checks for '#' at the beginning of the
524 first line of the input file. This is because the compiler outputs
525 #NO_APP at the beginning of its output.
526 Also note that comments started like this one will always work if
527 '/' isn't otherwise defined. */
528 const char line_comment_chars
[] = "#/";
530 const char line_separator_chars
[] = ";";
532 /* Chars that can be used to separate mant from exp in floating point
534 const char EXP_CHARS
[] = "eE";
536 /* Chars that mean this number is a floating point constant
539 const char FLT_CHARS
[] = "fFdDxXhHbB";
541 /* Tables for lexical analysis. */
542 static char mnemonic_chars
[256];
543 static char register_chars
[256];
544 static char operand_chars
[256];
546 /* Lexical macros. */
547 #define is_operand_char(x) (operand_chars[(unsigned char) x])
548 #define is_register_char(x) (register_chars[(unsigned char) x])
549 #define is_space_char(x) ((x) == ' ')
551 /* All non-digit non-letter characters that may occur in an operand and
552 which aren't already in extra_symbol_chars[]. */
553 static const char operand_special_chars
[] = "$+,)._~/<>|&^!=:@]";
555 /* md_assemble() always leaves the strings it's passed unaltered. To
556 effect this we maintain a stack of saved characters that we've smashed
557 with '\0's (indicating end of strings for various sub-fields of the
558 assembler instruction). */
559 static char save_stack
[32];
560 static char *save_stack_p
;
561 #define END_STRING_AND_SAVE(s) \
562 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
563 #define RESTORE_END_STRING(s) \
564 do { *(s) = *--save_stack_p; } while (0)
566 /* The instruction we're assembling. */
569 /* Possible templates for current insn. */
570 static const templates
*current_templates
;
572 /* Per instruction expressionS buffers: max displacements & immediates. */
573 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
574 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
576 /* Current operand we are working on. */
577 static int this_operand
= -1;
579 /* Are we processing a .insn directive? */
580 #define dot_insn() (i.tm.mnem_off == MN__insn)
582 enum i386_flag_code i386_flag_code
;
583 #define flag_code i386_flag_code /* Permit to continue using original name. */
584 static unsigned int object_64bit
;
585 static unsigned int disallow_64bit_reloc
;
586 static int use_rela_relocations
= 0;
587 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
588 static const char *tls_get_addr
;
590 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
591 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
592 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
594 /* The ELF ABI to use. */
602 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
605 #if defined (TE_PE) || defined (TE_PEP)
606 /* Use big object file format. */
607 static int use_big_obj
= 0;
610 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
611 /* 1 if generating code for a shared library. */
612 static int shared
= 0;
614 unsigned int x86_sframe_cfa_sp_reg
;
615 /* The other CFA base register for SFrame stack trace info. */
616 unsigned int x86_sframe_cfa_fp_reg
;
617 unsigned int x86_sframe_cfa_ra_reg
;
621 /* 1 for intel syntax,
623 static int intel_syntax
= 0;
625 static enum x86_64_isa
627 amd64
= 1, /* AMD64 ISA. */
628 intel64
/* Intel64 ISA. */
631 /* 1 for intel mnemonic,
632 0 if att mnemonic. */
633 static int intel_mnemonic
= !SYSV386_COMPAT
;
635 /* 1 if pseudo registers are permitted. */
636 static int allow_pseudo_reg
= 0;
638 /* 1 if register prefix % not required. */
639 static int allow_naked_reg
= 0;
641 /* 1 if the assembler should add BND prefix for all control-transferring
642 instructions supporting it, even if this prefix wasn't specified
644 static int add_bnd_prefix
= 0;
646 /* 1 if pseudo index register, eiz/riz, is allowed . */
647 static int allow_index_reg
= 0;
649 /* 1 if the assembler should ignore LOCK prefix, even if it was
650 specified explicitly. */
651 static int omit_lock_prefix
= 0;
653 /* 1 if the assembler should encode lfence, mfence, and sfence as
654 "lock addl $0, (%{re}sp)". */
655 static int avoid_fence
= 0;
657 /* 1 if lfence should be inserted after every load. */
658 static int lfence_after_load
= 0;
660 /* Non-zero if lfence should be inserted before indirect branch. */
661 static enum lfence_before_indirect_branch_kind
663 lfence_branch_none
= 0,
664 lfence_branch_register
,
665 lfence_branch_memory
,
668 lfence_before_indirect_branch
;
670 /* Non-zero if lfence should be inserted before ret. */
671 static enum lfence_before_ret_kind
673 lfence_before_ret_none
= 0,
674 lfence_before_ret_not
,
675 lfence_before_ret_or
,
676 lfence_before_ret_shl
680 /* Types of previous instruction is .byte or prefix. */
695 /* 1 if the assembler should generate relax relocations. */
697 static int generate_relax_relocations
698 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
700 static enum check_kind
706 sse_check
, operand_check
= check_warning
;
708 /* Non-zero if branches should be aligned within power of 2 boundary. */
709 static int align_branch_power
= 0;
711 /* Types of branches to align. */
712 enum align_branch_kind
714 align_branch_none
= 0,
715 align_branch_jcc
= 1,
716 align_branch_fused
= 2,
717 align_branch_jmp
= 3,
718 align_branch_call
= 4,
719 align_branch_indirect
= 5,
723 /* Type bits of branches to align. */
724 enum align_branch_bit
726 align_branch_jcc_bit
= 1 << align_branch_jcc
,
727 align_branch_fused_bit
= 1 << align_branch_fused
,
728 align_branch_jmp_bit
= 1 << align_branch_jmp
,
729 align_branch_call_bit
= 1 << align_branch_call
,
730 align_branch_indirect_bit
= 1 << align_branch_indirect
,
731 align_branch_ret_bit
= 1 << align_branch_ret
734 static unsigned int align_branch
= (align_branch_jcc_bit
735 | align_branch_fused_bit
736 | align_branch_jmp_bit
);
738 /* Types of condition jump used by macro-fusion. */
741 mf_jcc_jo
= 0, /* base opcode 0x70 */
742 mf_jcc_jc
, /* base opcode 0x72 */
743 mf_jcc_je
, /* base opcode 0x74 */
744 mf_jcc_jna
, /* base opcode 0x76 */
745 mf_jcc_js
, /* base opcode 0x78 */
746 mf_jcc_jp
, /* base opcode 0x7a */
747 mf_jcc_jl
, /* base opcode 0x7c */
748 mf_jcc_jle
, /* base opcode 0x7e */
751 /* Types of compare flag-modifying insntructions used by macro-fusion. */
754 mf_cmp_test_and
, /* test/cmp */
755 mf_cmp_alu_cmp
, /* add/sub/cmp */
756 mf_cmp_incdec
/* inc/dec */
759 /* The maximum padding size for fused jcc. CMP like instruction can
760 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
762 #define MAX_FUSED_JCC_PADDING_SIZE 20
764 /* The maximum number of prefixes added for an instruction. */
765 static unsigned int align_branch_prefix_size
= 5;
768 1. Clear the REX_W bit with register operand if possible.
769 2. Above plus use 128bit vector instruction to clear the full vector
772 static int optimize
= 0;
775 1. Clear the REX_W bit with register operand if possible.
776 2. Above plus use 128bit vector instruction to clear the full vector
778 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
781 static int optimize_for_space
= 0;
783 /* Register prefix used for error message. */
784 static const char *register_prefix
= "%";
786 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
787 leave, push, and pop instructions so that gcc has the same stack
788 frame as in 32 bit mode. */
789 static char stackop_size
= '\0';
791 /* Non-zero to optimize code alignment. */
792 int optimize_align_code
= 1;
794 /* Non-zero to quieten some warnings. */
795 static int quiet_warnings
= 0;
797 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
798 static bool pre_386_16bit_warned
;
801 static const char *cpu_arch_name
= NULL
;
802 static char *cpu_sub_arch_name
= NULL
;
804 /* CPU feature flags. */
805 i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
807 /* ISA extensions available in 64-bit mode only. */
808 static const i386_cpu_flags cpu_64_flags
= CPU_ANY_64_FLAGS
;
810 /* If we have selected a cpu we are generating instructions for. */
811 static int cpu_arch_tune_set
= 0;
813 /* Cpu we are generating instructions for. */
814 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
816 /* CPU instruction set architecture used. */
817 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
819 /* CPU feature flags of instruction set architecture used. */
820 i386_cpu_flags cpu_arch_isa_flags
;
822 /* If set, conditional jumps are not automatically promoted to handle
823 larger than a byte offset. */
824 static bool no_cond_jump_promotion
= false;
826 /* This will be set from an expression parser hook if there's any
827 applicable operator involved in an expression. */
830 expr_operator_present
,
834 /* Encode SSE instructions with VEX prefix. */
835 static unsigned int sse2avx
;
837 /* Encode aligned vector move as unaligned vector move. */
838 static unsigned int use_unaligned_vector_move
;
840 /* Maximum permitted vector size. */
841 #define VSZ_DEFAULT VSZ512
842 static unsigned int vector_size
= VSZ_DEFAULT
;
844 /* Encode scalar AVX instructions with specific vector length. */
851 /* Encode VEX WIG instructions with specific vex.w. */
858 /* Encode scalar EVEX LIG instructions with specific vector length. */
866 /* Encode EVEX WIG instructions with specific evex.w. */
873 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
874 static enum rc_type evexrcig
= rne
;
876 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
877 static symbolS
*GOT_symbol
;
879 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
880 unsigned int x86_dwarf2_return_column
;
882 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
883 int x86_cie_data_alignment
;
885 /* Interface to relax_segment.
886 There are 3 major relax states for 386 jump insns because the
887 different types of jumps add different sizes to frags when we're
888 figuring out what sort of jump to choose to reach a given label.
890 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
891 branches which are handled by md_estimate_size_before_relax() and
892 i386_generic_table_relax_frag(). */
895 #define UNCOND_JUMP 0
897 #define COND_JUMP86 2
898 #define BRANCH_PADDING 3
899 #define BRANCH_PREFIX 4
900 #define FUSED_JCC_PADDING 5
905 #define SMALL16 (SMALL | CODE16)
907 #define BIG16 (BIG | CODE16)
911 #define INLINE __inline__
917 #define ENCODE_RELAX_STATE(type, size) \
918 ((relax_substateT) (((type) << 2) | (size)))
919 #define TYPE_FROM_RELAX_STATE(s) \
921 #define DISP_SIZE_FROM_RELAX_STATE(s) \
922 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
924 /* This table is used by relax_frag to promote short jumps to long
925 ones where necessary. SMALL (short) jumps may be promoted to BIG
926 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
927 don't allow a short jump in a 32 bit code segment to be promoted to
928 a 16 bit offset jump because it's slower (requires data size
929 prefix), and doesn't work, unless the destination is in the bottom
930 64k of the code segment (The top 16 bits of eip are zeroed). */
932 const relax_typeS md_relax_table
[] =
935 1) most positive reach of this state,
936 2) most negative reach of this state,
937 3) how many bytes this mode will have in the variable part of the frag
938 4) which index into the table to try if we can't fit into this one. */
940 /* UNCOND_JUMP states. */
941 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
942 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
943 /* dword jmp adds 4 bytes to frag:
944 0 extra opcode bytes, 4 displacement bytes. */
946 /* word jmp adds 2 byte2 to frag:
947 0 extra opcode bytes, 2 displacement bytes. */
950 /* COND_JUMP states. */
951 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
952 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
953 /* dword conditionals adds 5 bytes to frag:
954 1 extra opcode byte, 4 displacement bytes. */
956 /* word conditionals add 3 bytes to frag:
957 1 extra opcode byte, 2 displacement bytes. */
960 /* COND_JUMP86 states. */
961 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
962 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
963 /* dword conditionals adds 5 bytes to frag:
964 1 extra opcode byte, 4 displacement bytes. */
966 /* word conditionals add 4 bytes to frag:
967 1 displacement byte and a 3 byte long branch insn. */
971 #define ARCH(n, t, f, s) \
972 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
974 #define SUBARCH(n, e, d, s) \
975 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
976 CPU_ ## d ## _FLAGS }
977 #define VECARCH(n, e, d, v) \
978 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
979 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
981 static const arch_entry cpu_arch
[] =
983 /* Do not replace the first two entries - i386_target_format() and
984 set_cpu_arch() rely on them being there in this order. */
985 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
986 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
987 ARCH (i8086
, UNKNOWN
, NONE
, false),
988 ARCH (i186
, UNKNOWN
, 186, false),
989 ARCH (i286
, UNKNOWN
, 286, false),
990 ARCH (i386
, I386
, 386, false),
991 ARCH (i486
, I486
, 486, false),
992 ARCH (i586
, PENTIUM
, 586, false),
993 ARCH (pentium
, PENTIUM
, 586, false),
994 ARCH (i686
, I686
, 686, false),
995 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
996 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
997 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
998 ARCH (pentium4
, PENTIUM4
, P4
, false),
999 ARCH (prescott
, NOCONA
, CORE
, false),
1000 ARCH (nocona
, NOCONA
, NOCONA
, false),
1001 ARCH (yonah
, CORE
, CORE
, true),
1002 ARCH (core
, CORE
, CORE
, false),
1003 ARCH (merom
, CORE2
, CORE2
, true),
1004 ARCH (core2
, CORE2
, CORE2
, false),
1005 ARCH (corei7
, COREI7
, COREI7
, false),
1006 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1007 ARCH (k6
, K6
, K6
, false),
1008 ARCH (k6_2
, K6
, K6_2
, false),
1009 ARCH (athlon
, ATHLON
, ATHLON
, false),
1010 ARCH (sledgehammer
, K8
, K8
, true),
1011 ARCH (opteron
, K8
, K8
, false),
1012 ARCH (k8
, K8
, K8
, false),
1013 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1014 ARCH (bdver1
, BD
, BDVER1
, false),
1015 ARCH (bdver2
, BD
, BDVER2
, false),
1016 ARCH (bdver3
, BD
, BDVER3
, false),
1017 ARCH (bdver4
, BD
, BDVER4
, false),
1018 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1019 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1020 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1021 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1022 ARCH (btver1
, BT
, BTVER1
, false),
1023 ARCH (btver2
, BT
, BTVER2
, false),
1025 SUBARCH (8087, 8087, ANY_8087
, false),
1026 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1027 SUBARCH (287, 287, ANY_287
, false),
1028 SUBARCH (387, 387, ANY_387
, false),
1029 SUBARCH (687, 687, ANY_687
, false),
1030 SUBARCH (cmov
, CMOV
, CMOV
, false),
1031 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1032 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1033 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1034 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1035 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1036 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1037 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1038 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1039 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1040 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1041 VECARCH (avx
, AVX
, ANY_AVX
, reset
),
1042 VECARCH (avx2
, AVX2
, ANY_AVX2
, reset
),
1043 VECARCH (avx512f
, AVX512F
, ANY_AVX512F
, reset
),
1044 VECARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, reset
),
1045 VECARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, reset
),
1046 VECARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, reset
),
1047 VECARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, reset
),
1048 VECARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, reset
),
1049 VECARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, reset
),
1050 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1051 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1052 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1053 SUBARCH (smx
, SMX
, SMX
, false),
1054 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1055 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1056 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1057 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1058 SUBARCH (aes
, AES
, ANY_AES
, false),
1059 SUBARCH (pclmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, false),
1060 SUBARCH (clmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, true),
1061 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1062 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1063 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1064 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1065 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1066 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1067 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1068 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1069 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1070 SUBARCH (cx16
, CX16
, CX16
, false),
1071 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1072 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1073 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1074 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1075 SUBARCH (hle
, HLE
, HLE
, false),
1076 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1077 SUBARCH (tsx
, TSX
, TSX
, false),
1078 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1079 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1080 SUBARCH (nop
, NOP
, NOP
, false),
1081 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1082 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1083 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1084 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1085 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1086 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1087 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1088 SUBARCH (abm
, ABM
, ABM
, false),
1089 SUBARCH (bmi
, BMI
, BMI
, false),
1090 SUBARCH (tbm
, TBM
, TBM
, false),
1091 SUBARCH (adx
, ADX
, ADX
, false),
1092 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1093 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1094 SUBARCH (smap
, SMAP
, SMAP
, false),
1095 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1096 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1097 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1098 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1099 SUBARCH (se1
, SE1
, SE1
, false),
1100 SUBARCH (clwb
, CLWB
, CLWB
, false),
1101 VECARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, reset
),
1102 VECARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, reset
),
1103 VECARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, reset
),
1104 VECARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, reset
),
1105 VECARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, reset
),
1106 VECARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, reset
),
1107 VECARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, reset
),
1108 VECARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, reset
),
1109 VECARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, reset
),
1110 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1111 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1112 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1113 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1114 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1115 SUBARCH (ibt
, IBT
, IBT
, false),
1116 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1117 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1118 VECARCH (vaes
, VAES
, ANY_VAES
, reset
),
1119 VECARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, reset
),
1120 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1121 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1122 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1123 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1124 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1125 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1126 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1127 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1128 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1129 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1130 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1131 VECARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, reset
),
1132 VECARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1133 ANY_AVX512_VP2INTERSECT
, reset
),
1134 SUBARCH (tdx
, TDX
, TDX
, false),
1135 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1136 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1137 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1138 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1139 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1140 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1141 SUBARCH (kl
, KL
, ANY_KL
, false),
1142 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1143 SUBARCH (uintr
, UINTR
, UINTR
, false),
1144 SUBARCH (hreset
, HRESET
, HRESET
, false),
1145 VECARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, reset
),
1146 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1147 VECARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, reset
),
1148 VECARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, reset
),
1149 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1150 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1151 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1152 VECARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, reset
),
1153 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1154 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1155 SUBARCH (fred
, FRED
, ANY_FRED
, false),
1156 SUBARCH (lkgs
, LKGS
, ANY_LKGS
, false),
1157 VECARCH (avx_vnni_int16
, AVX_VNNI_INT16
, ANY_AVX_VNNI_INT16
, reset
),
1158 VECARCH (sha512
, SHA512
, ANY_SHA512
, reset
),
1159 VECARCH (sm3
, SM3
, ANY_SM3
, reset
),
1160 VECARCH (sm4
, SM4
, ANY_SM4
, reset
),
1161 SUBARCH (pbndkb
, PBNDKB
, PBNDKB
, false),
1162 VECARCH (avx10
.1
, AVX10_1
, ANY_AVX512F
, set
),
1163 SUBARCH (user_msr
, USER_MSR
, USER_MSR
, false),
1170 /* Like s_lcomm_internal in gas/read.c but the alignment string
1171 is allowed to be optional. */
1174 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1181 && *input_line_pointer
== ',')
1183 align
= parse_align (needs_align
- 1);
1185 if (align
== (addressT
) -1)
1200 bss_alloc (symbolP
, size
, align
);
1205 pe_lcomm (int needs_align
)
1207 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1211 const pseudo_typeS md_pseudo_table
[] =
1213 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1214 {"align", s_align_bytes
, 0},
1216 {"align", s_align_ptwo
, 0},
1218 {"arch", set_cpu_arch
, 0},
1222 {"lcomm", pe_lcomm
, 1},
1224 {"ffloat", float_cons
, 'f'},
1225 {"dfloat", float_cons
, 'd'},
1226 {"tfloat", float_cons
, 'x'},
1227 {"hfloat", float_cons
, 'h'},
1228 {"bfloat16", float_cons
, 'b'},
1230 {"slong", signed_cons
, 4},
1231 {"insn", s_insn
, 0},
1232 {"noopt", s_ignore
, 0},
1233 {"optim", s_ignore
, 0},
1234 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1235 {"code16", set_code_flag
, CODE_16BIT
},
1236 {"code32", set_code_flag
, CODE_32BIT
},
1238 {"code64", set_code_flag
, CODE_64BIT
},
1240 {"intel_syntax", set_intel_syntax
, 1},
1241 {"att_syntax", set_intel_syntax
, 0},
1242 {"intel_mnemonic", set_intel_mnemonic
, 1},
1243 {"att_mnemonic", set_intel_mnemonic
, 0},
1244 {"allow_index_reg", set_allow_index_reg
, 1},
1245 {"disallow_index_reg", set_allow_index_reg
, 0},
1246 {"sse_check", set_check
, 0},
1247 {"operand_check", set_check
, 1},
1248 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1249 {"largecomm", handle_large_common
, 0},
1251 {"file", dwarf2_directive_file
, 0},
1252 {"loc", dwarf2_directive_loc
, 0},
1253 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1256 {"secrel32", pe_directive_secrel
, 0},
1257 {"secidx", pe_directive_secidx
, 0},
1262 /* For interface with expression (). */
1263 extern char *input_line_pointer
;
1265 /* Hash table for instruction mnemonic lookup. */
1266 static htab_t op_hash
;
1268 /* Hash table for register lookup. */
1269 static htab_t reg_hash
;
1271 /* Various efficient no-op patterns for aligning code labels.
1272 Note: Don't try to assemble the instructions in the comments.
1273 0L and 0w are not legal. */
1274 static const unsigned char f32_1
[] =
1276 static const unsigned char f32_2
[] =
1277 {0x66,0x90}; /* xchg %ax,%ax */
1278 static const unsigned char f32_3
[] =
1279 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1280 #define f32_4 (f32_5 + 1) /* leal 0(%esi,%eiz),%esi */
1281 static const unsigned char f32_5
[] =
1282 {0x2e,0x8d,0x74,0x26,0x00}; /* leal %cs:0(%esi,%eiz),%esi */
1283 static const unsigned char f32_6
[] =
1284 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1285 #define f32_7 (f32_8 + 1) /* leal 0L(%esi,%eiz),%esi */
1286 static const unsigned char f32_8
[] =
1287 {0x2e,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal %cs:0L(%esi,%eiz),%esi */
1288 static const unsigned char f64_3
[] =
1289 {0x48,0x89,0xf6}; /* mov %rsi,%rsi */
1290 static const unsigned char f64_4
[] =
1291 {0x48,0x8d,0x76,0x00}; /* lea 0(%rsi),%rsi */
1292 #define f64_5 (f64_6 + 1) /* lea 0(%rsi,%riz),%rsi */
1293 static const unsigned char f64_6
[] =
1294 {0x2e,0x48,0x8d,0x74,0x26,0x00}; /* lea %cs:0(%rsi,%riz),%rsi */
1295 static const unsigned char f64_7
[] =
1296 {0x48,0x8d,0xb6,0x00,0x00,0x00,0x00}; /* lea 0L(%rsi),%rsi */
1297 #define f64_8 (f64_9 + 1) /* lea 0L(%rsi,%riz),%rsi */
1298 static const unsigned char f64_9
[] =
1299 {0x2e,0x48,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* lea %cs:0L(%rsi,%riz),%rsi */
1300 #define f16_2 (f64_3 + 1) /* mov %si,%si */
1301 static const unsigned char f16_3
[] =
1302 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1303 #define f16_4 (f16_5 + 1) /* lea 0W(%si),%si */
1304 static const unsigned char f16_5
[] =
1305 {0x2e,0x8d,0xb4,0x00,0x00}; /* lea %cs:0W(%si),%si */
1306 static const unsigned char jump_disp8
[] =
1307 {0xeb}; /* jmp disp8 */
1308 static const unsigned char jump32_disp32
[] =
1309 {0xe9}; /* jmp disp32 */
1310 static const unsigned char jump16_disp32
[] =
1311 {0x66,0xe9}; /* jmp disp32 */
1312 /* 32-bit NOPs patterns. */
1313 static const unsigned char *const f32_patt
[] = {
1314 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
1316 /* 64-bit NOPs patterns. */
1317 static const unsigned char *const f64_patt
[] = {
1318 f32_1
, f32_2
, f64_3
, f64_4
, f64_5
, f64_6
, f64_7
, f64_8
, f64_9
1320 /* 16-bit NOPs patterns. */
1321 static const unsigned char *const f16_patt
[] = {
1322 f32_1
, f16_2
, f16_3
, f16_4
, f16_5
1324 /* nopl (%[re]ax) */
1325 static const unsigned char alt_3
[] =
1327 /* nopl 0(%[re]ax) */
1328 static const unsigned char alt_4
[] =
1329 {0x0f,0x1f,0x40,0x00};
1330 /* nopl 0(%[re]ax,%[re]ax,1) */
1331 #define alt_5 (alt_6 + 1)
1332 /* nopw 0(%[re]ax,%[re]ax,1) */
1333 static const unsigned char alt_6
[] =
1334 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1335 /* nopl 0L(%[re]ax) */
1336 static const unsigned char alt_7
[] =
1337 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1338 /* nopl 0L(%[re]ax,%[re]ax,1) */
1339 #define alt_8 (alt_9 + 1)
1340 /* nopw 0L(%[re]ax,%[re]ax,1) */
1341 static const unsigned char alt_9
[] =
1342 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1343 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1344 #define alt_10 (alt_11 + 1)
1345 /* data16 nopw %cs:0L(%eax,%eax,1) */
1346 static const unsigned char alt_11
[] =
1347 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1348 /* 32-bit and 64-bit NOPs patterns. */
1349 static const unsigned char *const alt_patt
[] = {
1350 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1351 alt_9
, alt_10
, alt_11
1354 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1355 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1358 i386_output_nops (char *where
, const unsigned char *const *patt
,
1359 int count
, int max_single_nop_size
)
1362 /* Place the longer NOP first. */
1365 const unsigned char *nops
;
1367 if (max_single_nop_size
< 1)
1369 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1370 max_single_nop_size
);
1374 nops
= patt
[max_single_nop_size
- 1];
1375 last
= count
% max_single_nop_size
;
1378 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1379 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1383 nops
= patt
[last
- 1];
1384 memcpy (where
+ offset
, nops
, last
);
1389 fits_in_imm7 (offsetT num
)
1391 return (num
& 0x7f) == num
;
1395 fits_in_imm31 (offsetT num
)
1397 return (num
& 0x7fffffff) == num
;
1400 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1401 single NOP instruction LIMIT. */
1404 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1406 const unsigned char *const *patt
= NULL
;
1407 int max_single_nop_size
;
1408 /* Maximum number of NOPs before switching to jump over NOPs. */
1409 int max_number_of_nops
;
1411 switch (fragP
->fr_type
)
1416 case rs_machine_dependent
:
1417 /* Allow NOP padding for jumps and calls. */
1418 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1419 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1426 /* We need to decide which NOP sequence to use for 32bit and
1427 64bit. When -mtune= is used:
1429 1. For PROCESSOR_I?86, PROCESSOR_PENTIUM, PROCESSOR_IAMCU, and
1430 PROCESSOR_GENERIC32, f32_patt will be used.
1431 2. For the rest, alt_patt will be used.
1433 When -mtune= isn't used, alt_patt will be used if
1434 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt/f64_patt will
1437 When -march= or .arch is used, we can't use anything beyond
1438 cpu_arch_isa_flags. */
1440 if (fragP
->tc_frag_data
.code
== CODE_16BIT
)
1443 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1444 /* Limit number of NOPs to 2 in 16-bit mode. */
1445 max_number_of_nops
= 2;
1449 patt
= fragP
->tc_frag_data
.code
== CODE_64BIT
? f64_patt
: f32_patt
;
1450 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1452 /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless
1453 explicitly disabled. */
1454 switch (fragP
->tc_frag_data
.tune
)
1456 case PROCESSOR_UNKNOWN
:
1457 /* We use cpu_arch_isa_flags to check if we SHOULD
1458 optimize with nops. */
1459 if (fragP
->tc_frag_data
.isanop
)
1463 case PROCESSOR_PENTIUMPRO
:
1464 case PROCESSOR_PENTIUM4
:
1465 case PROCESSOR_NOCONA
:
1466 case PROCESSOR_CORE
:
1467 case PROCESSOR_CORE2
:
1468 case PROCESSOR_COREI7
:
1469 case PROCESSOR_GENERIC64
:
1471 case PROCESSOR_ATHLON
:
1473 case PROCESSOR_AMDFAM10
:
1475 case PROCESSOR_ZNVER
:
1477 if (fragP
->tc_frag_data
.cpunop
)
1481 case PROCESSOR_I386
:
1482 case PROCESSOR_I486
:
1483 case PROCESSOR_PENTIUM
:
1484 case PROCESSOR_I686
:
1485 case PROCESSOR_IAMCU
:
1486 case PROCESSOR_GENERIC32
:
1488 case PROCESSOR_NONE
:
1494 switch (fragP
->tc_frag_data
.tune
)
1496 case PROCESSOR_UNKNOWN
:
1497 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1498 PROCESSOR_UNKNOWN. */
1503 /* We use cpu_arch_isa_flags to check if we CAN optimize
1505 if (fragP
->tc_frag_data
.isanop
)
1509 case PROCESSOR_NONE
:
1514 if (patt
!= alt_patt
)
1516 max_single_nop_size
= patt
== f32_patt
? ARRAY_SIZE (f32_patt
)
1517 : ARRAY_SIZE (f64_patt
);
1518 /* Limit number of NOPs to 2 for older processors. */
1519 max_number_of_nops
= 2;
1523 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1524 /* Limit number of NOPs to 7 for newer processors. */
1525 max_number_of_nops
= 7;
1530 limit
= max_single_nop_size
;
1532 if (fragP
->fr_type
== rs_fill_nop
)
1534 /* Output NOPs for .nop directive. */
1535 if (limit
> max_single_nop_size
)
1537 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1538 _("invalid single nop size: %d "
1539 "(expect within [0, %d])"),
1540 limit
, max_single_nop_size
);
1544 else if (fragP
->fr_type
!= rs_machine_dependent
)
1545 fragP
->fr_var
= count
;
1547 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1549 /* Generate jump over NOPs. */
1550 offsetT disp
= count
- 2;
1551 if (fits_in_imm7 (disp
))
1553 /* Use "jmp disp8" if possible. */
1555 where
[0] = jump_disp8
[0];
1561 unsigned int size_of_jump
;
1563 if (flag_code
== CODE_16BIT
)
1565 where
[0] = jump16_disp32
[0];
1566 where
[1] = jump16_disp32
[1];
1571 where
[0] = jump32_disp32
[0];
1575 count
-= size_of_jump
+ 4;
1576 if (!fits_in_imm31 (count
))
1578 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1579 _("jump over nop padding out of range"));
1583 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1584 where
+= size_of_jump
+ 4;
1588 /* Generate multiple NOPs. */
1589 i386_output_nops (where
, patt
, count
, limit
);
1593 operand_type_all_zero (const union i386_operand_type
*x
)
1595 switch (ARRAY_SIZE(x
->array
))
1606 return !x
->array
[0];
1613 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1615 switch (ARRAY_SIZE(x
->array
))
1631 x
->bitfield
.class = ClassNone
;
1632 x
->bitfield
.instance
= InstanceNone
;
1636 operand_type_equal (const union i386_operand_type
*x
,
1637 const union i386_operand_type
*y
)
1639 switch (ARRAY_SIZE(x
->array
))
1642 if (x
->array
[2] != y
->array
[2])
1646 if (x
->array
[1] != y
->array
[1])
1650 return x
->array
[0] == y
->array
[0];
1658 _is_cpu (const i386_cpu_attr
*a
, enum i386_cpu cpu
)
1662 case Cpu287
: return a
->bitfield
.cpu287
;
1663 case Cpu387
: return a
->bitfield
.cpu387
;
1664 case Cpu3dnow
: return a
->bitfield
.cpu3dnow
;
1665 case Cpu3dnowA
: return a
->bitfield
.cpu3dnowa
;
1666 case CpuAVX
: return a
->bitfield
.cpuavx
;
1667 case CpuHLE
: return a
->bitfield
.cpuhle
;
1668 case CpuAVX512F
: return a
->bitfield
.cpuavx512f
;
1669 case CpuAVX512VL
: return a
->bitfield
.cpuavx512vl
;
1670 case Cpu64
: return a
->bitfield
.cpu64
;
1671 case CpuNo64
: return a
->bitfield
.cpuno64
;
1673 gas_assert (cpu
< CpuAttrEnums
);
1675 return a
->bitfield
.isa
== cpu
+ 1u;
1679 is_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1681 return _is_cpu(&t
->cpu
, cpu
);
1685 maybe_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1687 return _is_cpu(&t
->cpu_any
, cpu
);
1690 static i386_cpu_flags
cpu_flags_from_attr (i386_cpu_attr a
)
1692 const unsigned int bps
= sizeof (a
.array
[0]) * CHAR_BIT
;
1693 i386_cpu_flags f
= { .array
[0] = 0 };
1695 switch (ARRAY_SIZE(a
.array
))
1698 f
.array
[CpuAttrEnums
/ bps
]
1699 |= (a
.array
[0] >> CpuIsaBits
) << (CpuAttrEnums
% bps
);
1700 if (CpuAttrEnums
% bps
> CpuIsaBits
)
1701 f
.array
[CpuAttrEnums
/ bps
+ 1]
1702 = (a
.array
[0] >> CpuIsaBits
) >> (bps
- CpuAttrEnums
% bps
);
1709 f
.array
[(a
.bitfield
.isa
- 1) / bps
] |= 1u << ((a
.bitfield
.isa
- 1) % bps
);
1715 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1717 switch (ARRAY_SIZE(x
->array
))
1736 return !x
->array
[0];
1743 cpu_flags_equal (const union i386_cpu_flags
*x
,
1744 const union i386_cpu_flags
*y
)
1746 switch (ARRAY_SIZE(x
->array
))
1749 if (x
->array
[4] != y
->array
[4])
1753 if (x
->array
[3] != y
->array
[3])
1757 if (x
->array
[2] != y
->array
[2])
1761 if (x
->array
[1] != y
->array
[1])
1765 return x
->array
[0] == y
->array
[0];
1773 cpu_flags_check_cpu64 (const insn_template
*t
)
1775 return flag_code
== CODE_64BIT
1776 ? !t
->cpu
.bitfield
.cpuno64
1777 : !t
->cpu
.bitfield
.cpu64
;
1780 static INLINE i386_cpu_flags
1781 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1783 switch (ARRAY_SIZE (x
.array
))
1786 x
.array
[4] &= y
.array
[4];
1789 x
.array
[3] &= y
.array
[3];
1792 x
.array
[2] &= y
.array
[2];
1795 x
.array
[1] &= y
.array
[1];
1798 x
.array
[0] &= y
.array
[0];
1806 static INLINE i386_cpu_flags
1807 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1809 switch (ARRAY_SIZE (x
.array
))
1812 x
.array
[4] |= y
.array
[4];
1815 x
.array
[3] |= y
.array
[3];
1818 x
.array
[2] |= y
.array
[2];
1821 x
.array
[1] |= y
.array
[1];
1824 x
.array
[0] |= y
.array
[0];
1832 static INLINE i386_cpu_flags
1833 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1835 switch (ARRAY_SIZE (x
.array
))
1838 x
.array
[4] &= ~y
.array
[4];
1841 x
.array
[3] &= ~y
.array
[3];
1844 x
.array
[2] &= ~y
.array
[2];
1847 x
.array
[1] &= ~y
.array
[1];
1850 x
.array
[0] &= ~y
.array
[0];
1858 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1860 static INLINE
bool need_evex_encoding (void)
1862 return i
.vec_encoding
== vex_encoding_evex
1863 || i
.vec_encoding
== vex_encoding_evex512
1867 #define CPU_FLAGS_ARCH_MATCH 0x1
1868 #define CPU_FLAGS_64BIT_MATCH 0x2
1870 #define CPU_FLAGS_PERFECT_MATCH \
1871 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1873 /* Return CPU flags match bits. */
1876 cpu_flags_match (const insn_template
*t
)
1878 i386_cpu_flags cpu
, active
, all
= cpu_flags_from_attr (t
->cpu
);
1879 i386_cpu_flags any
= cpu_flags_from_attr (t
->cpu_any
);
1880 int match
= cpu_flags_check_cpu64 (t
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1882 all
.bitfield
.cpu64
= 0;
1883 all
.bitfield
.cpuno64
= 0;
1884 gas_assert (!any
.bitfield
.cpu64
);
1885 gas_assert (!any
.bitfield
.cpuno64
);
1887 if (cpu_flags_all_zero (&all
) && cpu_flags_all_zero (&any
))
1889 /* This instruction is available on all archs. */
1890 return match
| CPU_FLAGS_ARCH_MATCH
;
1893 /* This instruction is available only on some archs. */
1895 /* Dual VEX/EVEX templates may need stripping of one of the flags. */
1896 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
1898 /* Dual AVX/AVX512 templates need to retain AVX512* only if we already
1899 know that EVEX encoding will be needed. */
1900 if ((any
.bitfield
.cpuavx
|| any
.bitfield
.cpuavx2
|| any
.bitfield
.cpufma
)
1901 && (any
.bitfield
.cpuavx512f
|| any
.bitfield
.cpuavx512vl
))
1903 if (need_evex_encoding ())
1905 any
.bitfield
.cpuavx
= 0;
1906 any
.bitfield
.cpuavx2
= 0;
1907 any
.bitfield
.cpufma
= 0;
1909 /* need_evex_encoding() isn't reliable before operands were
1911 else if (i
.operands
)
1913 any
.bitfield
.cpuavx512f
= 0;
1914 any
.bitfield
.cpuavx512vl
= 0;
1919 if (flag_code
!= CODE_64BIT
)
1920 active
= cpu_flags_and_not (cpu_arch_flags
, cpu_64_flags
);
1922 active
= cpu_arch_flags
;
1923 cpu
= cpu_flags_and (all
, active
);
1924 if (cpu_flags_equal (&cpu
, &all
))
1926 /* AVX and AVX2 present at the same time express an operand size
1927 dependency - strip AVX2 for the purposes here. The operand size
1928 dependent check occurs in check_vecOperands(). */
1929 if (any
.bitfield
.cpuavx
&& any
.bitfield
.cpuavx2
)
1930 any
.bitfield
.cpuavx2
= 0;
1932 cpu
= cpu_flags_and (any
, active
);
1933 if (cpu_flags_all_zero (&any
) || !cpu_flags_all_zero (&cpu
))
1935 if (all
.bitfield
.cpuavx
)
1937 /* We need to check SSE2AVX with AVX. */
1938 if (!t
->opcode_modifier
.sse2avx
1939 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1940 match
|= CPU_FLAGS_ARCH_MATCH
;
1943 match
|= CPU_FLAGS_ARCH_MATCH
;
1949 static INLINE i386_operand_type
1950 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1952 if (x
.bitfield
.class != y
.bitfield
.class)
1953 x
.bitfield
.class = ClassNone
;
1954 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1955 x
.bitfield
.instance
= InstanceNone
;
1957 switch (ARRAY_SIZE (x
.array
))
1960 x
.array
[2] &= y
.array
[2];
1963 x
.array
[1] &= y
.array
[1];
1966 x
.array
[0] &= y
.array
[0];
1974 static INLINE i386_operand_type
1975 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1977 gas_assert (y
.bitfield
.class == ClassNone
);
1978 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1980 switch (ARRAY_SIZE (x
.array
))
1983 x
.array
[2] &= ~y
.array
[2];
1986 x
.array
[1] &= ~y
.array
[1];
1989 x
.array
[0] &= ~y
.array
[0];
1997 static INLINE i386_operand_type
1998 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2000 gas_assert (x
.bitfield
.class == ClassNone
||
2001 y
.bitfield
.class == ClassNone
||
2002 x
.bitfield
.class == y
.bitfield
.class);
2003 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2004 y
.bitfield
.instance
== InstanceNone
||
2005 x
.bitfield
.instance
== y
.bitfield
.instance
);
2007 switch (ARRAY_SIZE (x
.array
))
2010 x
.array
[2] |= y
.array
[2];
2013 x
.array
[1] |= y
.array
[1];
2016 x
.array
[0] |= y
.array
[0];
2024 static INLINE i386_operand_type
2025 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2027 gas_assert (y
.bitfield
.class == ClassNone
);
2028 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2030 switch (ARRAY_SIZE (x
.array
))
2033 x
.array
[2] ^= y
.array
[2];
2036 x
.array
[1] ^= y
.array
[1];
2039 x
.array
[0] ^= y
.array
[0];
2047 static const i386_operand_type anydisp
= {
2048 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
2060 operand_type_check (i386_operand_type t
, enum operand_type c
)
2065 return t
.bitfield
.class == Reg
;
2068 return (t
.bitfield
.imm8
2072 || t
.bitfield
.imm32s
2073 || t
.bitfield
.imm64
);
2076 return (t
.bitfield
.disp8
2077 || t
.bitfield
.disp16
2078 || t
.bitfield
.disp32
2079 || t
.bitfield
.disp64
);
2082 return (t
.bitfield
.disp8
2083 || t
.bitfield
.disp16
2084 || t
.bitfield
.disp32
2085 || t
.bitfield
.disp64
2086 || t
.bitfield
.baseindex
);
2095 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2096 between operand GIVEN and opeand WANTED for instruction template T. */
2099 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2102 return !((i
.types
[given
].bitfield
.byte
2103 && !t
->operand_types
[wanted
].bitfield
.byte
)
2104 || (i
.types
[given
].bitfield
.word
2105 && !t
->operand_types
[wanted
].bitfield
.word
)
2106 || (i
.types
[given
].bitfield
.dword
2107 && !t
->operand_types
[wanted
].bitfield
.dword
)
2108 || (i
.types
[given
].bitfield
.qword
2109 && (!t
->operand_types
[wanted
].bitfield
.qword
2110 /* Don't allow 64-bit (memory) operands outside of 64-bit
2111 mode, when they're used where a 64-bit GPR could also
2112 be used. Checking is needed for Intel Syntax only. */
2114 && flag_code
!= CODE_64BIT
2115 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2116 || t
->operand_types
[wanted
].bitfield
.class == Accum
2117 || t
->opcode_modifier
.isstring
))))
2118 || (i
.types
[given
].bitfield
.tbyte
2119 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2122 /* Return 1 if there is no conflict in SIMD register between operand
2123 GIVEN and opeand WANTED for instruction template T. */
2126 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2129 return !((i
.types
[given
].bitfield
.xmmword
2130 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2131 || (i
.types
[given
].bitfield
.ymmword
2132 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2133 || (i
.types
[given
].bitfield
.zmmword
2134 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2135 || (i
.types
[given
].bitfield
.tmmword
2136 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2139 /* Return 1 if there is no conflict in any size between operand GIVEN
2140 and opeand WANTED for instruction template T. */
2143 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2146 return (match_operand_size (t
, wanted
, given
)
2147 && !((i
.types
[given
].bitfield
.unspecified
2148 && !i
.broadcast
.type
2149 && !i
.broadcast
.bytes
2150 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2151 || (i
.types
[given
].bitfield
.fword
2152 && !t
->operand_types
[wanted
].bitfield
.fword
)
2153 /* For scalar opcode templates to allow register and memory
2154 operands at the same time, some special casing is needed
2155 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2156 down-conversion vpmov*. */
2157 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2158 && t
->operand_types
[wanted
].bitfield
.byte
2159 + t
->operand_types
[wanted
].bitfield
.word
2160 + t
->operand_types
[wanted
].bitfield
.dword
2161 + t
->operand_types
[wanted
].bitfield
.qword
2162 > !!t
->opcode_modifier
.broadcast
)
2163 ? (i
.types
[given
].bitfield
.xmmword
2164 || i
.types
[given
].bitfield
.ymmword
2165 || i
.types
[given
].bitfield
.zmmword
)
2166 : !match_simd_size(t
, wanted
, given
))));
2169 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2170 operands for instruction template T, and it has MATCH_REVERSE set if there
2171 is no size conflict on any operands for the template with operands reversed
2172 (and the template allows for reversing in the first place). */
2174 #define MATCH_STRAIGHT 1
2175 #define MATCH_REVERSE 2
2177 static INLINE
unsigned int
2178 operand_size_match (const insn_template
*t
)
2180 unsigned int j
, match
= MATCH_STRAIGHT
;
2182 /* Don't check non-absolute jump instructions. */
2183 if (t
->opcode_modifier
.jump
2184 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2187 /* Check memory and accumulator operand size. */
2188 for (j
= 0; j
< i
.operands
; j
++)
2190 if (i
.types
[j
].bitfield
.class != Reg
2191 && i
.types
[j
].bitfield
.class != RegSIMD
2192 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2195 if (t
->operand_types
[j
].bitfield
.class == Reg
2196 && !match_operand_size (t
, j
, j
))
2202 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2203 && !match_simd_size (t
, j
, j
))
2209 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2210 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2216 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2223 if (!t
->opcode_modifier
.d
)
2226 /* Check reverse. */
2227 gas_assert (i
.operands
>= 2);
2229 for (j
= 0; j
< i
.operands
; j
++)
2231 unsigned int given
= i
.operands
- j
- 1;
2233 /* For FMA4 and XOP insns VEX.W controls just the first two
2234 register operands. */
2235 if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
2236 given
= j
< 2 ? 1 - j
: j
;
2238 if (t
->operand_types
[j
].bitfield
.class == Reg
2239 && !match_operand_size (t
, j
, given
))
2242 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2243 && !match_simd_size (t
, j
, given
))
2246 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2247 && (!match_operand_size (t
, j
, given
)
2248 || !match_simd_size (t
, j
, given
)))
2251 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2255 return match
| MATCH_REVERSE
;
2259 operand_type_match (i386_operand_type overlap
,
2260 i386_operand_type given
)
2262 i386_operand_type temp
= overlap
;
2264 temp
.bitfield
.unspecified
= 0;
2265 temp
.bitfield
.byte
= 0;
2266 temp
.bitfield
.word
= 0;
2267 temp
.bitfield
.dword
= 0;
2268 temp
.bitfield
.fword
= 0;
2269 temp
.bitfield
.qword
= 0;
2270 temp
.bitfield
.tbyte
= 0;
2271 temp
.bitfield
.xmmword
= 0;
2272 temp
.bitfield
.ymmword
= 0;
2273 temp
.bitfield
.zmmword
= 0;
2274 temp
.bitfield
.tmmword
= 0;
2275 if (operand_type_all_zero (&temp
))
2278 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2282 i
.error
= operand_type_mismatch
;
2286 /* If given types g0 and g1 are registers they must be of the same type
2287 unless the expected operand type register overlap is null.
2288 Intel syntax sized memory operands are also checked here. */
2291 operand_type_register_match (i386_operand_type g0
,
2292 i386_operand_type t0
,
2293 i386_operand_type g1
,
2294 i386_operand_type t1
)
2296 if (g0
.bitfield
.class != Reg
2297 && g0
.bitfield
.class != RegSIMD
2298 && (g0
.bitfield
.unspecified
2299 || !operand_type_check (g0
, anymem
)))
2302 if (g1
.bitfield
.class != Reg
2303 && g1
.bitfield
.class != RegSIMD
2304 && (g1
.bitfield
.unspecified
2305 || !operand_type_check (g1
, anymem
)))
2308 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2309 && g0
.bitfield
.word
== g1
.bitfield
.word
2310 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2311 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2312 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2313 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2314 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2317 /* If expectations overlap in no more than a single size, all is fine. */
2318 g0
= operand_type_and (t0
, t1
);
2319 if (g0
.bitfield
.byte
2323 + g0
.bitfield
.xmmword
2324 + g0
.bitfield
.ymmword
2325 + g0
.bitfield
.zmmword
<= 1)
2328 i
.error
= register_type_mismatch
;
2333 static INLINE
unsigned int
2334 register_number (const reg_entry
*r
)
2336 unsigned int nr
= r
->reg_num
;
2338 if (r
->reg_flags
& RegRex
)
2341 if (r
->reg_flags
& RegVRex
)
2347 static INLINE
unsigned int
2348 mode_from_disp_size (i386_operand_type t
)
2350 if (t
.bitfield
.disp8
)
2352 else if (t
.bitfield
.disp16
2353 || t
.bitfield
.disp32
)
2360 fits_in_signed_byte (addressT num
)
2362 return num
+ 0x80 <= 0xff;
2366 fits_in_unsigned_byte (addressT num
)
2372 fits_in_unsigned_word (addressT num
)
2374 return num
<= 0xffff;
2378 fits_in_signed_word (addressT num
)
2380 return num
+ 0x8000 <= 0xffff;
2384 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2389 return num
+ 0x80000000 <= 0xffffffff;
2391 } /* fits_in_signed_long() */
2394 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2399 return num
<= 0xffffffff;
2401 } /* fits_in_unsigned_long() */
2403 static INLINE valueT
extend_to_32bit_address (addressT num
)
2406 if (fits_in_unsigned_long(num
))
2407 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2409 if (!fits_in_signed_long (num
))
2410 return num
& 0xffffffff;
2417 fits_in_disp8 (offsetT num
)
2419 int shift
= i
.memshift
;
2425 mask
= (1 << shift
) - 1;
2427 /* Return 0 if NUM isn't properly aligned. */
2431 /* Check if NUM will fit in 8bit after shift. */
2432 return fits_in_signed_byte (num
>> shift
);
2436 fits_in_imm4 (offsetT num
)
2438 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2439 return (num
& (i
.vec_encoding
!= vex_encoding_evex
? 0xf : 7)) == num
;
2442 static i386_operand_type
2443 smallest_imm_type (offsetT num
)
2445 i386_operand_type t
;
2447 operand_type_set (&t
, 0);
2448 t
.bitfield
.imm64
= 1;
2450 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2452 /* This code is disabled on the 486 because all the Imm1 forms
2453 in the opcode table are slower on the i486. They're the
2454 versions with the implicitly specified single-position
2455 displacement, which has another syntax if you really want to
2457 t
.bitfield
.imm1
= 1;
2458 t
.bitfield
.imm8
= 1;
2459 t
.bitfield
.imm8s
= 1;
2460 t
.bitfield
.imm16
= 1;
2461 t
.bitfield
.imm32
= 1;
2462 t
.bitfield
.imm32s
= 1;
2464 else if (fits_in_signed_byte (num
))
2466 if (fits_in_unsigned_byte (num
))
2467 t
.bitfield
.imm8
= 1;
2468 t
.bitfield
.imm8s
= 1;
2469 t
.bitfield
.imm16
= 1;
2470 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2471 t
.bitfield
.imm32
= 1;
2472 t
.bitfield
.imm32s
= 1;
2474 else if (fits_in_unsigned_byte (num
))
2476 t
.bitfield
.imm8
= 1;
2477 t
.bitfield
.imm16
= 1;
2478 t
.bitfield
.imm32
= 1;
2479 t
.bitfield
.imm32s
= 1;
2481 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2483 t
.bitfield
.imm16
= 1;
2484 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2485 t
.bitfield
.imm32
= 1;
2486 t
.bitfield
.imm32s
= 1;
2488 else if (fits_in_signed_long (num
))
2490 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2491 t
.bitfield
.imm32
= 1;
2492 t
.bitfield
.imm32s
= 1;
2494 else if (fits_in_unsigned_long (num
))
2495 t
.bitfield
.imm32
= 1;
2501 offset_in_range (offsetT val
, int size
)
2507 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2508 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2510 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2512 case sizeof (val
): return val
;
2516 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2517 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2518 (uint64_t) val
, (uint64_t) (val
& mask
));
2523 static INLINE
const char *insn_name (const insn_template
*t
)
2525 return &i386_mnemonics
[t
->mnem_off
];
2538 a. PREFIX_EXIST if attempting to add a prefix where one from the
2539 same class already exists.
2540 b. PREFIX_LOCK if lock prefix is added.
2541 c. PREFIX_REP if rep/repne prefix is added.
2542 d. PREFIX_DS if ds prefix is added.
2543 e. PREFIX_OTHER if other prefix is added.
2546 static enum PREFIX_GROUP
2547 add_prefix (unsigned int prefix
)
2549 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2552 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2553 && flag_code
== CODE_64BIT
)
2555 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2556 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2557 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2558 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2569 case DS_PREFIX_OPCODE
:
2572 case CS_PREFIX_OPCODE
:
2573 case ES_PREFIX_OPCODE
:
2574 case FS_PREFIX_OPCODE
:
2575 case GS_PREFIX_OPCODE
:
2576 case SS_PREFIX_OPCODE
:
2580 case REPNE_PREFIX_OPCODE
:
2581 case REPE_PREFIX_OPCODE
:
2586 case LOCK_PREFIX_OPCODE
:
2595 case ADDR_PREFIX_OPCODE
:
2599 case DATA_PREFIX_OPCODE
:
2603 if (i
.prefix
[q
] != 0)
2611 i
.prefix
[q
] |= prefix
;
2614 as_bad (_("same type of prefix used twice"));
2620 update_code_flag (int value
, int check
)
2622 PRINTF_LIKE ((*as_error
)) = check
? as_fatal
: as_bad
;
2624 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpu64
)
2626 as_error (_("64bit mode not supported on `%s'."),
2627 cpu_arch_name
? cpu_arch_name
: default_arch
);
2631 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2633 as_error (_("32bit mode not supported on `%s'."),
2634 cpu_arch_name
? cpu_arch_name
: default_arch
);
2638 flag_code
= (enum flag_code
) value
;
2640 stackop_size
= '\0';
2644 set_code_flag (int value
)
2646 update_code_flag (value
, 0);
2650 set_16bit_gcc_code_flag (int new_code_flag
)
2652 flag_code
= (enum flag_code
) new_code_flag
;
2653 if (flag_code
!= CODE_16BIT
)
2655 stackop_size
= LONG_MNEM_SUFFIX
;
2659 set_intel_syntax (int syntax_flag
)
2661 /* Find out if register prefixing is specified. */
2662 int ask_naked_reg
= 0;
2665 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2668 int e
= get_symbol_name (&string
);
2670 if (strcmp (string
, "prefix") == 0)
2672 else if (strcmp (string
, "noprefix") == 0)
2675 as_bad (_("bad argument to syntax directive."));
2676 (void) restore_line_pointer (e
);
2678 demand_empty_rest_of_line ();
2680 intel_syntax
= syntax_flag
;
2682 if (ask_naked_reg
== 0)
2683 allow_naked_reg
= (intel_syntax
2684 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2686 allow_naked_reg
= (ask_naked_reg
< 0);
2688 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2690 register_prefix
= allow_naked_reg
? "" : "%";
2694 set_intel_mnemonic (int mnemonic_flag
)
2696 intel_mnemonic
= mnemonic_flag
;
2700 set_allow_index_reg (int flag
)
2702 allow_index_reg
= flag
;
2706 set_check (int what
)
2708 enum check_kind
*kind
;
2713 kind
= &operand_check
;
2724 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2727 int e
= get_symbol_name (&string
);
2729 if (strcmp (string
, "none") == 0)
2731 else if (strcmp (string
, "warning") == 0)
2732 *kind
= check_warning
;
2733 else if (strcmp (string
, "error") == 0)
2734 *kind
= check_error
;
2736 as_bad (_("bad argument to %s_check directive."), str
);
2737 (void) restore_line_pointer (e
);
2740 as_bad (_("missing argument for %s_check directive"), str
);
2742 demand_empty_rest_of_line ();
2746 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2747 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2749 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2750 static const char *arch
;
2752 /* Intel MCU is only supported on ELF. */
2758 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2759 use default_arch. */
2760 arch
= cpu_arch_name
;
2762 arch
= default_arch
;
2765 /* If we are targeting Intel MCU, we must enable it. */
2766 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2767 == new_flag
.bitfield
.cpuiamcu
)
2770 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2775 extend_cpu_sub_arch_name (const char *pfx
, const char *name
)
2777 if (cpu_sub_arch_name
)
2778 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2779 pfx
, name
, (const char *) NULL
);
2781 cpu_sub_arch_name
= concat (pfx
, name
, (const char *) NULL
);
2784 static void isa_enable (unsigned int idx
)
2786 i386_cpu_flags flags
= cpu_flags_or (cpu_arch_flags
, cpu_arch
[idx
].enable
);
2788 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2790 extend_cpu_sub_arch_name (".", cpu_arch
[idx
].name
);
2791 cpu_arch_flags
= flags
;
2794 cpu_arch_isa_flags
= cpu_flags_or (cpu_arch_isa_flags
, cpu_arch
[idx
].enable
);
2797 static void isa_disable (unsigned int idx
)
2799 i386_cpu_flags flags
2800 = cpu_flags_and_not (cpu_arch_flags
, cpu_arch
[idx
].disable
);
2802 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2804 extend_cpu_sub_arch_name (".no", cpu_arch
[idx
].name
);
2805 cpu_arch_flags
= flags
;
2809 = cpu_flags_and_not (cpu_arch_isa_flags
, cpu_arch
[idx
].disable
);
2813 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2815 typedef struct arch_stack_entry
2817 const struct arch_stack_entry
*prev
;
2820 i386_cpu_flags flags
;
2821 i386_cpu_flags isa_flags
;
2822 enum processor_type isa
;
2823 enum flag_code flag_code
;
2824 unsigned int vector_size
;
2826 bool no_cond_jump_promotion
;
2828 static const arch_stack_entry
*arch_stack_top
;
2836 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
2838 as_bad (_("missing cpu architecture"));
2839 input_line_pointer
++;
2843 e
= get_symbol_name (&s
);
2846 if (strcmp (string
, "push") == 0)
2848 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2850 top
->name
= cpu_arch_name
;
2851 if (cpu_sub_arch_name
)
2852 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2854 top
->sub_name
= NULL
;
2855 top
->flags
= cpu_arch_flags
;
2856 top
->isa
= cpu_arch_isa
;
2857 top
->isa_flags
= cpu_arch_isa_flags
;
2858 top
->flag_code
= flag_code
;
2859 top
->vector_size
= vector_size
;
2860 top
->stackop_size
= stackop_size
;
2861 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2863 top
->prev
= arch_stack_top
;
2864 arch_stack_top
= top
;
2866 (void) restore_line_pointer (e
);
2867 demand_empty_rest_of_line ();
2871 if (strcmp (string
, "pop") == 0)
2873 const arch_stack_entry
*top
= arch_stack_top
;
2876 as_bad (_(".arch stack is empty"));
2877 else if (top
->flag_code
!= flag_code
2878 || top
->stackop_size
!= stackop_size
)
2880 static const unsigned int bits
[] = {
2886 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2887 bits
[top
->flag_code
],
2888 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2892 arch_stack_top
= top
->prev
;
2894 cpu_arch_name
= top
->name
;
2895 free (cpu_sub_arch_name
);
2896 cpu_sub_arch_name
= top
->sub_name
;
2897 cpu_arch_flags
= top
->flags
;
2898 cpu_arch_isa
= top
->isa
;
2899 cpu_arch_isa_flags
= top
->isa_flags
;
2900 vector_size
= top
->vector_size
;
2901 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2906 (void) restore_line_pointer (e
);
2907 demand_empty_rest_of_line ();
2911 if (strcmp (string
, "default") == 0)
2913 if (strcmp (default_arch
, "iamcu") == 0)
2914 string
= default_arch
;
2917 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2919 cpu_arch_name
= NULL
;
2920 free (cpu_sub_arch_name
);
2921 cpu_sub_arch_name
= NULL
;
2922 cpu_arch_flags
= cpu_unknown_flags
;
2923 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2924 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2925 if (!cpu_arch_tune_set
)
2926 cpu_arch_tune
= PROCESSOR_UNKNOWN
;
2928 vector_size
= VSZ_DEFAULT
;
2930 j
= ARRAY_SIZE (cpu_arch
) + 1;
2934 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2936 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2937 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2941 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2943 if (flag_code
== CODE_64BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpu64
)
2945 as_bad (_("64bit mode not supported on `%s'."),
2947 (void) restore_line_pointer (e
);
2948 ignore_rest_of_line ();
2952 if (flag_code
== CODE_32BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpui386
)
2954 as_bad (_("32bit mode not supported on `%s'."),
2956 (void) restore_line_pointer (e
);
2957 ignore_rest_of_line ();
2961 cpu_arch_name
= cpu_arch
[j
].name
;
2962 free (cpu_sub_arch_name
);
2963 cpu_sub_arch_name
= NULL
;
2964 cpu_arch_flags
= cpu_arch
[j
].enable
;
2965 cpu_arch_isa
= cpu_arch
[j
].type
;
2966 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2967 if (!cpu_arch_tune_set
)
2968 cpu_arch_tune
= cpu_arch_isa
;
2970 vector_size
= VSZ_DEFAULT
;
2972 pre_386_16bit_warned
= false;
2976 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
2981 (void) restore_line_pointer (e
);
2983 switch (cpu_arch
[j
].vsz
)
2989 #ifdef SVR4_COMMENT_CHARS
2990 if (*input_line_pointer
== ':' || *input_line_pointer
== '/')
2992 if (*input_line_pointer
== '/')
2995 ++input_line_pointer
;
2996 switch (get_absolute_expression ())
2998 case 512: vector_size
= VSZ512
; break;
2999 case 256: vector_size
= VSZ256
; break;
3000 case 128: vector_size
= VSZ128
; break;
3002 as_bad (_("Unrecognized vector size specifier"));
3003 ignore_rest_of_line ();
3010 vector_size
= VSZ_DEFAULT
;
3014 demand_empty_rest_of_line ();
3019 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
3021 /* Disable an ISA extension. */
3022 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
3023 if (cpu_arch
[j
].type
== PROCESSOR_NONE
3024 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
3028 if (cpu_arch
[j
].vsz
== vsz_set
)
3029 vector_size
= VSZ_DEFAULT
;
3031 (void) restore_line_pointer (e
);
3032 demand_empty_rest_of_line ();
3037 if (j
== ARRAY_SIZE (cpu_arch
))
3038 as_bad (_("no such architecture: `%s'"), string
);
3040 *input_line_pointer
= e
;
3042 no_cond_jump_promotion
= 0;
3043 if (*input_line_pointer
== ','
3044 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
3046 ++input_line_pointer
;
3047 e
= get_symbol_name (&s
);
3050 if (strcmp (string
, "nojumps") == 0)
3051 no_cond_jump_promotion
= 1;
3052 else if (strcmp (string
, "jumps") == 0)
3055 as_bad (_("no such architecture modifier: `%s'"), string
);
3057 (void) restore_line_pointer (e
);
3060 demand_empty_rest_of_line ();
3063 enum bfd_architecture
3066 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3068 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3069 || flag_code
== CODE_64BIT
)
3070 as_fatal (_("Intel MCU is 32bit ELF only"));
3071 return bfd_arch_iamcu
;
3074 return bfd_arch_i386
;
3080 if (startswith (default_arch
, "x86_64"))
3082 if (default_arch
[6] == '\0')
3083 return bfd_mach_x86_64
;
3085 return bfd_mach_x64_32
;
3087 else if (!strcmp (default_arch
, "i386")
3088 || !strcmp (default_arch
, "iamcu"))
3090 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3092 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3093 as_fatal (_("Intel MCU is 32bit ELF only"));
3094 return bfd_mach_i386_iamcu
;
3097 return bfd_mach_i386_i386
;
3100 as_fatal (_("unknown architecture"));
3103 #include "opcodes/i386-tbl.h"
3108 /* Support pseudo prefixes like {disp32}. */
3109 lex_type
['{'] = LEX_BEGIN_NAME
;
3111 /* Initialize op_hash hash table. */
3112 op_hash
= str_htab_create ();
3115 const insn_template
*const *sets
= i386_op_sets
;
3116 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
3118 /* Type checks to compensate for the conversion through void * which
3119 occurs during hash table insertion / lookup. */
3120 (void) sizeof (sets
== ¤t_templates
->start
);
3121 (void) sizeof (end
== ¤t_templates
->end
);
3122 for (; sets
< end
; ++sets
)
3123 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3124 as_fatal (_("duplicate %s"), insn_name (*sets
));
3127 /* Initialize reg_hash hash table. */
3128 reg_hash
= str_htab_create ();
3130 const reg_entry
*regtab
;
3131 unsigned int regtab_size
= i386_regtab_size
;
3133 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3135 switch (regtab
->reg_type
.bitfield
.class)
3138 if (regtab
->reg_type
.bitfield
.dword
)
3140 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3143 else if (regtab
->reg_type
.bitfield
.tbyte
)
3145 /* There's no point inserting st(<N>) in the hash table, as
3146 parentheses aren't included in register_chars[] anyway. */
3147 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3154 switch (regtab
->reg_num
)
3156 case 0: reg_es
= regtab
; break;
3157 case 2: reg_ss
= regtab
; break;
3158 case 3: reg_ds
= regtab
; break;
3163 if (!regtab
->reg_num
)
3168 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3169 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3173 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3178 for (c
= 0; c
< 256; c
++)
3180 if (ISDIGIT (c
) || ISLOWER (c
))
3182 mnemonic_chars
[c
] = c
;
3183 register_chars
[c
] = c
;
3184 operand_chars
[c
] = c
;
3186 else if (ISUPPER (c
))
3188 mnemonic_chars
[c
] = TOLOWER (c
);
3189 register_chars
[c
] = mnemonic_chars
[c
];
3190 operand_chars
[c
] = c
;
3192 #ifdef SVR4_COMMENT_CHARS
3193 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3194 operand_chars
[c
] = c
;
3198 operand_chars
[c
] = c
;
3201 mnemonic_chars
['_'] = '_';
3202 mnemonic_chars
['-'] = '-';
3203 mnemonic_chars
['.'] = '.';
3205 for (p
= extra_symbol_chars
; *p
!= '\0'; p
++)
3206 operand_chars
[(unsigned char) *p
] = *p
;
3207 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3208 operand_chars
[(unsigned char) *p
] = *p
;
3211 if (flag_code
== CODE_64BIT
)
3213 #if defined (OBJ_COFF) && defined (TE_PE)
3214 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3217 x86_dwarf2_return_column
= 16;
3219 x86_cie_data_alignment
= -8;
3220 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3221 x86_sframe_cfa_sp_reg
= 7;
3222 x86_sframe_cfa_fp_reg
= 6;
3227 x86_dwarf2_return_column
= 8;
3228 x86_cie_data_alignment
= -4;
3231 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3232 can be turned into BRANCH_PREFIX frag. */
3233 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3238 i386_print_statistics (FILE *file
)
3240 htab_print_statistics (file
, "i386 opcode", op_hash
);
3241 htab_print_statistics (file
, "i386 register", reg_hash
);
3247 htab_delete (op_hash
);
3248 htab_delete (reg_hash
);
3253 /* Debugging routines for md_assemble. */
3254 static void pte (insn_template
*);
3255 static void pt (i386_operand_type
);
3256 static void pe (expressionS
*);
3257 static void ps (symbolS
*);
3260 pi (const char *line
, i386_insn
*x
)
3264 fprintf (stdout
, "%s: template ", line
);
3266 fprintf (stdout
, " address: base %s index %s scale %x\n",
3267 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3268 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3269 x
->log2_scale_factor
);
3270 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3271 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3272 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3273 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3274 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3275 (x
->rex
& REX_W
) != 0,
3276 (x
->rex
& REX_R
) != 0,
3277 (x
->rex
& REX_X
) != 0,
3278 (x
->rex
& REX_B
) != 0);
3279 for (j
= 0; j
< x
->operands
; j
++)
3281 fprintf (stdout
, " #%d: ", j
+ 1);
3283 fprintf (stdout
, "\n");
3284 if (x
->types
[j
].bitfield
.class == Reg
3285 || x
->types
[j
].bitfield
.class == RegMMX
3286 || x
->types
[j
].bitfield
.class == RegSIMD
3287 || x
->types
[j
].bitfield
.class == RegMask
3288 || x
->types
[j
].bitfield
.class == SReg
3289 || x
->types
[j
].bitfield
.class == RegCR
3290 || x
->types
[j
].bitfield
.class == RegDR
3291 || x
->types
[j
].bitfield
.class == RegTR
3292 || x
->types
[j
].bitfield
.class == RegBND
)
3293 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3294 if (operand_type_check (x
->types
[j
], imm
))
3296 if (operand_type_check (x
->types
[j
], disp
))
3297 pe (x
->op
[j
].disps
);
3302 pte (insn_template
*t
)
3304 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3305 static const char *const opc_spc
[] = {
3306 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3307 "XOP08", "XOP09", "XOP0A",
3311 fprintf (stdout
, " %d operands ", t
->operands
);
3312 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3313 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3314 if (opc_spc
[t
->opcode_space
])
3315 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3316 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3317 if (t
->extension_opcode
!= None
)
3318 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3319 if (t
->opcode_modifier
.d
)
3320 fprintf (stdout
, "D");
3321 if (t
->opcode_modifier
.w
)
3322 fprintf (stdout
, "W");
3323 fprintf (stdout
, "\n");
3324 for (j
= 0; j
< t
->operands
; j
++)
3326 fprintf (stdout
, " #%d type ", j
+ 1);
3327 pt (t
->operand_types
[j
]);
3328 fprintf (stdout
, "\n");
3335 fprintf (stdout
, " operation %d\n", e
->X_op
);
3336 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3337 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3338 if (e
->X_add_symbol
)
3340 fprintf (stdout
, " add_symbol ");
3341 ps (e
->X_add_symbol
);
3342 fprintf (stdout
, "\n");
3346 fprintf (stdout
, " op_symbol ");
3347 ps (e
->X_op_symbol
);
3348 fprintf (stdout
, "\n");
3355 fprintf (stdout
, "%s type %s%s",
3357 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3358 segment_name (S_GET_SEGMENT (s
)));
3361 static struct type_name
3363 i386_operand_type mask
;
3366 const type_names
[] =
3368 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3369 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3370 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3371 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3372 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3373 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3374 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3375 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3376 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3377 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3378 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3379 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3380 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3381 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3382 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3383 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3384 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3385 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3386 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3387 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3388 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3389 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3390 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3391 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3392 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3393 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3394 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3395 { { .bitfield
= { .class = SReg
} }, "SReg" },
3396 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3397 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3398 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3399 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3400 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3401 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3405 pt (i386_operand_type t
)
3408 i386_operand_type a
;
3410 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3412 a
= operand_type_and (t
, type_names
[j
].mask
);
3413 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3414 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3419 #endif /* DEBUG386 */
3421 static bfd_reloc_code_real_type
3422 reloc (unsigned int size
,
3425 bfd_reloc_code_real_type other
)
3427 if (other
!= NO_RELOC
)
3429 reloc_howto_type
*rel
;
3434 case BFD_RELOC_X86_64_GOT32
:
3435 return BFD_RELOC_X86_64_GOT64
;
3437 case BFD_RELOC_X86_64_GOTPLT64
:
3438 return BFD_RELOC_X86_64_GOTPLT64
;
3440 case BFD_RELOC_X86_64_PLTOFF64
:
3441 return BFD_RELOC_X86_64_PLTOFF64
;
3443 case BFD_RELOC_X86_64_GOTPC32
:
3444 other
= BFD_RELOC_X86_64_GOTPC64
;
3446 case BFD_RELOC_X86_64_GOTPCREL
:
3447 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3449 case BFD_RELOC_X86_64_TPOFF32
:
3450 other
= BFD_RELOC_X86_64_TPOFF64
;
3452 case BFD_RELOC_X86_64_DTPOFF32
:
3453 other
= BFD_RELOC_X86_64_DTPOFF64
;
3459 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3460 if (other
== BFD_RELOC_SIZE32
)
3463 other
= BFD_RELOC_SIZE64
;
3466 as_bad (_("there are no pc-relative size relocations"));
3472 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3473 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3476 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3478 as_bad (_("unknown relocation (%u)"), other
);
3479 else if (size
!= bfd_get_reloc_size (rel
))
3480 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3481 bfd_get_reloc_size (rel
),
3483 else if (pcrel
&& !rel
->pc_relative
)
3484 as_bad (_("non-pc-relative relocation for pc-relative field"));
3485 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3487 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3489 as_bad (_("relocated field and relocation type differ in signedness"));
3498 as_bad (_("there are no unsigned pc-relative relocations"));
3501 case 1: return BFD_RELOC_8_PCREL
;
3502 case 2: return BFD_RELOC_16_PCREL
;
3503 case 4: return BFD_RELOC_32_PCREL
;
3504 case 8: return BFD_RELOC_64_PCREL
;
3506 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3513 case 4: return BFD_RELOC_X86_64_32S
;
3518 case 1: return BFD_RELOC_8
;
3519 case 2: return BFD_RELOC_16
;
3520 case 4: return BFD_RELOC_32
;
3521 case 8: return BFD_RELOC_64
;
3523 as_bad (_("cannot do %s %u byte relocation"),
3524 sign
> 0 ? "signed" : "unsigned", size
);
3530 /* Here we decide which fixups can be adjusted to make them relative to
3531 the beginning of the section instead of the symbol. Basically we need
3532 to make sure that the dynamic relocations are done correctly, so in
3533 some cases we force the original symbol to be used. */
3536 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3538 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3542 /* Don't adjust pc-relative references to merge sections in 64-bit
3544 if (use_rela_relocations
3545 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3549 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3550 and changed later by validate_fix. */
3551 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3552 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3555 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3556 for size relocations. */
3557 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3558 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3559 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3560 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3561 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3562 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3563 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3564 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3565 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3566 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3567 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3568 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3569 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3570 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3571 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3572 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3573 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3574 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3575 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3576 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3577 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3578 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3579 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3580 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3581 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3582 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3583 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3584 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3585 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3586 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3587 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3594 want_disp32 (const insn_template
*t
)
3596 return flag_code
!= CODE_64BIT
3597 || i
.prefix
[ADDR_PREFIX
]
3598 || (t
->mnem_off
== MN_lea
3599 && (!i
.types
[1].bitfield
.qword
3600 || t
->opcode_modifier
.size
== SIZE32
));
3604 intel_float_operand (const char *mnemonic
)
3606 /* Note that the value returned is meaningful only for opcodes with (memory)
3607 operands, hence the code here is free to improperly handle opcodes that
3608 have no operands (for better performance and smaller code). */
3610 if (mnemonic
[0] != 'f')
3611 return 0; /* non-math */
3613 switch (mnemonic
[1])
3615 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3616 the fs segment override prefix not currently handled because no
3617 call path can make opcodes without operands get here */
3619 return 2 /* integer op */;
3621 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3622 return 3; /* fldcw/fldenv */
3625 if (mnemonic
[2] != 'o' /* fnop */)
3626 return 3; /* non-waiting control op */
3629 if (mnemonic
[2] == 's')
3630 return 3; /* frstor/frstpm */
3633 if (mnemonic
[2] == 'a')
3634 return 3; /* fsave */
3635 if (mnemonic
[2] == 't')
3637 switch (mnemonic
[3])
3639 case 'c': /* fstcw */
3640 case 'd': /* fstdw */
3641 case 'e': /* fstenv */
3642 case 's': /* fsts[gw] */
3648 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3649 return 0; /* fxsave/fxrstor are not really math ops */
3657 install_template (const insn_template
*t
)
3663 /* Dual VEX/EVEX templates need stripping one of the possible variants. */
3664 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
3666 if ((maybe_cpu (t
, CpuAVX
) || maybe_cpu (t
, CpuAVX2
)
3667 || maybe_cpu (t
, CpuFMA
))
3668 && (maybe_cpu (t
, CpuAVX512F
) || maybe_cpu (t
, CpuAVX512VL
)))
3670 if (need_evex_encoding ())
3672 i
.tm
.opcode_modifier
.vex
= 0;
3673 i
.tm
.cpu
.bitfield
.cpuavx512f
= i
.tm
.cpu_any
.bitfield
.cpuavx512f
;
3674 i
.tm
.cpu
.bitfield
.cpuavx512vl
= i
.tm
.cpu_any
.bitfield
.cpuavx512vl
;
3678 i
.tm
.opcode_modifier
.evex
= 0;
3679 if (i
.tm
.cpu_any
.bitfield
.cpuavx
)
3680 i
.tm
.cpu
.bitfield
.cpuavx
= 1;
3681 else if (!i
.tm
.cpu
.bitfield
.isa
)
3682 i
.tm
.cpu
.bitfield
.isa
= i
.tm
.cpu_any
.bitfield
.isa
;
3684 gas_assert (i
.tm
.cpu
.bitfield
.isa
== i
.tm
.cpu_any
.bitfield
.isa
);
3689 /* Note that for pseudo prefixes this produces a length of 1. But for them
3690 the length isn't interesting at all. */
3691 for (l
= 1; l
< 4; ++l
)
3692 if (!(t
->base_opcode
>> (8 * l
)))
3695 i
.opcode_length
= l
;
3698 /* Build the VEX prefix. */
3701 build_vex_prefix (const insn_template
*t
)
3703 unsigned int register_specifier
;
3704 unsigned int vector_length
;
3707 /* Check register specifier. */
3708 if (i
.vex
.register_specifier
)
3710 register_specifier
=
3711 ~register_number (i
.vex
.register_specifier
) & 0xf;
3712 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3715 register_specifier
= 0xf;
3717 /* Use 2-byte VEX prefix by swapping destination and source operand
3718 if there are more than 1 register operand. */
3719 if (i
.reg_operands
> 1
3720 && i
.vec_encoding
!= vex_encoding_vex3
3721 && i
.dir_encoding
== dir_encoding_default
3722 && i
.operands
== i
.reg_operands
3723 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3724 && i
.tm
.opcode_space
== SPACE_0F
3725 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3730 swap_2_operands (0, i
.operands
- 1);
3732 gas_assert (i
.rm
.mode
== 3);
3736 i
.rm
.regmem
= i
.rm
.reg
;
3739 if (i
.tm
.opcode_modifier
.d
)
3740 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3741 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3742 else /* Use the next insn. */
3743 install_template (&t
[1]);
3746 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3747 are no memory operands and at least 3 register ones. */
3748 if (i
.reg_operands
>= 3
3749 && i
.vec_encoding
!= vex_encoding_vex3
3750 && i
.reg_operands
== i
.operands
- i
.imm_operands
3751 && i
.tm
.opcode_modifier
.vex
3752 && i
.tm
.opcode_modifier
.commutative
3753 && (i
.tm
.opcode_modifier
.sse2avx
3754 || (optimize
> 1 && !i
.no_optimize
))
3756 && i
.vex
.register_specifier
3757 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3759 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3761 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3762 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3763 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3764 &i
.types
[i
.operands
- 3]));
3765 gas_assert (i
.rm
.mode
== 3);
3767 swap_2_operands (xchg
, xchg
+ 1);
3770 xchg
= i
.rm
.regmem
| 8;
3771 i
.rm
.regmem
= ~register_specifier
& 0xf;
3772 gas_assert (!(i
.rm
.regmem
& 8));
3773 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3774 register_specifier
= ~xchg
& 0xf;
3777 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3778 vector_length
= avxscalar
;
3779 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3781 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3787 /* Determine vector length from the last multi-length vector
3790 for (op
= t
->operands
; op
--;)
3791 if (t
->operand_types
[op
].bitfield
.xmmword
3792 && t
->operand_types
[op
].bitfield
.ymmword
3793 && i
.types
[op
].bitfield
.ymmword
)
3800 /* Check the REX.W bit and VEXW. */
3801 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3802 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3803 else if (i
.tm
.opcode_modifier
.vexw
)
3804 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3806 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3808 /* Use 2-byte VEX prefix if possible. */
3810 && i
.vec_encoding
!= vex_encoding_vex3
3811 && i
.tm
.opcode_space
== SPACE_0F
3812 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3814 /* 2-byte VEX prefix. */
3818 i
.vex
.bytes
[0] = 0xc5;
3820 /* Check the REX.R bit. */
3821 r
= (i
.rex
& REX_R
) ? 0 : 1;
3822 i
.vex
.bytes
[1] = (r
<< 7
3823 | register_specifier
<< 3
3824 | vector_length
<< 2
3825 | i
.tm
.opcode_modifier
.opcodeprefix
);
3829 /* 3-byte VEX prefix. */
3832 switch (i
.tm
.opcode_space
)
3838 i
.vex
.bytes
[0] = 0xc4;
3843 i
.vex
.bytes
[0] = 0x8f;
3849 /* The high 3 bits of the second VEX byte are 1's compliment
3850 of RXB bits from REX. */
3851 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3852 | (!dot_insn () ? i
.tm
.opcode_space
3853 : i
.insn_opcode_space
);
3855 i
.vex
.bytes
[2] = (w
<< 7
3856 | register_specifier
<< 3
3857 | vector_length
<< 2
3858 | i
.tm
.opcode_modifier
.opcodeprefix
);
3863 is_any_vex_encoding (const insn_template
*t
)
3865 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.evex
;
3869 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3871 unsigned int op
, bytes
;
3872 const i386_operand_type
*types
;
3874 if (i
.broadcast
.type
)
3875 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3877 gas_assert (intel_syntax
);
3879 for (op
= 0; op
< t
->operands
; ++op
)
3880 if (t
->operand_types
[op
].bitfield
.baseindex
)
3883 gas_assert (op
< t
->operands
);
3885 if (t
->opcode_modifier
.evex
!= EVEXDYN
)
3886 switch (i
.broadcast
.bytes
)
3889 if (t
->operand_types
[op
].bitfield
.word
)
3893 if (t
->operand_types
[op
].bitfield
.dword
)
3897 if (t
->operand_types
[op
].bitfield
.qword
)
3901 if (t
->operand_types
[op
].bitfield
.xmmword
)
3903 if (t
->operand_types
[op
].bitfield
.ymmword
)
3905 if (t
->operand_types
[op
].bitfield
.zmmword
)
3912 gas_assert (op
+ 1 < t
->operands
);
3914 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3915 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3916 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3918 types
= &i
.types
[op
+ 1];
3921 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3922 types
= &t
->operand_types
[op
];
3924 if (types
->bitfield
.zmmword
)
3926 else if (types
->bitfield
.ymmword
)
3932 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3933 insn_name (t
), bytes
* 8);
3938 /* Build the EVEX prefix. */
3941 build_evex_prefix (void)
3943 unsigned int register_specifier
, w
;
3944 rex_byte vrex_used
= 0;
3946 /* Check register specifier. */
3947 if (i
.vex
.register_specifier
)
3949 gas_assert ((i
.vrex
& REX_X
) == 0);
3951 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3952 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3953 register_specifier
+= 8;
3954 /* The upper 16 registers are encoded in the fourth byte of the
3956 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3957 i
.vex
.bytes
[3] = 0x8;
3958 register_specifier
= ~register_specifier
& 0xf;
3962 register_specifier
= 0xf;
3964 /* Encode upper 16 vector index register in the fourth byte of
3966 if (!(i
.vrex
& REX_X
))
3967 i
.vex
.bytes
[3] = 0x8;
3972 /* 4 byte EVEX prefix. */
3974 i
.vex
.bytes
[0] = 0x62;
3976 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3978 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
3979 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
3980 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3981 | (!dot_insn () ? i
.tm
.opcode_space
3982 : i
.insn_opcode_space
);
3984 /* The fifth bit of the second EVEX byte is 1's compliment of the
3985 REX_R bit in VREX. */
3986 if (!(i
.vrex
& REX_R
))
3987 i
.vex
.bytes
[1] |= 0x10;
3991 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3993 /* When all operands are registers, the REX_X bit in REX is not
3994 used. We reuse it to encode the upper 16 registers, which is
3995 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3996 as 1's compliment. */
3997 if ((i
.vrex
& REX_B
))
4000 i
.vex
.bytes
[1] &= ~0x40;
4004 /* EVEX instructions shouldn't need the REX prefix. */
4005 i
.vrex
&= ~vrex_used
;
4006 gas_assert (i
.vrex
== 0);
4008 /* Check the REX.W bit and VEXW. */
4009 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
4010 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
4011 else if (i
.tm
.opcode_modifier
.vexw
)
4012 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
4014 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
4016 /* The third byte of the EVEX prefix. */
4017 i
.vex
.bytes
[2] = ((w
<< 7)
4018 | (register_specifier
<< 3)
4019 | 4 /* Encode the U bit. */
4020 | i
.tm
.opcode_modifier
.opcodeprefix
);
4022 /* The fourth byte of the EVEX prefix. */
4023 /* The zeroing-masking bit. */
4024 if (i
.mask
.reg
&& i
.mask
.zeroing
)
4025 i
.vex
.bytes
[3] |= 0x80;
4027 /* Don't always set the broadcast bit if there is no RC. */
4028 if (i
.rounding
.type
== rc_none
)
4030 /* Encode the vector length. */
4031 unsigned int vec_length
;
4033 if (i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
4037 /* Determine vector length from the last multi-length vector
4039 for (op
= i
.operands
; op
--;)
4040 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
4041 + i
.tm
.operand_types
[op
].bitfield
.ymmword
4042 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
4044 if (i
.types
[op
].bitfield
.zmmword
)
4046 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4049 else if (i
.types
[op
].bitfield
.ymmword
)
4051 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4054 else if (i
.types
[op
].bitfield
.xmmword
)
4056 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4059 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
4060 && op
== i
.broadcast
.operand
)
4062 switch (get_broadcast_bytes (&i
.tm
, true))
4065 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4068 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4071 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4080 if (op
>= MAX_OPERANDS
)
4084 switch (i
.tm
.opcode_modifier
.evex
)
4086 case EVEXLIG
: /* LL' is ignored */
4087 vec_length
= evexlig
<< 5;
4090 vec_length
= 0 << 5;
4093 vec_length
= 1 << 5;
4096 vec_length
= 2 << 5;
4101 vec_length
= 3 << 5;
4109 i
.vex
.bytes
[3] |= vec_length
;
4110 /* Encode the broadcast bit. */
4111 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
4112 i
.vex
.bytes
[3] |= 0x10;
4114 else if (i
.rounding
.type
!= saeonly
)
4115 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4117 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4120 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4124 process_immext (void)
4128 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4129 which is coded in the same place as an 8-bit immediate field
4130 would be. Here we fake an 8-bit immediate operand from the
4131 opcode suffix stored in tm.extension_opcode.
4133 AVX instructions also use this encoding, for some of
4134 3 argument instructions. */
4136 gas_assert (i
.imm_operands
<= 1
4138 || (is_any_vex_encoding (&i
.tm
)
4139 && i
.operands
<= 4)));
4141 exp
= &im_expressions
[i
.imm_operands
++];
4142 i
.op
[i
.operands
].imms
= exp
;
4143 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4145 exp
->X_op
= O_constant
;
4146 exp
->X_add_number
= i
.tm
.extension_opcode
;
4147 i
.tm
.extension_opcode
= None
;
4154 switch (i
.tm
.opcode_modifier
.prefixok
)
4162 as_bad (_("invalid instruction `%s' after `%s'"),
4163 insn_name (&i
.tm
), i
.hle_prefix
);
4166 if (i
.prefix
[LOCK_PREFIX
])
4168 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4172 case PrefixHLERelease
:
4173 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4175 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4179 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4181 as_bad (_("memory destination needed for instruction `%s'"
4182 " after `xrelease'"), insn_name (&i
.tm
));
4189 /* Encode aligned vector move as unaligned vector move. */
4192 encode_with_unaligned_vector_move (void)
4194 switch (i
.tm
.base_opcode
)
4196 case 0x28: /* Load instructions. */
4197 case 0x29: /* Store instructions. */
4198 /* movaps/movapd/vmovaps/vmovapd. */
4199 if (i
.tm
.opcode_space
== SPACE_0F
4200 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4201 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4203 case 0x6f: /* Load instructions. */
4204 case 0x7f: /* Store instructions. */
4205 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4206 if (i
.tm
.opcode_space
== SPACE_0F
4207 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4208 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4215 /* Try the shortest encoding by shortening operand size. */
4218 optimize_encoding (void)
4222 if (i
.tm
.mnem_off
== MN_lea
)
4225 lea symbol, %rN -> mov $symbol, %rN
4226 lea (%rM), %rN -> mov %rM, %rN
4227 lea (,%rM,1), %rN -> mov %rM, %rN
4229 and in 32-bit mode for 16-bit addressing
4231 lea (%rM), %rN -> movzx %rM, %rN
4233 and in 64-bit mode zap 32-bit addressing in favor of using a
4234 32-bit (or less) destination.
4236 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4238 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4239 i
.tm
.opcode_modifier
.size
= SIZE32
;
4240 i
.prefix
[ADDR_PREFIX
] = 0;
4243 if (!i
.index_reg
&& !i
.base_reg
)
4246 lea symbol, %rN -> mov $symbol, %rN
4248 if (flag_code
== CODE_64BIT
)
4250 /* Don't transform a relocation to a 16-bit one. */
4252 && i
.op
[0].disps
->X_op
!= O_constant
4253 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4256 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4257 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4259 i
.tm
.base_opcode
= 0xb8;
4260 i
.tm
.opcode_modifier
.modrm
= 0;
4261 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4262 i
.types
[0].bitfield
.imm32
= 1;
4265 i
.tm
.opcode_modifier
.size
= SIZE16
;
4266 i
.types
[0].bitfield
.imm16
= 1;
4271 /* Subject to further optimization below. */
4272 i
.tm
.base_opcode
= 0xc7;
4273 i
.tm
.extension_opcode
= 0;
4274 i
.types
[0].bitfield
.imm32s
= 1;
4275 i
.types
[0].bitfield
.baseindex
= 0;
4278 /* Outside of 64-bit mode address and operand sizes have to match if
4279 a relocation is involved, as otherwise we wouldn't (currently) or
4280 even couldn't express the relocation correctly. */
4281 else if (i
.op
[0].disps
4282 && i
.op
[0].disps
->X_op
!= O_constant
4283 && ((!i
.prefix
[ADDR_PREFIX
])
4284 != (flag_code
== CODE_32BIT
4285 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4286 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4288 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4289 destination is going to grow encoding size. */
4290 else if (flag_code
== CODE_16BIT
4291 && (optimize
<= 1 || optimize_for_space
)
4292 && !i
.prefix
[ADDR_PREFIX
]
4293 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4297 i
.tm
.base_opcode
= 0xb8;
4298 i
.tm
.opcode_modifier
.modrm
= 0;
4299 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4300 i
.types
[0].bitfield
.imm32
= 1;
4302 i
.types
[0].bitfield
.imm16
= 1;
4305 && i
.op
[0].disps
->X_op
== O_constant
4306 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4307 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4309 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4310 i
.op
[0].disps
->X_add_number
&= 0xffff;
4313 i
.tm
.operand_types
[0] = i
.types
[0];
4317 i
.op
[0].imms
= &im_expressions
[0];
4318 i
.op
[0].imms
->X_op
= O_absent
;
4321 else if (i
.op
[0].disps
4322 && (i
.op
[0].disps
->X_op
!= O_constant
4323 || i
.op
[0].disps
->X_add_number
))
4328 lea (%rM), %rN -> mov %rM, %rN
4329 lea (,%rM,1), %rN -> mov %rM, %rN
4330 lea (%rM), %rN -> movzx %rM, %rN
4332 const reg_entry
*addr_reg
;
4334 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4335 addr_reg
= i
.base_reg
;
4336 else if (!i
.base_reg
4337 && i
.index_reg
->reg_num
!= RegIZ
4338 && !i
.log2_scale_factor
)
4339 addr_reg
= i
.index_reg
;
4343 if (addr_reg
->reg_type
.bitfield
.word
4344 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4346 if (flag_code
!= CODE_32BIT
)
4348 i
.tm
.opcode_space
= SPACE_0F
;
4349 i
.tm
.base_opcode
= 0xb7;
4352 i
.tm
.base_opcode
= 0x8b;
4354 if (addr_reg
->reg_type
.bitfield
.dword
4355 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4356 i
.tm
.opcode_modifier
.size
= SIZE32
;
4358 i
.op
[0].regs
= addr_reg
;
4363 i
.disp_operands
= 0;
4364 i
.prefix
[ADDR_PREFIX
] = 0;
4365 i
.prefix
[SEG_PREFIX
] = 0;
4369 if (optimize_for_space
4370 && i
.tm
.mnem_off
== MN_test
4371 && i
.reg_operands
== 1
4372 && i
.imm_operands
== 1
4373 && !i
.types
[1].bitfield
.byte
4374 && i
.op
[0].imms
->X_op
== O_constant
4375 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4378 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4380 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4381 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4383 i
.types
[1].bitfield
.byte
= 1;
4384 /* Ignore the suffix. */
4386 /* Convert to byte registers. */
4387 if (i
.types
[1].bitfield
.word
)
4389 else if (i
.types
[1].bitfield
.dword
)
4393 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4398 else if (flag_code
== CODE_64BIT
4399 && i
.tm
.opcode_space
== SPACE_BASE
4400 && ((i
.types
[1].bitfield
.qword
4401 && i
.reg_operands
== 1
4402 && i
.imm_operands
== 1
4403 && i
.op
[0].imms
->X_op
== O_constant
4404 && ((i
.tm
.base_opcode
== 0xb8
4405 && i
.tm
.extension_opcode
== None
4406 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4407 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4408 && (i
.tm
.base_opcode
== 0x24
4409 || (i
.tm
.base_opcode
== 0x80
4410 && i
.tm
.extension_opcode
== 0x4)
4411 || i
.tm
.mnem_off
== MN_test
4412 || ((i
.tm
.base_opcode
| 1) == 0xc7
4413 && i
.tm
.extension_opcode
== 0x0)))
4414 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4415 && i
.tm
.base_opcode
== 0x83
4416 && i
.tm
.extension_opcode
== 0x4)))
4417 || (i
.types
[0].bitfield
.qword
4418 && ((i
.reg_operands
== 2
4419 && i
.op
[0].regs
== i
.op
[1].regs
4420 && (i
.tm
.mnem_off
== MN_xor
4421 || i
.tm
.mnem_off
== MN_sub
))
4422 || i
.tm
.mnem_off
== MN_clr
))))
4425 andq $imm31, %r64 -> andl $imm31, %r32
4426 andq $imm7, %r64 -> andl $imm7, %r32
4427 testq $imm31, %r64 -> testl $imm31, %r32
4428 xorq %r64, %r64 -> xorl %r32, %r32
4429 subq %r64, %r64 -> subl %r32, %r32
4430 movq $imm31, %r64 -> movl $imm31, %r32
4431 movq $imm32, %r64 -> movl $imm32, %r32
4433 i
.tm
.opcode_modifier
.size
= SIZE32
;
4436 i
.types
[0].bitfield
.imm32
= 1;
4437 i
.types
[0].bitfield
.imm32s
= 0;
4438 i
.types
[0].bitfield
.imm64
= 0;
4442 i
.types
[0].bitfield
.dword
= 1;
4443 i
.types
[0].bitfield
.qword
= 0;
4445 i
.types
[1].bitfield
.dword
= 1;
4446 i
.types
[1].bitfield
.qword
= 0;
4447 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4450 movq $imm31, %r64 -> movl $imm31, %r32
4451 movq $imm32, %r64 -> movl $imm32, %r32
4453 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4454 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4455 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4456 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4459 movq $imm31, %r64 -> movl $imm31, %r32
4461 i
.tm
.base_opcode
= 0xb8;
4462 i
.tm
.extension_opcode
= None
;
4463 i
.tm
.opcode_modifier
.w
= 0;
4464 i
.tm
.opcode_modifier
.modrm
= 0;
4468 else if (optimize
> 1
4469 && !optimize_for_space
4470 && i
.reg_operands
== 2
4471 && i
.op
[0].regs
== i
.op
[1].regs
4472 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4473 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4476 andb %rN, %rN -> testb %rN, %rN
4477 andw %rN, %rN -> testw %rN, %rN
4478 andq %rN, %rN -> testq %rN, %rN
4479 orb %rN, %rN -> testb %rN, %rN
4480 orw %rN, %rN -> testw %rN, %rN
4481 orq %rN, %rN -> testq %rN, %rN
4483 and outside of 64-bit mode
4485 andl %rN, %rN -> testl %rN, %rN
4486 orl %rN, %rN -> testl %rN, %rN
4488 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4490 else if (i
.tm
.base_opcode
== 0xba
4491 && i
.tm
.opcode_space
== SPACE_0F
4492 && i
.reg_operands
== 1
4493 && i
.op
[0].imms
->X_op
== O_constant
4494 && i
.op
[0].imms
->X_add_number
>= 0)
4497 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4498 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4499 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4501 With <BT> one of bts, btr, and bts also:
4502 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4503 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4508 if (i
.tm
.extension_opcode
!= 4)
4510 if (i
.types
[1].bitfield
.qword
4511 && i
.op
[0].imms
->X_add_number
< 32
4512 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4513 i
.tm
.opcode_modifier
.size
= SIZE32
;
4516 if (i
.types
[1].bitfield
.word
4517 && i
.op
[0].imms
->X_add_number
< 16)
4518 i
.tm
.opcode_modifier
.size
= SIZE32
;
4521 if (i
.op
[0].imms
->X_add_number
< 16)
4522 i
.tm
.opcode_modifier
.size
= SIZE16
;
4526 else if (i
.reg_operands
== 3
4527 && i
.op
[0].regs
== i
.op
[1].regs
4528 && !i
.types
[2].bitfield
.xmmword
4529 && (i
.tm
.opcode_modifier
.vex
4530 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4531 && i
.tm
.opcode_modifier
.evex
4532 && (i
.vec_encoding
!= vex_encoding_evex
4533 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4534 || is_cpu (&i
.tm
, CpuAVX512VL
)
4535 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4536 && i
.types
[2].bitfield
.ymmword
))))
4537 && i
.tm
.opcode_space
== SPACE_0F
4538 && ((i
.tm
.base_opcode
| 2) == 0x57
4539 || i
.tm
.base_opcode
== 0xdf
4540 || i
.tm
.base_opcode
== 0xef
4541 || (i
.tm
.base_opcode
| 3) == 0xfb
4542 || i
.tm
.base_opcode
== 0x42
4543 || i
.tm
.base_opcode
== 0x47))
4546 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4548 EVEX VOP %zmmM, %zmmM, %zmmN
4549 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4550 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4551 EVEX VOP %ymmM, %ymmM, %ymmN
4552 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4553 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4554 VEX VOP %ymmM, %ymmM, %ymmN
4555 -> VEX VOP %xmmM, %xmmM, %xmmN
4556 VOP, one of vpandn and vpxor:
4557 VEX VOP %ymmM, %ymmM, %ymmN
4558 -> VEX VOP %xmmM, %xmmM, %xmmN
4559 VOP, one of vpandnd and vpandnq:
4560 EVEX VOP %zmmM, %zmmM, %zmmN
4561 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4562 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4563 EVEX VOP %ymmM, %ymmM, %ymmN
4564 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4565 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4566 VOP, one of vpxord and vpxorq:
4567 EVEX VOP %zmmM, %zmmM, %zmmN
4568 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4569 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4570 EVEX VOP %ymmM, %ymmM, %ymmN
4571 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4572 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4573 VOP, one of kxord and kxorq:
4574 VEX VOP %kM, %kM, %kN
4575 -> VEX kxorw %kM, %kM, %kN
4576 VOP, one of kandnd and kandnq:
4577 VEX VOP %kM, %kM, %kN
4578 -> VEX kandnw %kM, %kM, %kN
4580 if (i
.tm
.opcode_modifier
.evex
)
4582 if (i
.vec_encoding
!= vex_encoding_evex
)
4584 i
.tm
.opcode_modifier
.vex
= VEX128
;
4585 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4586 i
.tm
.opcode_modifier
.evex
= 0;
4587 i
.vec_encoding
= vex_encoding_vex
;
4590 else if (optimize
> 1)
4591 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4595 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4597 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4598 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4601 i
.tm
.opcode_modifier
.vex
= VEX128
;
4603 if (i
.tm
.opcode_modifier
.vex
)
4604 for (j
= 0; j
< 3; j
++)
4606 i
.types
[j
].bitfield
.xmmword
= 1;
4607 i
.types
[j
].bitfield
.ymmword
= 0;
4610 else if (i
.vec_encoding
!= vex_encoding_evex
4611 && !i
.types
[0].bitfield
.zmmword
4612 && !i
.types
[1].bitfield
.zmmword
4614 && !i
.broadcast
.type
4615 && !i
.broadcast
.bytes
4616 && i
.tm
.opcode_modifier
.evex
4617 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4618 || (i
.tm
.base_opcode
& ~4) == 0xdb
4619 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4620 && i
.tm
.extension_opcode
== None
)
4623 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4624 vmovdqu32 and vmovdqu64:
4625 EVEX VOP %xmmM, %xmmN
4626 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4627 EVEX VOP %ymmM, %ymmN
4628 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4630 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4632 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4634 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4636 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4637 VOP, one of vpand, vpandn, vpor, vpxor:
4638 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4639 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4640 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4641 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4642 EVEX VOP{d,q} mem, %xmmM, %xmmN
4643 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4644 EVEX VOP{d,q} mem, %ymmM, %ymmN
4645 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4647 for (j
= 0; j
< i
.operands
; j
++)
4648 if (operand_type_check (i
.types
[j
], disp
)
4649 && i
.op
[j
].disps
->X_op
== O_constant
)
4651 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4652 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4653 bytes, we choose EVEX Disp8 over VEX Disp32. */
4654 int evex_disp8
, vex_disp8
;
4655 unsigned int memshift
= i
.memshift
;
4656 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4658 evex_disp8
= fits_in_disp8 (n
);
4660 vex_disp8
= fits_in_disp8 (n
);
4661 if (evex_disp8
!= vex_disp8
)
4663 i
.memshift
= memshift
;
4667 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4670 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4671 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4672 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4673 i
.tm
.opcode_modifier
.vex
4674 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4675 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4676 /* VPAND, VPOR, and VPXOR are commutative. */
4677 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4678 i
.tm
.opcode_modifier
.commutative
= 1;
4679 i
.tm
.opcode_modifier
.evex
= 0;
4680 i
.tm
.opcode_modifier
.masking
= 0;
4681 i
.tm
.opcode_modifier
.broadcast
= 0;
4682 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4685 i
.types
[j
].bitfield
.disp8
4686 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4688 else if (optimize_for_space
4689 && i
.tm
.base_opcode
== 0x29
4690 && i
.tm
.opcode_space
== SPACE_0F38
4691 && i
.operands
== i
.reg_operands
4692 && i
.op
[0].regs
== i
.op
[1].regs
4693 && (!i
.tm
.opcode_modifier
.vex
4694 || !(i
.op
[0].regs
->reg_flags
& RegRex
))
4695 && !i
.tm
.opcode_modifier
.evex
)
4698 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4699 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4700 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4702 i
.tm
.opcode_space
= SPACE_0F
;
4703 i
.tm
.base_opcode
= 0x76;
4705 else if (((i
.tm
.base_opcode
>= 0x64
4706 && i
.tm
.base_opcode
<= 0x66
4707 && i
.tm
.opcode_space
== SPACE_0F
)
4708 || (i
.tm
.base_opcode
== 0x37
4709 && i
.tm
.opcode_space
== SPACE_0F38
))
4710 && i
.operands
== i
.reg_operands
4711 && i
.op
[0].regs
== i
.op
[1].regs
4712 && !i
.tm
.opcode_modifier
.evex
)
4715 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4716 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4717 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4718 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4719 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4720 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4722 i
.tm
.opcode_space
= SPACE_0F
;
4723 i
.tm
.base_opcode
= 0xef;
4724 if (i
.tm
.opcode_modifier
.vex
&& (i
.op
[0].regs
->reg_flags
& RegRex
))
4726 if (i
.operands
== 2)
4728 gas_assert (i
.tm
.opcode_modifier
.sse2avx
);
4734 i
.op
[2].regs
= i
.op
[0].regs
;
4735 i
.types
[2] = i
.types
[0];
4736 i
.flags
[2] = i
.flags
[0];
4737 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4739 i
.tm
.opcode_modifier
.sse2avx
= 0;
4741 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
+ 8;
4742 i
.op
[1].regs
= i
.op
[0].regs
;
4745 else if (optimize_for_space
4746 && i
.tm
.base_opcode
== 0x59
4747 && i
.tm
.opcode_space
== SPACE_0F38
4748 && i
.operands
== i
.reg_operands
4749 && i
.tm
.opcode_modifier
.vex
4750 && !(i
.op
[0].regs
->reg_flags
& RegRex
)
4751 && i
.op
[0].regs
->reg_type
.bitfield
.xmmword
4752 && i
.vec_encoding
!= vex_encoding_vex3
)
4755 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
4757 i
.tm
.opcode_space
= SPACE_0F
;
4758 i
.tm
.base_opcode
= 0x6c;
4759 i
.tm
.opcode_modifier
.vexvvvv
= 1;
4765 i
.op
[2].regs
= i
.op
[0].regs
;
4766 i
.types
[2] = i
.types
[0];
4767 i
.flags
[2] = i
.flags
[0];
4768 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4770 swap_2_operands (1, 2);
4774 /* Return non-zero for load instruction. */
4780 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4781 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4785 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4786 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4787 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4791 if (i
.tm
.mnem_off
== MN_pop
)
4795 if (i
.tm
.opcode_space
== SPACE_BASE
)
4798 if (i
.tm
.base_opcode
== 0x9d
4799 || i
.tm
.base_opcode
== 0x61)
4802 /* movs, cmps, lods, scas. */
4803 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4807 if (base_opcode
== 0x6f
4808 || i
.tm
.base_opcode
== 0xd7)
4810 /* NB: For AMD-specific insns with implicit memory operands,
4811 they're intentionally not covered. */
4814 /* No memory operand. */
4815 if (!i
.mem_operands
)
4820 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4823 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4825 /* test, not, neg, mul, imul, div, idiv. */
4826 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4830 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4833 /* add, or, adc, sbb, and, sub, xor, cmp. */
4834 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4837 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4838 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4839 && i
.tm
.extension_opcode
!= 6)
4842 /* Check for x87 instructions. */
4843 if ((base_opcode
| 6) == 0xdf)
4845 /* Skip fst, fstp, fstenv, fstcw. */
4846 if (i
.tm
.base_opcode
== 0xd9
4847 && (i
.tm
.extension_opcode
== 2
4848 || i
.tm
.extension_opcode
== 3
4849 || i
.tm
.extension_opcode
== 6
4850 || i
.tm
.extension_opcode
== 7))
4853 /* Skip fisttp, fist, fistp, fstp. */
4854 if (i
.tm
.base_opcode
== 0xdb
4855 && (i
.tm
.extension_opcode
== 1
4856 || i
.tm
.extension_opcode
== 2
4857 || i
.tm
.extension_opcode
== 3
4858 || i
.tm
.extension_opcode
== 7))
4861 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4862 if (i
.tm
.base_opcode
== 0xdd
4863 && (i
.tm
.extension_opcode
== 1
4864 || i
.tm
.extension_opcode
== 2
4865 || i
.tm
.extension_opcode
== 3
4866 || i
.tm
.extension_opcode
== 6
4867 || i
.tm
.extension_opcode
== 7))
4870 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4871 if (i
.tm
.base_opcode
== 0xdf
4872 && (i
.tm
.extension_opcode
== 1
4873 || i
.tm
.extension_opcode
== 2
4874 || i
.tm
.extension_opcode
== 3
4875 || i
.tm
.extension_opcode
== 6
4876 || i
.tm
.extension_opcode
== 7))
4882 else if (i
.tm
.opcode_space
== SPACE_0F
)
4884 /* bt, bts, btr, btc. */
4885 if (i
.tm
.base_opcode
== 0xba
4886 && (i
.tm
.extension_opcode
| 3) == 7)
4889 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4890 if (i
.tm
.base_opcode
== 0xc7
4891 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4892 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4893 || i
.tm
.extension_opcode
== 6))
4896 /* fxrstor, ldmxcsr, xrstor. */
4897 if (i
.tm
.base_opcode
== 0xae
4898 && (i
.tm
.extension_opcode
== 1
4899 || i
.tm
.extension_opcode
== 2
4900 || i
.tm
.extension_opcode
== 5))
4903 /* lgdt, lidt, lmsw. */
4904 if (i
.tm
.base_opcode
== 0x01
4905 && (i
.tm
.extension_opcode
== 2
4906 || i
.tm
.extension_opcode
== 3
4907 || i
.tm
.extension_opcode
== 6))
4911 dest
= i
.operands
- 1;
4913 /* Check fake imm8 operand and 3 source operands. */
4914 if ((i
.tm
.opcode_modifier
.immext
4915 || i
.reg_operands
+ i
.mem_operands
== 4)
4916 && i
.types
[dest
].bitfield
.imm8
)
4919 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4920 if (i
.tm
.opcode_space
== SPACE_BASE
4921 && ((base_opcode
| 0x38) == 0x39
4922 || (base_opcode
| 2) == 0x87))
4925 if (i
.tm
.mnem_off
== MN_xadd
)
4928 /* Check for load instruction. */
4929 return (i
.types
[dest
].bitfield
.class != ClassNone
4930 || i
.types
[dest
].bitfield
.instance
== Accum
);
4933 /* Output lfence, 0xfaee8, after instruction. */
4936 insert_lfence_after (void)
4938 if (lfence_after_load
&& load_insn_p ())
4940 /* There are also two REP string instructions that require
4941 special treatment. Specifically, the compare string (CMPS)
4942 and scan string (SCAS) instructions set EFLAGS in a manner
4943 that depends on the data being compared/scanned. When used
4944 with a REP prefix, the number of iterations may therefore
4945 vary depending on this data. If the data is a program secret
4946 chosen by the adversary using an LVI method,
4947 then this data-dependent behavior may leak some aspect
4949 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4950 && i
.prefix
[REP_PREFIX
])
4952 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4955 char *p
= frag_more (3);
4962 /* Output lfence, 0xfaee8, before instruction. */
4965 insert_lfence_before (void)
4969 if (i
.tm
.opcode_space
!= SPACE_BASE
)
4972 if (i
.tm
.base_opcode
== 0xff
4973 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4975 /* Insert lfence before indirect branch if needed. */
4977 if (lfence_before_indirect_branch
== lfence_branch_none
)
4980 if (i
.operands
!= 1)
4983 if (i
.reg_operands
== 1)
4985 /* Indirect branch via register. Don't insert lfence with
4986 -mlfence-after-load=yes. */
4987 if (lfence_after_load
4988 || lfence_before_indirect_branch
== lfence_branch_memory
)
4991 else if (i
.mem_operands
== 1
4992 && lfence_before_indirect_branch
!= lfence_branch_register
)
4994 as_warn (_("indirect `%s` with memory operand should be avoided"),
5001 if (last_insn
.kind
!= last_insn_other
5002 && last_insn
.seg
== now_seg
)
5004 as_warn_where (last_insn
.file
, last_insn
.line
,
5005 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
5006 last_insn
.name
, insn_name (&i
.tm
));
5017 /* Output or/not/shl and lfence before near ret. */
5018 if (lfence_before_ret
!= lfence_before_ret_none
5019 && (i
.tm
.base_opcode
| 1) == 0xc3)
5021 if (last_insn
.kind
!= last_insn_other
5022 && last_insn
.seg
== now_seg
)
5024 as_warn_where (last_insn
.file
, last_insn
.line
,
5025 _("`%s` skips -mlfence-before-ret on `%s`"),
5026 last_insn
.name
, insn_name (&i
.tm
));
5030 /* Near ret ingore operand size override under CPU64. */
5031 char prefix
= flag_code
== CODE_64BIT
5033 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
5035 if (lfence_before_ret
== lfence_before_ret_not
)
5037 /* not: 0xf71424, may add prefix
5038 for operand size override or 64-bit code. */
5039 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
5053 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
5056 if (lfence_before_ret
== lfence_before_ret_or
)
5058 /* or: 0x830c2400, may add prefix
5059 for operand size override or 64-bit code. */
5065 /* shl: 0xc1242400, may add prefix
5066 for operand size override or 64-bit code. */
5081 /* Shared helper for md_assemble() and s_insn(). */
5082 static void init_globals (void)
5086 memset (&i
, '\0', sizeof (i
));
5087 i
.rounding
.type
= rc_none
;
5088 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5089 i
.reloc
[j
] = NO_RELOC
;
5090 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
5091 memset (im_expressions
, '\0', sizeof (im_expressions
));
5092 save_stack_p
= save_stack
;
5095 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5096 parsing pass. Instead of introducing a rarely use new insn attribute this
5097 utilizes a common pattern between affected templates. It is deemed
5098 acceptable that this will lead to unnecessary pass 2 preparations in a
5099 limited set of cases. */
5100 static INLINE
bool may_need_pass2 (const insn_template
*t
)
5102 return t
->opcode_modifier
.sse2avx
5103 /* Note that all SSE2AVX templates have at least one operand. */
5104 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
5105 : (t
->opcode_space
== SPACE_0F
5106 && (t
->base_opcode
| 1) == 0xbf)
5107 || (t
->opcode_space
== SPACE_BASE
5108 && t
->base_opcode
== 0x63);
5111 /* This is the guts of the machine-dependent assembler. LINE points to a
5112 machine dependent instruction. This function is supposed to emit
5113 the frags/bytes it assembles to. */
5116 md_assemble (char *line
)
5119 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
5120 const char *end
, *pass1_mnem
= NULL
;
5121 enum i386_error pass1_err
= 0;
5122 const insn_template
*t
;
5124 /* Initialize globals. */
5125 current_templates
= NULL
;
5129 /* First parse an instruction mnemonic & call i386_operand for the operands.
5130 We assume that the scrubber has arranged it so that line[0] is the valid
5131 start of a (possibly prefixed) mnemonic. */
5133 end
= parse_insn (line
, mnemonic
, false);
5136 if (pass1_mnem
!= NULL
)
5138 if (i
.error
!= no_error
)
5140 gas_assert (current_templates
!= NULL
);
5141 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
5143 /* No point in trying a 2nd pass - it'll only find the same suffix
5145 mnem_suffix
= i
.suffix
;
5150 t
= current_templates
->start
;
5151 if (may_need_pass2 (t
))
5153 /* Make a copy of the full line in case we need to retry. */
5154 copy
= xstrdup (line
);
5157 mnem_suffix
= i
.suffix
;
5159 line
= parse_operands (line
, mnemonic
);
5167 /* Now we've parsed the mnemonic into a set of templates, and have the
5168 operands at hand. */
5170 /* All Intel opcodes have reversed operands except for "bound", "enter",
5171 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
5172 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
5173 intersegment "jmp" and "call" instructions with 2 immediate operands so
5174 that the immediate segment precedes the offset consistently in Intel and
5178 && (t
->mnem_off
!= MN_bound
)
5179 && !startswith (mnemonic
, "invlpg")
5180 && !startswith (mnemonic
, "monitor")
5181 && !startswith (mnemonic
, "mwait")
5182 && (t
->mnem_off
!= MN_pvalidate
)
5183 && !startswith (mnemonic
, "rmp")
5184 && (t
->mnem_off
!= MN_tpause
)
5185 && (t
->mnem_off
!= MN_umwait
)
5186 && !(i
.operands
== 2
5187 && operand_type_check (i
.types
[0], imm
)
5188 && operand_type_check (i
.types
[1], imm
)))
5191 /* The order of the immediates should be reversed for 2-immediates EXTRQ
5192 and INSERTQ instructions. Also UWRMSR wants its immediate to be in the
5193 "canonical" place (first), despite it appearing last (in AT&T syntax, or
5194 because of the swapping above) in the incoming set of operands. */
5195 if ((i
.imm_operands
== 2
5196 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
5197 || (t
->mnem_off
== MN_uwrmsr
&& i
.imm_operands
5198 && i
.operands
> i
.imm_operands
))
5199 swap_2_operands (0, 1);
5203 /* For USER_MSR instructions, imm32 stands for the name of an model specific
5204 register (MSR). That's an unsigned quantity, whereas all other insns with
5205 32-bit immediate and 64-bit operand size use sign-extended
5206 immediates (imm32s). Therefore these insns are special-cased, bypassing
5207 the normal handling of immediates here. */
5208 if (is_cpu(current_templates
->start
, CpuUSER_MSR
))
5210 for (j
= 0; j
< i
.operands
; j
++)
5212 if (operand_type_check(i
.types
[j
], imm
))
5213 i
.types
[j
] = smallest_imm_type (i
.op
[j
].imms
->X_add_number
);
5220 if (i
.disp_operands
&& !optimize_disp (t
))
5223 /* Next, we find a template that matches the given insn,
5224 making sure the overlap of the given operands types is consistent
5225 with the template operand types. */
5227 if (!(t
= match_template (mnem_suffix
)))
5229 const char *err_msg
;
5231 if (copy
&& !mnem_suffix
)
5236 pass1_err
= i
.error
;
5237 pass1_mnem
= insn_name (current_templates
->start
);
5241 /* If a non-/only-64bit template (group) was found in pass 1, and if
5242 _some_ template (group) was found in pass 2, squash pass 1's
5244 if (pass1_err
== unsupported_64bit
)
5250 switch (pass1_mnem
? pass1_err
: i
.error
)
5254 case operand_size_mismatch
:
5255 err_msg
= _("operand size mismatch");
5257 case operand_type_mismatch
:
5258 err_msg
= _("operand type mismatch");
5260 case register_type_mismatch
:
5261 err_msg
= _("register type mismatch");
5263 case number_of_operands_mismatch
:
5264 err_msg
= _("number of operands mismatch");
5266 case invalid_instruction_suffix
:
5267 err_msg
= _("invalid instruction suffix");
5270 err_msg
= _("constant doesn't fit in 4 bits");
5272 case unsupported_with_intel_mnemonic
:
5273 err_msg
= _("unsupported with Intel mnemonic");
5275 case unsupported_syntax
:
5276 err_msg
= _("unsupported syntax");
5279 as_bad (_("unsupported instruction `%s'"),
5280 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5282 case unsupported_on_arch
:
5283 as_bad (_("`%s' is not supported on `%s%s'"),
5284 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5285 cpu_arch_name
? cpu_arch_name
: default_arch
,
5286 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5288 case unsupported_64bit
:
5289 if (ISLOWER (mnem_suffix
))
5291 if (flag_code
== CODE_64BIT
)
5292 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5293 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5296 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5297 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5302 if (flag_code
== CODE_64BIT
)
5303 as_bad (_("`%s' is not supported in 64-bit mode"),
5304 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5306 as_bad (_("`%s' is only supported in 64-bit mode"),
5307 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5310 case invalid_sib_address
:
5311 err_msg
= _("invalid SIB address");
5313 case invalid_vsib_address
:
5314 err_msg
= _("invalid VSIB address");
5316 case invalid_vector_register_set
:
5317 err_msg
= _("mask, index, and destination registers must be distinct");
5319 case invalid_tmm_register_set
:
5320 err_msg
= _("all tmm registers must be distinct");
5322 case invalid_dest_and_src_register_set
:
5323 err_msg
= _("destination and source registers must be distinct");
5325 case unsupported_vector_index_register
:
5326 err_msg
= _("unsupported vector index register");
5328 case unsupported_broadcast
:
5329 err_msg
= _("unsupported broadcast");
5331 case broadcast_needed
:
5332 err_msg
= _("broadcast is needed for operand of such type");
5334 case unsupported_masking
:
5335 err_msg
= _("unsupported masking");
5337 case mask_not_on_destination
:
5338 err_msg
= _("mask not on destination operand");
5340 case no_default_mask
:
5341 err_msg
= _("default mask isn't allowed");
5343 case unsupported_rc_sae
:
5344 err_msg
= _("unsupported static rounding/sae");
5346 case invalid_register_operand
:
5347 err_msg
= _("invalid register operand");
5349 case internal_error
:
5350 err_msg
= _("internal error");
5353 as_bad (_("%s for `%s'"), err_msg
,
5354 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5360 if (sse_check
!= check_none
5361 /* The opcode space check isn't strictly needed; it's there only to
5362 bypass the logic below when easily possible. */
5363 && t
->opcode_space
>= SPACE_0F
5364 && t
->opcode_space
<= SPACE_0F3A
5365 && !is_cpu (&i
.tm
, CpuSSE4a
)
5366 && !is_any_vex_encoding (t
))
5370 for (j
= 0; j
< t
->operands
; ++j
)
5372 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5374 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5378 if (j
>= t
->operands
&& simd
)
5379 (sse_check
== check_warning
5381 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5384 if (i
.tm
.opcode_modifier
.fwait
)
5385 if (!add_prefix (FWAIT_OPCODE
))
5388 /* Check if REP prefix is OK. */
5389 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5391 as_bad (_("invalid instruction `%s' after `%s'"),
5392 insn_name (&i
.tm
), i
.rep_prefix
);
5396 /* Check for lock without a lockable instruction. Destination operand
5397 must be memory unless it is xchg (0x86). */
5398 if (i
.prefix
[LOCK_PREFIX
])
5400 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5401 || i
.mem_operands
== 0
5402 || (i
.tm
.base_opcode
!= 0x86
5403 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5405 as_bad (_("expecting lockable instruction after `lock'"));
5409 /* Zap the redundant prefix from XCHG when optimizing. */
5410 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5411 i
.prefix
[LOCK_PREFIX
] = 0;
5414 if (is_any_vex_encoding (&i
.tm
)
5415 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5416 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5418 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5419 if (i
.prefix
[DATA_PREFIX
])
5421 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5425 /* Don't allow e.g. KMOV in TLS code sequences. */
5426 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5429 case BFD_RELOC_386_TLS_GOTIE
:
5430 case BFD_RELOC_386_TLS_LE_32
:
5431 case BFD_RELOC_X86_64_GOTTPOFF
:
5432 case BFD_RELOC_X86_64_TLSLD
:
5433 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5440 /* Check if HLE prefix is OK. */
5441 if (i
.hle_prefix
&& !check_hle ())
5444 /* Check BND prefix. */
5445 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5446 as_bad (_("expecting valid branch instruction after `bnd'"));
5448 /* Check NOTRACK prefix. */
5449 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5450 as_bad (_("expecting indirect branch instruction after `notrack'"));
5452 if (is_cpu (&i
.tm
, CpuMPX
))
5454 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5455 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5456 else if (flag_code
!= CODE_16BIT
5457 ? i
.prefix
[ADDR_PREFIX
]
5458 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5459 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5462 /* Insert BND prefix. */
5463 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5465 if (!i
.prefix
[BND_PREFIX
])
5466 add_prefix (BND_PREFIX_OPCODE
);
5467 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5469 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5470 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5474 /* Check string instruction segment overrides. */
5475 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5477 gas_assert (i
.mem_operands
);
5478 if (!check_string ())
5480 i
.disp_operands
= 0;
5483 /* The memory operand of (%dx) should be only used with input/output
5484 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5485 if (i
.input_output_operand
5486 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5487 || i
.tm
.opcode_space
!= SPACE_BASE
))
5489 as_bad (_("input/output port address isn't allowed with `%s'"),
5494 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5495 optimize_encoding ();
5497 /* Past optimization there's no need to distinguish vex_encoding_evex and
5498 vex_encoding_evex512 anymore. */
5499 if (i
.vec_encoding
== vex_encoding_evex512
)
5500 i
.vec_encoding
= vex_encoding_evex
;
5502 if (use_unaligned_vector_move
)
5503 encode_with_unaligned_vector_move ();
5505 if (!process_suffix ())
5508 /* Check if IP-relative addressing requirements can be satisfied. */
5509 if (is_cpu (&i
.tm
, CpuPREFETCHI
)
5510 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5511 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5513 /* Update operand types and check extended states. */
5514 for (j
= 0; j
< i
.operands
; j
++)
5516 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5517 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5522 i
.xstate
|= xstate_mmx
;
5525 i
.xstate
|= xstate_mask
;
5528 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5529 i
.xstate
|= xstate_tmm
;
5530 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
5531 && !i
.tm
.opcode_modifier
.vex
5532 && vector_size
>= VSZ512
)
5533 i
.xstate
|= xstate_zmm
;
5534 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
5535 && vector_size
>= VSZ256
)
5536 i
.xstate
|= xstate_ymm
;
5537 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5538 i
.xstate
|= xstate_xmm
;
5543 /* Make still unresolved immediate matches conform to size of immediate
5544 given in i.suffix. */
5545 if (!finalize_imm ())
5548 if (i
.types
[0].bitfield
.imm1
)
5549 i
.imm_operands
= 0; /* kludge for shift insns. */
5551 /* For insns with operands there are more diddles to do to the opcode. */
5554 if (!process_operands ())
5557 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5559 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5560 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5563 if (is_any_vex_encoding (&i
.tm
))
5565 if (!cpu_arch_flags
.bitfield
.cpui286
)
5567 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5572 /* Check for explicit REX prefix. */
5573 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5575 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5579 if (i
.tm
.opcode_modifier
.vex
)
5580 build_vex_prefix (t
);
5582 build_evex_prefix ();
5584 /* The individual REX.RXBW bits got consumed. */
5585 i
.rex
&= REX_OPCODE
;
5588 /* Handle conversion of 'int $3' --> special int3 insn. */
5589 if (i
.tm
.mnem_off
== MN_int
5590 && i
.op
[0].imms
->X_add_number
== 3)
5592 i
.tm
.base_opcode
= INT3_OPCODE
;
5596 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5597 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5598 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5599 && i
.op
[0].disps
->X_op
== O_constant
)
5601 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5602 the absolute address given by the constant. Since ix86 jumps and
5603 calls are pc relative, we need to generate a reloc. */
5604 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5605 i
.op
[0].disps
->X_op
= O_symbol
;
5608 /* For 8 bit registers we need an empty rex prefix. Also if the
5609 instruction already has a prefix, we need to convert old
5610 registers to new ones. */
5612 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5613 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5614 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5615 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5616 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5617 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5622 i
.rex
|= REX_OPCODE
;
5623 for (x
= 0; x
< 2; x
++)
5625 /* Look for 8 bit operand that uses old registers. */
5626 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5627 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5629 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5630 /* In case it is "hi" register, give up. */
5631 if (i
.op
[x
].regs
->reg_num
> 3)
5632 as_bad (_("can't encode register '%s%s' in an "
5633 "instruction requiring REX prefix."),
5634 register_prefix
, i
.op
[x
].regs
->reg_name
);
5636 /* Otherwise it is equivalent to the extended register.
5637 Since the encoding doesn't change this is merely
5638 cosmetic cleanup for debug output. */
5640 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5645 if (i
.rex
== 0 && i
.rex_encoding
)
5647 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5648 that uses legacy register. If it is "hi" register, don't add
5649 the REX_OPCODE byte. */
5651 for (x
= 0; x
< 2; x
++)
5652 if (i
.types
[x
].bitfield
.class == Reg
5653 && i
.types
[x
].bitfield
.byte
5654 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5655 && i
.op
[x
].regs
->reg_num
> 3)
5657 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5658 i
.rex_encoding
= false;
5667 add_prefix (REX_OPCODE
| i
.rex
);
5669 insert_lfence_before ();
5671 /* We are ready to output the insn. */
5674 insert_lfence_after ();
5676 last_insn
.seg
= now_seg
;
5678 if (i
.tm
.opcode_modifier
.isprefix
)
5680 last_insn
.kind
= last_insn_prefix
;
5681 last_insn
.name
= insn_name (&i
.tm
);
5682 last_insn
.file
= as_where (&last_insn
.line
);
5685 last_insn
.kind
= last_insn_other
;
5688 /* The Q suffix is generally valid only in 64-bit mode, with very few
5689 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5690 and fisttp only one of their two templates is matched below: That's
5691 sufficient since other relevant attributes are the same between both
5692 respective templates. */
5693 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5695 return flag_code
== CODE_64BIT
5696 || (t
->opcode_space
== SPACE_BASE
5697 && t
->base_opcode
== 0xdf
5698 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5699 || t
->mnem_off
== MN_cmpxchg8b
;
5703 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5705 const char *l
= line
, *token_start
= l
;
5707 bool pass1
= !current_templates
;
5709 const insn_template
*t
;
5715 /* Pseudo-prefixes start with an opening figure brace. */
5716 if ((*mnem_p
= *l
) == '{')
5721 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5726 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5729 as_bad (_("no such instruction: `%s'"), token_start
);
5734 /* Pseudo-prefixes end with a closing figure brace. */
5735 if (*mnemonic
== '{' && *l
== '}')
5738 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5742 /* Point l at the closing brace if there's no other separator. */
5743 if (*l
!= END_OF_INSN
&& !is_space_char (*l
)
5744 && *l
!= PREFIX_SEPARATOR
)
5747 else if (!is_space_char (*l
)
5748 && *l
!= END_OF_INSN
5750 || (*l
!= PREFIX_SEPARATOR
&& *l
!= ',')))
5754 as_bad (_("invalid character %s in mnemonic"),
5755 output_invalid (*l
));
5758 if (token_start
== l
)
5760 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5761 as_bad (_("expecting prefix; got nothing"));
5763 as_bad (_("expecting mnemonic; got nothing"));
5767 /* Look up instruction (or prefix) via hash table. */
5768 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5770 if (*l
!= END_OF_INSN
5771 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5772 && current_templates
5773 && current_templates
->start
->opcode_modifier
.isprefix
)
5775 if (!cpu_flags_check_cpu64 (current_templates
->start
))
5777 as_bad ((flag_code
!= CODE_64BIT
5778 ? _("`%s' is only supported in 64-bit mode")
5779 : _("`%s' is not supported in 64-bit mode")),
5780 insn_name (current_templates
->start
));
5783 /* If we are in 16-bit mode, do not allow addr16 or data16.
5784 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5785 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5786 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5787 && flag_code
!= CODE_64BIT
5788 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5789 ^ (flag_code
== CODE_16BIT
)))
5791 as_bad (_("redundant %s prefix"),
5792 insn_name (current_templates
->start
));
5796 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5798 /* Handle pseudo prefixes. */
5799 switch (current_templates
->start
->extension_opcode
)
5803 i
.disp_encoding
= disp_encoding_8bit
;
5807 i
.disp_encoding
= disp_encoding_16bit
;
5811 i
.disp_encoding
= disp_encoding_32bit
;
5815 i
.dir_encoding
= dir_encoding_load
;
5819 i
.dir_encoding
= dir_encoding_store
;
5823 i
.vec_encoding
= vex_encoding_vex
;
5827 i
.vec_encoding
= vex_encoding_vex3
;
5831 i
.vec_encoding
= vex_encoding_evex
;
5835 i
.rex_encoding
= true;
5837 case Prefix_NoOptimize
:
5839 i
.no_optimize
= true;
5847 /* Add prefix, checking for repeated prefixes. */
5848 switch (add_prefix (current_templates
->start
->base_opcode
))
5853 if (is_cpu (current_templates
->start
, CpuIBT
))
5854 i
.notrack_prefix
= insn_name (current_templates
->start
);
5857 if (is_cpu (current_templates
->start
, CpuHLE
))
5858 i
.hle_prefix
= insn_name (current_templates
->start
);
5859 else if (is_cpu (current_templates
->start
, CpuMPX
))
5860 i
.bnd_prefix
= insn_name (current_templates
->start
);
5862 i
.rep_prefix
= insn_name (current_templates
->start
);
5868 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5878 if (!current_templates
)
5880 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5881 Check if we should swap operand or force 32bit displacement in
5883 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5884 i
.dir_encoding
= dir_encoding_swap
;
5885 else if (mnem_p
- 3 == dot_p
5888 i
.disp_encoding
= disp_encoding_8bit
;
5889 else if (mnem_p
- 4 == dot_p
5893 i
.disp_encoding
= disp_encoding_32bit
;
5898 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5901 if (!current_templates
|| !pass1
)
5903 current_templates
= NULL
;
5906 if (mnem_p
> mnemonic
)
5908 /* See if we can get a match by trimming off a suffix. */
5911 case WORD_MNEM_SUFFIX
:
5912 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5913 i
.suffix
= SHORT_MNEM_SUFFIX
;
5916 case BYTE_MNEM_SUFFIX
:
5917 case QWORD_MNEM_SUFFIX
:
5918 i
.suffix
= mnem_p
[-1];
5921 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5923 case SHORT_MNEM_SUFFIX
:
5924 case LONG_MNEM_SUFFIX
:
5927 i
.suffix
= mnem_p
[-1];
5930 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5938 if (intel_float_operand (mnemonic
) == 1)
5939 i
.suffix
= SHORT_MNEM_SUFFIX
;
5941 i
.suffix
= LONG_MNEM_SUFFIX
;
5944 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5946 /* For compatibility reasons accept MOVSD and CMPSD without
5947 operands even in AT&T mode. */
5948 else if (*l
== END_OF_INSN
5949 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5953 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5954 if (current_templates
!= NULL
5956 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5957 && current_templates
->start
->opcode_space
5959 && mnem_p
[-2] == 's')
5961 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5962 mnemonic
, mnemonic
);
5963 i
.suffix
= LONG_MNEM_SUFFIX
;
5967 current_templates
= NULL
;
5975 if (!current_templates
)
5978 as_bad (_("no such instruction: `%s'"), token_start
);
5983 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5984 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5986 /* Check for a branch hint. We allow ",pt" and ",pn" for
5987 predict taken and predict not taken respectively.
5988 I'm not sure that branch hints actually do anything on loop
5989 and jcxz insns (JumpByte) for current Pentium4 chips. They
5990 may work in the future and it doesn't hurt to accept them
5992 if (l
[0] == ',' && l
[1] == 'p')
5996 if (!add_prefix (DS_PREFIX_OPCODE
))
6000 else if (l
[2] == 'n')
6002 if (!add_prefix (CS_PREFIX_OPCODE
))
6008 /* Any other comma loses. */
6011 as_bad (_("invalid character %s in mnemonic"),
6012 output_invalid (*l
));
6016 /* Check if instruction is supported on specified architecture. */
6018 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
6020 supported
|= cpu_flags_match (t
);
6022 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
6023 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
6025 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
6031 if (supported
& CPU_FLAGS_64BIT_MATCH
)
6032 i
.error
= unsupported_on_arch
;
6034 i
.error
= unsupported_64bit
;
6041 parse_operands (char *l
, const char *mnemonic
)
6045 /* 1 if operand is pending after ','. */
6046 unsigned int expecting_operand
= 0;
6048 while (*l
!= END_OF_INSN
)
6050 /* Non-zero if operand parens not balanced. */
6051 unsigned int paren_not_balanced
= 0;
6052 /* True if inside double quotes. */
6053 bool in_quotes
= false;
6055 /* Skip optional white space before operand. */
6056 if (is_space_char (*l
))
6058 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
6060 as_bad (_("invalid character %s before operand %d"),
6061 output_invalid (*l
),
6065 token_start
= l
; /* After white space. */
6066 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
6068 if (*l
== END_OF_INSN
)
6072 as_bad (_("unbalanced double quotes in operand %d."),
6076 if (paren_not_balanced
)
6078 know (!intel_syntax
);
6079 as_bad (_("unbalanced parenthesis in operand %d."),
6084 break; /* we are done */
6086 else if (*l
== '\\' && l
[1] == '"')
6089 in_quotes
= !in_quotes
;
6090 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
6092 as_bad (_("invalid character %s in operand %d"),
6093 output_invalid (*l
),
6097 if (!intel_syntax
&& !in_quotes
)
6100 ++paren_not_balanced
;
6102 --paren_not_balanced
;
6106 if (l
!= token_start
)
6107 { /* Yes, we've read in another operand. */
6108 unsigned int operand_ok
;
6109 this_operand
= i
.operands
++;
6110 if (i
.operands
> MAX_OPERANDS
)
6112 as_bad (_("spurious operands; (%d operands/instruction max)"),
6116 i
.types
[this_operand
].bitfield
.unspecified
= 1;
6117 /* Now parse operand adding info to 'i' as we go along. */
6118 END_STRING_AND_SAVE (l
);
6120 if (i
.mem_operands
> 1)
6122 as_bad (_("too many memory references for `%s'"),
6129 i386_intel_operand (token_start
,
6130 intel_float_operand (mnemonic
));
6132 operand_ok
= i386_att_operand (token_start
);
6134 RESTORE_END_STRING (l
);
6140 if (expecting_operand
)
6142 expecting_operand_after_comma
:
6143 as_bad (_("expecting operand after ','; got nothing"));
6148 as_bad (_("expecting operand before ','; got nothing"));
6153 /* Now *l must be either ',' or END_OF_INSN. */
6156 if (*++l
== END_OF_INSN
)
6158 /* Just skip it, if it's \n complain. */
6159 goto expecting_operand_after_comma
;
6161 expecting_operand
= 1;
6168 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
6170 union i386_op temp_op
;
6171 i386_operand_type temp_type
;
6172 unsigned int temp_flags
;
6173 enum bfd_reloc_code_real temp_reloc
;
6175 temp_type
= i
.types
[xchg2
];
6176 i
.types
[xchg2
] = i
.types
[xchg1
];
6177 i
.types
[xchg1
] = temp_type
;
6179 temp_flags
= i
.flags
[xchg2
];
6180 i
.flags
[xchg2
] = i
.flags
[xchg1
];
6181 i
.flags
[xchg1
] = temp_flags
;
6183 temp_op
= i
.op
[xchg2
];
6184 i
.op
[xchg2
] = i
.op
[xchg1
];
6185 i
.op
[xchg1
] = temp_op
;
6187 temp_reloc
= i
.reloc
[xchg2
];
6188 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
6189 i
.reloc
[xchg1
] = temp_reloc
;
6191 temp_flags
= i
.imm_bits
[xchg2
];
6192 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
6193 i
.imm_bits
[xchg1
] = temp_flags
;
6197 if (i
.mask
.operand
== xchg1
)
6198 i
.mask
.operand
= xchg2
;
6199 else if (i
.mask
.operand
== xchg2
)
6200 i
.mask
.operand
= xchg1
;
6202 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6204 if (i
.broadcast
.operand
== xchg1
)
6205 i
.broadcast
.operand
= xchg2
;
6206 else if (i
.broadcast
.operand
== xchg2
)
6207 i
.broadcast
.operand
= xchg1
;
6212 swap_operands (void)
6218 swap_2_operands (1, i
.operands
- 2);
6222 swap_2_operands (0, i
.operands
- 1);
6228 if (i
.mem_operands
== 2)
6230 const reg_entry
*temp_seg
;
6231 temp_seg
= i
.seg
[0];
6232 i
.seg
[0] = i
.seg
[1];
6233 i
.seg
[1] = temp_seg
;
6237 /* Try to ensure constant immediates are represented in the smallest
6242 char guess_suffix
= 0;
6246 guess_suffix
= i
.suffix
;
6247 else if (i
.reg_operands
)
6249 /* Figure out a suffix from the last register operand specified.
6250 We can't do this properly yet, i.e. excluding special register
6251 instances, but the following works for instructions with
6252 immediates. In any case, we can't set i.suffix yet. */
6253 for (op
= i
.operands
; --op
>= 0;)
6254 if (i
.types
[op
].bitfield
.class != Reg
)
6256 else if (i
.types
[op
].bitfield
.byte
)
6258 guess_suffix
= BYTE_MNEM_SUFFIX
;
6261 else if (i
.types
[op
].bitfield
.word
)
6263 guess_suffix
= WORD_MNEM_SUFFIX
;
6266 else if (i
.types
[op
].bitfield
.dword
)
6268 guess_suffix
= LONG_MNEM_SUFFIX
;
6271 else if (i
.types
[op
].bitfield
.qword
)
6273 guess_suffix
= QWORD_MNEM_SUFFIX
;
6277 else if ((flag_code
== CODE_16BIT
)
6278 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
6279 guess_suffix
= WORD_MNEM_SUFFIX
;
6280 else if (flag_code
!= CODE_64BIT
6281 || (!(i
.prefix
[REX_PREFIX
] & REX_W
)
6282 /* A more generic (but also more involved) way of dealing
6283 with the special case(s) would be to go look for
6284 DefaultSize attributes on any of the templates. */
6285 && current_templates
->start
->mnem_off
!= MN_push
))
6286 guess_suffix
= LONG_MNEM_SUFFIX
;
6288 for (op
= i
.operands
; --op
>= 0;)
6289 if (operand_type_check (i
.types
[op
], imm
))
6291 switch (i
.op
[op
].imms
->X_op
)
6294 /* If a suffix is given, this operand may be shortened. */
6295 switch (guess_suffix
)
6297 case LONG_MNEM_SUFFIX
:
6298 i
.types
[op
].bitfield
.imm32
= 1;
6299 i
.types
[op
].bitfield
.imm64
= 1;
6301 case WORD_MNEM_SUFFIX
:
6302 i
.types
[op
].bitfield
.imm16
= 1;
6303 i
.types
[op
].bitfield
.imm32
= 1;
6304 i
.types
[op
].bitfield
.imm32s
= 1;
6305 i
.types
[op
].bitfield
.imm64
= 1;
6307 case BYTE_MNEM_SUFFIX
:
6308 i
.types
[op
].bitfield
.imm8
= 1;
6309 i
.types
[op
].bitfield
.imm8s
= 1;
6310 i
.types
[op
].bitfield
.imm16
= 1;
6311 i
.types
[op
].bitfield
.imm32
= 1;
6312 i
.types
[op
].bitfield
.imm32s
= 1;
6313 i
.types
[op
].bitfield
.imm64
= 1;
6317 /* If this operand is at most 16 bits, convert it
6318 to a signed 16 bit number before trying to see
6319 whether it will fit in an even smaller size.
6320 This allows a 16-bit operand such as $0xffe0 to
6321 be recognised as within Imm8S range. */
6322 if ((i
.types
[op
].bitfield
.imm16
)
6323 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6325 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6326 ^ 0x8000) - 0x8000);
6329 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6330 if ((i
.types
[op
].bitfield
.imm32
)
6331 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6333 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6334 ^ ((offsetT
) 1 << 31))
6335 - ((offsetT
) 1 << 31));
6339 = operand_type_or (i
.types
[op
],
6340 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6342 /* We must avoid matching of Imm32 templates when 64bit
6343 only immediate is available. */
6344 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6345 i
.types
[op
].bitfield
.imm32
= 0;
6352 /* Symbols and expressions. */
6354 /* Convert symbolic operand to proper sizes for matching, but don't
6355 prevent matching a set of insns that only supports sizes other
6356 than those matching the insn suffix. */
6358 i386_operand_type mask
, allowed
;
6359 const insn_template
*t
= current_templates
->start
;
6361 operand_type_set (&mask
, 0);
6362 switch (guess_suffix
)
6364 case QWORD_MNEM_SUFFIX
:
6365 mask
.bitfield
.imm64
= 1;
6366 mask
.bitfield
.imm32s
= 1;
6368 case LONG_MNEM_SUFFIX
:
6369 mask
.bitfield
.imm32
= 1;
6371 case WORD_MNEM_SUFFIX
:
6372 mask
.bitfield
.imm16
= 1;
6374 case BYTE_MNEM_SUFFIX
:
6375 mask
.bitfield
.imm8
= 1;
6381 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6382 while (++t
< current_templates
->end
)
6384 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6385 allowed
= operand_type_and (allowed
, mask
);
6388 if (!operand_type_all_zero (&allowed
))
6389 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6396 /* Try to use the smallest displacement type too. */
6398 optimize_disp (const insn_template
*t
)
6402 if (!want_disp32 (t
)
6403 && (!t
->opcode_modifier
.jump
6404 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6406 for (op
= 0; op
< i
.operands
; ++op
)
6408 const expressionS
*exp
= i
.op
[op
].disps
;
6410 if (!operand_type_check (i
.types
[op
], disp
))
6413 if (exp
->X_op
!= O_constant
)
6416 /* Since displacement is signed extended to 64bit, don't allow
6417 disp32 if it is out of range. */
6418 if (fits_in_signed_long (exp
->X_add_number
))
6421 i
.types
[op
].bitfield
.disp32
= 0;
6422 if (i
.types
[op
].bitfield
.baseindex
)
6424 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6425 (uint64_t) exp
->X_add_number
);
6431 /* Don't optimize displacement for movabs since it only takes 64bit
6433 if (i
.disp_encoding
> disp_encoding_8bit
6434 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6437 for (op
= i
.operands
; op
-- > 0;)
6438 if (operand_type_check (i
.types
[op
], disp
))
6440 if (i
.op
[op
].disps
->X_op
== O_constant
)
6442 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6444 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6446 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6447 i
.op
[op
].disps
= NULL
;
6452 if (i
.types
[op
].bitfield
.disp16
6453 && fits_in_unsigned_word (op_disp
))
6455 /* If this operand is at most 16 bits, convert
6456 to a signed 16 bit number and don't use 64bit
6458 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6459 i
.types
[op
].bitfield
.disp64
= 0;
6463 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6464 if ((flag_code
!= CODE_64BIT
6465 ? i
.types
[op
].bitfield
.disp32
6467 && (!t
->opcode_modifier
.jump
6468 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6469 && fits_in_unsigned_long (op_disp
))
6471 /* If this operand is at most 32 bits, convert
6472 to a signed 32 bit number and don't use 64bit
6474 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6475 i
.types
[op
].bitfield
.disp64
= 0;
6476 i
.types
[op
].bitfield
.disp32
= 1;
6479 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6481 i
.types
[op
].bitfield
.disp64
= 0;
6482 i
.types
[op
].bitfield
.disp32
= 1;
6485 if ((i
.types
[op
].bitfield
.disp32
6486 || i
.types
[op
].bitfield
.disp16
)
6487 && fits_in_disp8 (op_disp
))
6488 i
.types
[op
].bitfield
.disp8
= 1;
6490 i
.op
[op
].disps
->X_add_number
= op_disp
;
6492 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6493 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6495 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6496 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6497 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6500 /* We only support 64bit displacement on constants. */
6501 i
.types
[op
].bitfield
.disp64
= 0;
6507 /* Return 1 if there is a match in broadcast bytes between operand
6508 GIVEN and instruction template T. */
6511 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6513 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6514 && i
.types
[given
].bitfield
.byte
)
6515 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6516 && i
.types
[given
].bitfield
.word
)
6517 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6518 && i
.types
[given
].bitfield
.dword
)
6519 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6520 && i
.types
[given
].bitfield
.qword
));
6523 /* Check if operands are valid for the instruction. */
6526 check_VecOperands (const insn_template
*t
)
6531 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6532 any one operand are implicity requiring AVX512VL support if the actual
6533 operand size is YMMword or XMMword. Since this function runs after
6534 template matching, there's no need to check for YMMword/XMMword in
6536 cpu
= cpu_flags_and (cpu_flags_from_attr (t
->cpu
), avx512
);
6537 if (!cpu_flags_all_zero (&cpu
)
6538 && !is_cpu (t
, CpuAVX512VL
)
6539 && !cpu_arch_flags
.bitfield
.cpuavx512vl
6540 && (!t
->opcode_modifier
.vex
|| need_evex_encoding ()))
6542 for (op
= 0; op
< t
->operands
; ++op
)
6544 if (t
->operand_types
[op
].bitfield
.zmmword
6545 && (i
.types
[op
].bitfield
.ymmword
6546 || i
.types
[op
].bitfield
.xmmword
))
6548 i
.error
= unsupported
;
6554 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6555 requiring AVX2 support if the actual operand size is YMMword. */
6556 if (maybe_cpu (t
, CpuAVX
) && maybe_cpu (t
, CpuAVX2
)
6557 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6559 for (op
= 0; op
< t
->operands
; ++op
)
6561 if (t
->operand_types
[op
].bitfield
.xmmword
6562 && i
.types
[op
].bitfield
.ymmword
)
6564 i
.error
= unsupported
;
6570 /* Without VSIB byte, we can't have a vector register for index. */
6571 if (!t
->opcode_modifier
.sib
6573 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6574 || i
.index_reg
->reg_type
.bitfield
.ymmword
6575 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6577 i
.error
= unsupported_vector_index_register
;
6581 /* Check if default mask is allowed. */
6582 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6583 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6585 i
.error
= no_default_mask
;
6589 /* For VSIB byte, we need a vector register for index, and all vector
6590 registers must be distinct. */
6591 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6594 || !((t
->opcode_modifier
.sib
== VECSIB128
6595 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6596 || (t
->opcode_modifier
.sib
== VECSIB256
6597 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6598 || (t
->opcode_modifier
.sib
== VECSIB512
6599 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6601 i
.error
= invalid_vsib_address
;
6605 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6606 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6608 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6609 gas_assert (i
.types
[0].bitfield
.xmmword
6610 || i
.types
[0].bitfield
.ymmword
);
6611 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6612 gas_assert (i
.types
[2].bitfield
.xmmword
6613 || i
.types
[2].bitfield
.ymmword
);
6614 if (operand_check
== check_none
)
6616 if (register_number (i
.op
[0].regs
)
6617 != register_number (i
.index_reg
)
6618 && register_number (i
.op
[2].regs
)
6619 != register_number (i
.index_reg
)
6620 && register_number (i
.op
[0].regs
)
6621 != register_number (i
.op
[2].regs
))
6623 if (operand_check
== check_error
)
6625 i
.error
= invalid_vector_register_set
;
6628 as_warn (_("mask, index, and destination registers should be distinct"));
6630 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6632 if (i
.types
[1].bitfield
.class == RegSIMD
6633 && (i
.types
[1].bitfield
.xmmword
6634 || i
.types
[1].bitfield
.ymmword
6635 || i
.types
[1].bitfield
.zmmword
)
6636 && (register_number (i
.op
[1].regs
)
6637 == register_number (i
.index_reg
)))
6639 if (operand_check
== check_error
)
6641 i
.error
= invalid_vector_register_set
;
6644 if (operand_check
!= check_none
)
6645 as_warn (_("index and destination registers should be distinct"));
6650 /* For AMX instructions with 3 TMM register operands, all operands
6651 must be distinct. */
6652 if (i
.reg_operands
== 3
6653 && t
->operand_types
[0].bitfield
.tmmword
6654 && (i
.op
[0].regs
== i
.op
[1].regs
6655 || i
.op
[0].regs
== i
.op
[2].regs
6656 || i
.op
[1].regs
== i
.op
[2].regs
))
6658 i
.error
= invalid_tmm_register_set
;
6662 /* For some special instructions require that destination must be distinct
6663 from source registers. */
6664 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6666 unsigned int dest_reg
= i
.operands
- 1;
6668 know (i
.operands
>= 3);
6670 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6671 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6672 || (i
.reg_operands
> 2
6673 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6675 i
.error
= invalid_dest_and_src_register_set
;
6680 /* Check if broadcast is supported by the instruction and is applied
6681 to the memory operand. */
6682 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6684 i386_operand_type type
, overlap
;
6686 /* Check if specified broadcast is supported in this instruction,
6687 and its broadcast bytes match the memory operand. */
6688 op
= i
.broadcast
.operand
;
6689 if (!t
->opcode_modifier
.broadcast
6690 || !(i
.flags
[op
] & Operand_Mem
)
6691 || (!i
.types
[op
].bitfield
.unspecified
6692 && !match_broadcast_size (t
, op
)))
6695 i
.error
= unsupported_broadcast
;
6699 operand_type_set (&type
, 0);
6700 switch (get_broadcast_bytes (t
, false))
6703 type
.bitfield
.word
= 1;
6706 type
.bitfield
.dword
= 1;
6709 type
.bitfield
.qword
= 1;
6712 type
.bitfield
.xmmword
= 1;
6715 if (vector_size
< VSZ256
)
6717 type
.bitfield
.ymmword
= 1;
6720 if (vector_size
< VSZ512
)
6722 type
.bitfield
.zmmword
= 1;
6728 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6729 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6730 && t
->operand_types
[op
].bitfield
.byte
6731 + t
->operand_types
[op
].bitfield
.word
6732 + t
->operand_types
[op
].bitfield
.dword
6733 + t
->operand_types
[op
].bitfield
.qword
> 1)
6735 overlap
.bitfield
.xmmword
= 0;
6736 overlap
.bitfield
.ymmword
= 0;
6737 overlap
.bitfield
.zmmword
= 0;
6739 if (operand_type_all_zero (&overlap
))
6742 if (t
->opcode_modifier
.checkoperandsize
)
6746 type
.bitfield
.baseindex
= 1;
6747 for (j
= 0; j
< i
.operands
; ++j
)
6750 && !operand_type_register_match(i
.types
[j
],
6751 t
->operand_types
[j
],
6753 t
->operand_types
[op
]))
6758 /* If broadcast is supported in this instruction, we need to check if
6759 operand of one-element size isn't specified without broadcast. */
6760 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6762 /* Find memory operand. */
6763 for (op
= 0; op
< i
.operands
; op
++)
6764 if (i
.flags
[op
] & Operand_Mem
)
6766 gas_assert (op
< i
.operands
);
6767 /* Check size of the memory operand. */
6768 if (match_broadcast_size (t
, op
))
6770 i
.error
= broadcast_needed
;
6775 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6777 /* Check if requested masking is supported. */
6780 if (!t
->opcode_modifier
.masking
)
6782 i
.error
= unsupported_masking
;
6786 /* Common rules for masking:
6787 - mask register destinations permit only zeroing-masking, without
6788 that actually being expressed by a {z} operand suffix or EVEX.z,
6789 - memory destinations allow only merging-masking,
6790 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
6793 && (t
->operand_types
[t
->operands
- 1].bitfield
.class == RegMask
6794 || (i
.flags
[t
->operands
- 1] & Operand_Mem
)
6795 || t
->opcode_modifier
.sib
))
6797 i
.error
= unsupported_masking
;
6802 /* Check if masking is applied to dest operand. */
6803 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6805 i
.error
= mask_not_on_destination
;
6810 if (i
.rounding
.type
!= rc_none
)
6812 if (!t
->opcode_modifier
.sae
6813 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6816 i
.error
= unsupported_rc_sae
;
6820 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6822 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6824 for (op
= 0; op
< t
->operands
; ++op
)
6825 if (i
.types
[op
].bitfield
.zmmword
)
6827 if (op
>= t
->operands
)
6829 i
.error
= operand_size_mismatch
;
6835 /* Check the special Imm4 cases; must be the first operand. */
6836 if (is_cpu (t
, CpuXOP
) && t
->operands
== 5)
6838 if (i
.op
[0].imms
->X_op
!= O_constant
6839 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6845 /* Turn off Imm<N> so that update_imm won't complain. */
6846 operand_type_set (&i
.types
[0], 0);
6849 /* Check vector Disp8 operand. */
6850 if (t
->opcode_modifier
.disp8memshift
6851 && (!t
->opcode_modifier
.vex
6852 || need_evex_encoding ())
6853 && i
.disp_encoding
<= disp_encoding_8bit
)
6855 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6856 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6857 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6858 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6861 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6864 for (op
= 0; op
< i
.operands
; op
++)
6865 if (i
.flags
[op
] & Operand_Mem
)
6867 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6868 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6869 else if (t
->operand_types
[op
].bitfield
.xmmword
6870 + t
->operand_types
[op
].bitfield
.ymmword
6871 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6872 type
= &t
->operand_types
[op
];
6873 else if (!i
.types
[op
].bitfield
.unspecified
)
6874 type
= &i
.types
[op
];
6875 else /* Ambiguities get resolved elsewhere. */
6876 fallback
= &t
->operand_types
[op
];
6878 else if (i
.types
[op
].bitfield
.class == RegSIMD
6879 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6881 if (i
.types
[op
].bitfield
.zmmword
)
6883 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6885 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6889 if (!type
&& !i
.memshift
)
6893 if (type
->bitfield
.zmmword
)
6895 else if (type
->bitfield
.ymmword
)
6897 else if (type
->bitfield
.xmmword
)
6901 /* For the check in fits_in_disp8(). */
6902 if (i
.memshift
== 0)
6906 for (op
= 0; op
< i
.operands
; op
++)
6907 if (operand_type_check (i
.types
[op
], disp
)
6908 && i
.op
[op
].disps
->X_op
== O_constant
)
6910 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6912 i
.types
[op
].bitfield
.disp8
= 1;
6915 i
.types
[op
].bitfield
.disp8
= 0;
6924 /* Check if encoding requirements are met by the instruction. */
6927 VEX_check_encoding (const insn_template
*t
)
6929 if (i
.vec_encoding
== vex_encoding_error
)
6931 i
.error
= unsupported
;
6935 /* Vector size restrictions. */
6936 if ((vector_size
< VSZ512
6937 && (t
->opcode_modifier
.evex
== EVEX512
6938 || t
->opcode_modifier
.vsz
>= VSZ512
))
6939 || (vector_size
< VSZ256
6940 && (t
->opcode_modifier
.evex
== EVEX256
6941 || t
->opcode_modifier
.vex
== VEX256
6942 || t
->opcode_modifier
.vsz
>= VSZ256
)))
6944 i
.error
= unsupported
;
6948 if (i
.vec_encoding
== vex_encoding_evex
6949 || i
.vec_encoding
== vex_encoding_evex512
)
6951 /* This instruction must be encoded with EVEX prefix. */
6952 if (!t
->opcode_modifier
.evex
)
6954 i
.error
= unsupported
;
6960 if (!t
->opcode_modifier
.vex
)
6962 /* This instruction template doesn't have VEX prefix. */
6963 if (i
.vec_encoding
!= vex_encoding_default
)
6965 i
.error
= unsupported
;
6974 /* Helper function for the progress() macro in match_template(). */
6975 static INLINE
enum i386_error
progress (enum i386_error
new,
6976 enum i386_error last
,
6977 unsigned int line
, unsigned int *line_p
)
6979 if (line
<= *line_p
)
6985 static const insn_template
*
6986 match_template (char mnem_suffix
)
6988 /* Points to template once we've found it. */
6989 const insn_template
*t
;
6990 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6991 i386_operand_type overlap4
;
6992 unsigned int found_reverse_match
;
6993 i386_operand_type operand_types
[MAX_OPERANDS
];
6994 int addr_prefix_disp
;
6995 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
6996 enum i386_error specific_error
= number_of_operands_mismatch
;
6997 #define progress(err) progress (err, specific_error, __LINE__, &errline)
6999 #if MAX_OPERANDS != 5
7000 # error "MAX_OPERANDS must be 5."
7003 found_reverse_match
= 0;
7004 addr_prefix_disp
= -1;
7006 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
7008 addr_prefix_disp
= -1;
7009 found_reverse_match
= 0;
7011 /* Must have right number of operands. */
7012 if (i
.operands
!= t
->operands
)
7015 /* Check processor support. */
7016 specific_error
= progress (unsupported
);
7017 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
7020 /* Check AT&T mnemonic. */
7021 specific_error
= progress (unsupported_with_intel_mnemonic
);
7022 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
7025 /* Check AT&T/Intel syntax. */
7026 specific_error
= progress (unsupported_syntax
);
7027 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
7028 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
7031 /* Check Intel64/AMD64 ISA. */
7035 /* Default: Don't accept Intel64. */
7036 if (t
->opcode_modifier
.isa64
== INTEL64
)
7040 /* -mamd64: Don't accept Intel64 and Intel64 only. */
7041 if (t
->opcode_modifier
.isa64
>= INTEL64
)
7045 /* -mintel64: Don't accept AMD64. */
7046 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
7051 /* Check the suffix. */
7052 specific_error
= progress (invalid_instruction_suffix
);
7053 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
7054 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
7055 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
7056 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
7057 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
7060 specific_error
= progress (operand_size_mismatch
);
7061 size_match
= operand_size_match (t
);
7065 /* This is intentionally not
7067 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
7069 as the case of a missing * on the operand is accepted (perhaps with
7070 a warning, issued further down). */
7071 specific_error
= progress (operand_type_mismatch
);
7072 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
7075 /* In Intel syntax, normally we can check for memory operand size when
7076 there is no mnemonic suffix. But jmp and call have 2 different
7077 encodings with Dword memory operand size. Skip the "near" one
7078 (permitting a register operand) when "far" was requested. */
7080 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
7081 && t
->operand_types
[0].bitfield
.class == Reg
)
7084 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7085 operand_types
[j
] = t
->operand_types
[j
];
7087 /* In general, don't allow 32-bit operands on pre-386. */
7088 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
7089 : operand_size_mismatch
);
7090 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
7091 if (i
.suffix
== LONG_MNEM_SUFFIX
7092 && !cpu_arch_flags
.bitfield
.cpui386
7094 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
7095 && !intel_float_operand (insn_name (t
)))
7096 : intel_float_operand (insn_name (t
)) != 2)
7097 && (t
->operands
== i
.imm_operands
7098 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
7099 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
7100 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
7101 || (operand_types
[j
].bitfield
.class != RegMMX
7102 && operand_types
[j
].bitfield
.class != RegSIMD
7103 && operand_types
[j
].bitfield
.class != RegMask
))
7104 && !t
->opcode_modifier
.sib
)
7107 /* Do not verify operands when there are none. */
7110 if (VEX_check_encoding (t
))
7112 specific_error
= progress (i
.error
);
7116 /* We've found a match; break out of loop. */
7120 if (!t
->opcode_modifier
.jump
7121 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
7123 /* There should be only one Disp operand. */
7124 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7125 if (operand_type_check (operand_types
[j
], disp
))
7127 if (j
< MAX_OPERANDS
)
7129 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7131 addr_prefix_disp
= j
;
7133 /* Address size prefix will turn Disp64 operand into Disp32 and
7134 Disp32/Disp16 one into Disp16/Disp32 respectively. */
7138 override
= !override
;
7141 if (operand_types
[j
].bitfield
.disp32
7142 && operand_types
[j
].bitfield
.disp16
)
7144 operand_types
[j
].bitfield
.disp16
= override
;
7145 operand_types
[j
].bitfield
.disp32
= !override
;
7147 gas_assert (!operand_types
[j
].bitfield
.disp64
);
7151 if (operand_types
[j
].bitfield
.disp64
)
7153 gas_assert (!operand_types
[j
].bitfield
.disp32
);
7154 operand_types
[j
].bitfield
.disp32
= override
;
7155 operand_types
[j
].bitfield
.disp64
= !override
;
7157 operand_types
[j
].bitfield
.disp16
= 0;
7163 /* We check register size if needed. */
7164 if (t
->opcode_modifier
.checkoperandsize
)
7166 check_register
= (1 << t
->operands
) - 1;
7167 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
7168 check_register
&= ~(1 << i
.broadcast
.operand
);
7173 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
7174 switch (t
->operands
)
7177 if (!operand_type_match (overlap0
, i
.types
[0]))
7180 /* Allow the ModR/M encoding to be requested by using the {load} or
7181 {store} pseudo prefix on an applicable insn. */
7182 if (!t
->opcode_modifier
.modrm
7183 && i
.reg_operands
== 1
7184 && ((i
.dir_encoding
== dir_encoding_load
7185 && t
->mnem_off
!= MN_pop
)
7186 || (i
.dir_encoding
== dir_encoding_store
7187 && t
->mnem_off
!= MN_push
))
7189 && t
->mnem_off
!= MN_bswap
)
7194 /* xchg %eax, %eax is a special case. It is an alias for nop
7195 only in 32bit mode and we can use opcode 0x90. In 64bit
7196 mode, we can't use 0x90 for xchg %eax, %eax since it should
7197 zero-extend %eax to %rax. */
7198 if (t
->base_opcode
== 0x90
7199 && t
->opcode_space
== SPACE_BASE
)
7201 if (flag_code
== CODE_64BIT
7202 && i
.types
[0].bitfield
.instance
== Accum
7203 && i
.types
[0].bitfield
.dword
7204 && i
.types
[1].bitfield
.instance
== Accum
)
7207 /* Allow the ModR/M encoding to be requested by using the
7208 {load} or {store} pseudo prefix. */
7209 if (i
.dir_encoding
== dir_encoding_load
7210 || i
.dir_encoding
== dir_encoding_store
)
7214 if (t
->base_opcode
== MOV_AX_DISP32
7215 && t
->opcode_space
== SPACE_BASE
7216 && t
->mnem_off
!= MN_movabs
)
7218 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
7219 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
7222 /* xrelease mov %eax, <disp> is another special case. It must not
7223 match the accumulator-only encoding of mov. */
7227 /* Allow the ModR/M encoding to be requested by using a suitable
7228 {load} or {store} pseudo prefix. */
7229 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
7230 ? dir_encoding_store
7231 : dir_encoding_load
)
7232 && !i
.types
[0].bitfield
.disp64
7233 && !i
.types
[1].bitfield
.disp64
)
7237 /* Allow the ModR/M encoding to be requested by using the {load} or
7238 {store} pseudo prefix on an applicable insn. */
7239 if (!t
->opcode_modifier
.modrm
7240 && i
.reg_operands
== 1
7241 && i
.imm_operands
== 1
7242 && (i
.dir_encoding
== dir_encoding_load
7243 || i
.dir_encoding
== dir_encoding_store
)
7244 && t
->opcode_space
== SPACE_BASE
)
7246 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
7247 && i
.dir_encoding
== dir_encoding_store
)
7250 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
7251 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
7252 || i
.dir_encoding
== dir_encoding_load
))
7255 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
7256 && i
.dir_encoding
== dir_encoding_load
)
7262 if (!(size_match
& MATCH_STRAIGHT
))
7264 /* Reverse direction of operands if swapping is possible in the first
7265 place (operands need to be symmetric) and
7266 - the load form is requested, and the template is a store form,
7267 - the store form is requested, and the template is a load form,
7268 - the non-default (swapped) form is requested. */
7269 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
7270 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
7271 && !operand_type_all_zero (&overlap1
))
7272 switch (i
.dir_encoding
)
7274 case dir_encoding_load
:
7275 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7276 || t
->opcode_modifier
.regmem
)
7280 case dir_encoding_store
:
7281 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7282 && !t
->opcode_modifier
.regmem
)
7286 case dir_encoding_swap
:
7289 case dir_encoding_default
:
7292 /* If we want store form, we skip the current load. */
7293 if ((i
.dir_encoding
== dir_encoding_store
7294 || i
.dir_encoding
== dir_encoding_swap
)
7295 && i
.mem_operands
== 0
7296 && t
->opcode_modifier
.load
)
7301 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7302 if (!operand_type_match (overlap0
, i
.types
[0])
7303 || !operand_type_match (overlap1
, i
.types
[1])
7304 || ((check_register
& 3) == 3
7305 && !operand_type_register_match (i
.types
[0],
7310 specific_error
= progress (i
.error
);
7312 /* Check if other direction is valid ... */
7313 if (!t
->opcode_modifier
.d
)
7317 if (!(size_match
& MATCH_REVERSE
))
7319 /* Try reversing direction of operands. */
7320 j
= is_cpu (t
, CpuFMA4
)
7321 || is_cpu (t
, CpuXOP
) ? 1 : i
.operands
- 1;
7322 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7323 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7324 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7325 gas_assert (t
->operands
!= 3 || !check_register
);
7326 if (!operand_type_match (overlap0
, i
.types
[0])
7327 || !operand_type_match (overlap1
, i
.types
[j
])
7328 || (t
->operands
== 3
7329 && !operand_type_match (overlap2
, i
.types
[1]))
7331 && !operand_type_register_match (i
.types
[0],
7336 /* Does not match either direction. */
7337 specific_error
= progress (i
.error
);
7340 /* found_reverse_match holds which variant of D
7342 if (!t
->opcode_modifier
.d
)
7343 found_reverse_match
= 0;
7344 else if (operand_types
[0].bitfield
.tbyte
)
7346 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7347 found_reverse_match
= Opcode_FloatD
;
7349 found_reverse_match
= ~0;
7350 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7351 if ((t
->extension_opcode
& 4)
7352 && (intel_syntax
|| intel_mnemonic
))
7353 found_reverse_match
|= Opcode_FloatR
;
7355 else if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
7357 found_reverse_match
= Opcode_VexW
;
7358 goto check_operands_345
;
7360 else if (t
->opcode_space
!= SPACE_BASE
7361 && (t
->opcode_space
!= SPACE_0F
7362 /* MOV to/from CR/DR/TR, as an exception, follow
7363 the base opcode space encoding model. */
7364 || (t
->base_opcode
| 7) != 0x27))
7365 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7366 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7367 else if (!t
->opcode_modifier
.commutative
)
7368 found_reverse_match
= Opcode_D
;
7370 found_reverse_match
= ~0;
7374 /* Found a forward 2 operand match here. */
7376 switch (t
->operands
)
7379 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7380 if (!operand_type_match (overlap4
, i
.types
[4])
7381 || !operand_type_register_match (i
.types
[3],
7386 specific_error
= progress (i
.error
);
7391 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7392 if (!operand_type_match (overlap3
, i
.types
[3])
7393 || ((check_register
& 0xa) == 0xa
7394 && !operand_type_register_match (i
.types
[1],
7398 || ((check_register
& 0xc) == 0xc
7399 && !operand_type_register_match (i
.types
[2],
7404 specific_error
= progress (i
.error
);
7409 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7410 if (!operand_type_match (overlap2
, i
.types
[2])
7411 || ((check_register
& 5) == 5
7412 && !operand_type_register_match (i
.types
[0],
7416 || ((check_register
& 6) == 6
7417 && !operand_type_register_match (i
.types
[1],
7422 specific_error
= progress (i
.error
);
7428 /* Found either forward/reverse 2, 3 or 4 operand match here:
7429 slip through to break. */
7432 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7433 if (VEX_check_encoding (t
))
7435 specific_error
= progress (i
.error
);
7439 /* Check if vector operands are valid. */
7440 if (check_VecOperands (t
))
7442 specific_error
= progress (i
.error
);
7446 /* Check whether to use the shorter VEX encoding for certain insns where
7447 the EVEX enconding comes first in the table. This requires the respective
7448 AVX-* feature to be explicitly enabled. */
7449 if (t
== current_templates
->start
7450 && t
->opcode_modifier
.disp8memshift
7451 && !t
->opcode_modifier
.vex
7452 && !need_evex_encoding ()
7453 && t
+ 1 < current_templates
->end
7454 && t
[1].opcode_modifier
.vex
)
7457 unsigned int memshift
= i
.memshift
;
7460 cpu
= cpu_flags_and (cpu_flags_from_attr (t
[1].cpu
), cpu_arch_isa_flags
);
7461 if (!cpu_flags_all_zero (&cpu
)
7462 && (!i
.types
[0].bitfield
.disp8
7463 || !operand_type_check (i
.types
[0], disp
)
7464 || i
.op
[0].disps
->X_op
!= O_constant
7465 || fits_in_disp8 (i
.op
[0].disps
->X_add_number
)))
7467 specific_error
= progress (internal_error
);
7470 i
.memshift
= memshift
;
7473 /* We've found a match; break out of loop. */
7479 if (t
== current_templates
->end
)
7481 /* We found no match. */
7482 i
.error
= specific_error
;
7486 if (!quiet_warnings
)
7489 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7490 as_warn (_("indirect %s without `*'"), insn_name (t
));
7492 if (t
->opcode_modifier
.isprefix
7493 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7495 /* Warn them that a data or address size prefix doesn't
7496 affect assembly of the next line of code. */
7497 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7501 /* Copy the template we found. */
7502 install_template (t
);
7504 if (addr_prefix_disp
!= -1)
7505 i
.tm
.operand_types
[addr_prefix_disp
]
7506 = operand_types
[addr_prefix_disp
];
7508 switch (found_reverse_match
)
7514 case Opcode_FloatR
| Opcode_FloatD
:
7515 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7516 found_reverse_match
&= Opcode_FloatD
;
7520 /* If we found a reverse match we must alter the opcode direction
7521 bit and clear/flip the regmem modifier one. found_reverse_match
7522 holds bits to change (different for int & float insns). */
7524 i
.tm
.base_opcode
^= found_reverse_match
;
7526 /* Certain SIMD insns have their load forms specified in the opcode
7527 table, and hence we need to _set_ RegMem instead of clearing it.
7528 We need to avoid setting the bit though on insns like KMOVW. */
7529 i
.tm
.opcode_modifier
.regmem
7530 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7531 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7532 && !i
.tm
.opcode_modifier
.regmem
;
7536 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7537 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7541 /* Only the first two register operands need reversing, alongside
7543 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7545 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7546 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7547 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7557 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7558 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7560 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7562 as_bad (_("`%s' operand %u must use `%ses' segment"),
7564 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7569 /* There's only ever one segment override allowed per instruction.
7570 This instruction possibly has a legal segment override on the
7571 second operand, so copy the segment to where non-string
7572 instructions store it, allowing common code. */
7573 i
.seg
[op
] = i
.seg
[1];
7579 process_suffix (void)
7581 bool is_movx
= false;
7583 /* If matched instruction specifies an explicit instruction mnemonic
7585 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7586 i
.suffix
= WORD_MNEM_SUFFIX
;
7587 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7588 i
.suffix
= LONG_MNEM_SUFFIX
;
7589 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7590 i
.suffix
= QWORD_MNEM_SUFFIX
;
7591 else if (i
.reg_operands
7592 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7593 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7595 unsigned int numop
= i
.operands
;
7598 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7599 && (i
.tm
.base_opcode
| 8) == 0xbe)
7600 || (i
.tm
.opcode_space
== SPACE_BASE
7601 && i
.tm
.base_opcode
== 0x63
7602 && is_cpu (&i
.tm
, Cpu64
));
7604 /* movsx/movzx want only their source operand considered here, for the
7605 ambiguity checking below. The suffix will be replaced afterwards
7606 to represent the destination (register). */
7607 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7610 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7611 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7614 /* If there's no instruction mnemonic suffix we try to invent one
7615 based on GPR operands. */
7618 /* We take i.suffix from the last register operand specified,
7619 Destination register type is more significant than source
7620 register type. crc32 in SSE4.2 prefers source register
7622 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7625 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7626 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7628 if (i
.types
[op
].bitfield
.class != Reg
)
7630 if (i
.types
[op
].bitfield
.byte
)
7631 i
.suffix
= BYTE_MNEM_SUFFIX
;
7632 else if (i
.types
[op
].bitfield
.word
)
7633 i
.suffix
= WORD_MNEM_SUFFIX
;
7634 else if (i
.types
[op
].bitfield
.dword
)
7635 i
.suffix
= LONG_MNEM_SUFFIX
;
7636 else if (i
.types
[op
].bitfield
.qword
)
7637 i
.suffix
= QWORD_MNEM_SUFFIX
;
7643 /* As an exception, movsx/movzx silently default to a byte source
7645 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7646 i
.suffix
= BYTE_MNEM_SUFFIX
;
7648 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7650 if (!check_byte_reg ())
7653 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7655 if (!check_long_reg ())
7658 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7660 if (!check_qword_reg ())
7663 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7665 if (!check_word_reg ())
7668 else if (intel_syntax
7669 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7670 /* Do nothing if the instruction is going to ignore the prefix. */
7675 /* Undo the movsx/movzx change done above. */
7678 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7681 i
.suffix
= stackop_size
;
7682 if (stackop_size
== LONG_MNEM_SUFFIX
)
7684 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7685 .code16gcc directive to support 16-bit mode with
7686 32-bit address. For IRET without a suffix, generate
7687 16-bit IRET (opcode 0xcf) to return from an interrupt
7689 if (i
.tm
.base_opcode
== 0xcf)
7691 i
.suffix
= WORD_MNEM_SUFFIX
;
7692 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7694 /* Warn about changed behavior for segment register push/pop. */
7695 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7696 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7701 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7702 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7703 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7704 || (i
.tm
.opcode_space
== SPACE_0F
7705 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7706 && i
.tm
.extension_opcode
<= 3)))
7711 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7713 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7714 || i
.tm
.opcode_modifier
.no_lsuf
)
7715 i
.suffix
= QWORD_MNEM_SUFFIX
;
7720 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7721 i
.suffix
= LONG_MNEM_SUFFIX
;
7724 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7725 i
.suffix
= WORD_MNEM_SUFFIX
;
7731 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7732 /* Also cover lret/retf/iret in 64-bit mode. */
7733 || (flag_code
== CODE_64BIT
7734 && !i
.tm
.opcode_modifier
.no_lsuf
7735 && !i
.tm
.opcode_modifier
.no_qsuf
))
7736 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7737 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7738 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7739 /* Accept FLDENV et al without suffix. */
7740 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7742 unsigned int suffixes
, evex
= 0;
7744 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7745 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7747 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7749 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7751 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7754 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7755 also suitable for AT&T syntax mode, it was requested that this be
7756 restricted to just Intel syntax. */
7757 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7758 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7762 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7764 if (vector_size
< VSZ512
)
7766 i
.tm
.operand_types
[op
].bitfield
.zmmword
= 0;
7767 if (vector_size
< VSZ256
)
7769 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7770 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7771 && i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7772 i
.tm
.opcode_modifier
.evex
= EVEX128
;
7774 else if (i
.tm
.operand_types
[op
].bitfield
.ymmword
7775 && !i
.tm
.operand_types
[op
].bitfield
.xmmword
7776 && i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7777 i
.tm
.opcode_modifier
.evex
= EVEX256
;
7779 else if (i
.tm
.opcode_modifier
.evex
7780 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7782 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7783 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7784 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7785 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7786 if (i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7787 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7790 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7791 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7792 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7795 /* Any properly sized operand disambiguates the insn. */
7796 if (i
.types
[op
].bitfield
.xmmword
7797 || i
.types
[op
].bitfield
.ymmword
7798 || i
.types
[op
].bitfield
.zmmword
)
7800 suffixes
&= ~(7 << 6);
7805 if ((i
.flags
[op
] & Operand_Mem
)
7806 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7808 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7810 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7812 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7814 if (i
.tm
.opcode_modifier
.evex
)
7820 /* Are multiple suffixes / operand sizes allowed? */
7821 if (suffixes
& (suffixes
- 1))
7824 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7825 || operand_check
== check_error
))
7827 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7830 if (operand_check
== check_error
)
7832 as_bad (_("no instruction mnemonic suffix given and "
7833 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7836 if (operand_check
== check_warning
)
7837 as_warn (_("%s; using default for `%s'"),
7839 ? _("ambiguous operand size")
7840 : _("no instruction mnemonic suffix given and "
7841 "no register operands"),
7844 if (i
.tm
.opcode_modifier
.floatmf
)
7845 i
.suffix
= SHORT_MNEM_SUFFIX
;
7847 /* handled below */;
7849 i
.tm
.opcode_modifier
.evex
= evex
;
7850 else if (flag_code
== CODE_16BIT
)
7851 i
.suffix
= WORD_MNEM_SUFFIX
;
7852 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7853 i
.suffix
= LONG_MNEM_SUFFIX
;
7855 i
.suffix
= QWORD_MNEM_SUFFIX
;
7861 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7862 In AT&T syntax, if there is no suffix (warned about above), the default
7863 will be byte extension. */
7864 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7865 i
.tm
.base_opcode
|= 1;
7867 /* For further processing, the suffix should represent the destination
7868 (register). This is already the case when one was used with
7869 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7870 no suffix to begin with. */
7871 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7873 if (i
.types
[1].bitfield
.word
)
7874 i
.suffix
= WORD_MNEM_SUFFIX
;
7875 else if (i
.types
[1].bitfield
.qword
)
7876 i
.suffix
= QWORD_MNEM_SUFFIX
;
7878 i
.suffix
= LONG_MNEM_SUFFIX
;
7880 i
.tm
.opcode_modifier
.w
= 0;
7884 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7885 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7886 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7888 /* Change the opcode based on the operand size given by i.suffix. */
7891 /* Size floating point instruction. */
7892 case LONG_MNEM_SUFFIX
:
7893 if (i
.tm
.opcode_modifier
.floatmf
)
7895 i
.tm
.base_opcode
^= 4;
7899 case WORD_MNEM_SUFFIX
:
7900 case QWORD_MNEM_SUFFIX
:
7901 /* It's not a byte, select word/dword operation. */
7902 if (i
.tm
.opcode_modifier
.w
)
7905 i
.tm
.base_opcode
|= 8;
7907 i
.tm
.base_opcode
|= 1;
7910 case SHORT_MNEM_SUFFIX
:
7911 /* Now select between word & dword operations via the operand
7912 size prefix, except for instructions that will ignore this
7914 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7915 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7916 && !i
.tm
.opcode_modifier
.floatmf
7917 && !is_any_vex_encoding (&i
.tm
)
7918 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7919 || (flag_code
== CODE_64BIT
7920 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7922 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7924 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7925 prefix
= ADDR_PREFIX_OPCODE
;
7927 if (!add_prefix (prefix
))
7931 /* Set mode64 for an operand. */
7932 if (i
.suffix
== QWORD_MNEM_SUFFIX
7933 && flag_code
== CODE_64BIT
7934 && !i
.tm
.opcode_modifier
.norex64
7935 && !i
.tm
.opcode_modifier
.vexw
7936 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7938 && ! (i
.operands
== 2
7939 && i
.tm
.base_opcode
== 0x90
7940 && i
.tm
.opcode_space
== SPACE_BASE
7941 && i
.types
[0].bitfield
.instance
== Accum
7942 && i
.types
[0].bitfield
.qword
7943 && i
.types
[1].bitfield
.instance
== Accum
))
7949 /* Select word/dword/qword operation with explicit data sizing prefix
7950 when there are no suitable register operands. */
7951 if (i
.tm
.opcode_modifier
.w
7952 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7954 || (i
.reg_operands
== 1
7956 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7958 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7959 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7960 || i
.tm
.mnem_off
== MN_crc32
))))
7961 i
.tm
.base_opcode
|= 1;
7965 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7967 gas_assert (!i
.suffix
);
7968 gas_assert (i
.reg_operands
);
7970 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7973 /* The address size override prefix changes the size of the
7975 if (flag_code
== CODE_64BIT
7976 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7978 as_bad (_("16-bit addressing unavailable for `%s'"),
7983 if ((flag_code
== CODE_32BIT
7984 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7985 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7986 && !add_prefix (ADDR_PREFIX_OPCODE
))
7991 /* Check invalid register operand when the address size override
7992 prefix changes the size of register operands. */
7994 enum { need_word
, need_dword
, need_qword
} need
;
7996 /* Check the register operand for the address size prefix if
7997 the memory operand has no real registers, like symbol, DISP
7998 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7999 if (i
.mem_operands
== 1
8000 && i
.reg_operands
== 1
8002 && i
.types
[1].bitfield
.class == Reg
8003 && (flag_code
== CODE_32BIT
8004 ? i
.op
[1].regs
->reg_type
.bitfield
.word
8005 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
8006 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
8007 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8008 || (x86_elf_abi
== X86_64_X32_ABI
8010 && i
.base_reg
->reg_num
== RegIP
8011 && i
.base_reg
->reg_type
.bitfield
.qword
))
8015 && !add_prefix (ADDR_PREFIX_OPCODE
))
8018 if (flag_code
== CODE_32BIT
)
8019 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
8020 else if (i
.prefix
[ADDR_PREFIX
])
8023 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
8025 for (op
= 0; op
< i
.operands
; op
++)
8027 if (i
.types
[op
].bitfield
.class != Reg
)
8033 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
8037 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
8041 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
8046 as_bad (_("invalid register operand size for `%s'"),
8057 check_byte_reg (void)
8061 for (op
= i
.operands
; --op
>= 0;)
8063 /* Skip non-register operands. */
8064 if (i
.types
[op
].bitfield
.class != Reg
)
8067 /* If this is an eight bit register, it's OK. If it's the 16 or
8068 32 bit version of an eight bit register, we will just use the
8069 low portion, and that's OK too. */
8070 if (i
.types
[op
].bitfield
.byte
)
8073 /* I/O port address operands are OK too. */
8074 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
8075 && i
.tm
.operand_types
[op
].bitfield
.word
)
8078 /* crc32 only wants its source operand checked here. */
8079 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
8082 /* Any other register is bad. */
8083 as_bad (_("`%s%s' not allowed with `%s%c'"),
8084 register_prefix
, i
.op
[op
].regs
->reg_name
,
8085 insn_name (&i
.tm
), i
.suffix
);
8092 check_long_reg (void)
8096 for (op
= i
.operands
; --op
>= 0;)
8097 /* Skip non-register operands. */
8098 if (i
.types
[op
].bitfield
.class != Reg
)
8100 /* Reject eight bit registers, except where the template requires
8101 them. (eg. movzb) */
8102 else if (i
.types
[op
].bitfield
.byte
8103 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8104 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8105 && (i
.tm
.operand_types
[op
].bitfield
.word
8106 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8108 as_bad (_("`%s%s' not allowed with `%s%c'"),
8110 i
.op
[op
].regs
->reg_name
,
8115 /* Error if the e prefix on a general reg is missing. */
8116 else if (i
.types
[op
].bitfield
.word
8117 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8118 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8119 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8121 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8122 register_prefix
, i
.op
[op
].regs
->reg_name
,
8126 /* Warn if the r prefix on a general reg is present. */
8127 else if (i
.types
[op
].bitfield
.qword
8128 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8129 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8130 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8132 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8133 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8140 check_qword_reg (void)
8144 for (op
= i
.operands
; --op
>= 0; )
8145 /* Skip non-register operands. */
8146 if (i
.types
[op
].bitfield
.class != Reg
)
8148 /* Reject eight bit registers, except where the template requires
8149 them. (eg. movzb) */
8150 else if (i
.types
[op
].bitfield
.byte
8151 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8152 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8153 && (i
.tm
.operand_types
[op
].bitfield
.word
8154 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8156 as_bad (_("`%s%s' not allowed with `%s%c'"),
8158 i
.op
[op
].regs
->reg_name
,
8163 /* Warn if the r prefix on a general reg is missing. */
8164 else if ((i
.types
[op
].bitfield
.word
8165 || i
.types
[op
].bitfield
.dword
)
8166 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8167 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8168 && i
.tm
.operand_types
[op
].bitfield
.qword
)
8170 /* Prohibit these changes in the 64bit mode, since the
8171 lowering is more complicated. */
8172 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8173 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8180 check_word_reg (void)
8183 for (op
= i
.operands
; --op
>= 0;)
8184 /* Skip non-register operands. */
8185 if (i
.types
[op
].bitfield
.class != Reg
)
8187 /* Reject eight bit registers, except where the template requires
8188 them. (eg. movzb) */
8189 else if (i
.types
[op
].bitfield
.byte
8190 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8191 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8192 && (i
.tm
.operand_types
[op
].bitfield
.word
8193 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8195 as_bad (_("`%s%s' not allowed with `%s%c'"),
8197 i
.op
[op
].regs
->reg_name
,
8202 /* Error if the e or r prefix on a general reg is present. */
8203 else if ((i
.types
[op
].bitfield
.dword
8204 || i
.types
[op
].bitfield
.qword
)
8205 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8206 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8207 && i
.tm
.operand_types
[op
].bitfield
.word
)
8209 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8210 register_prefix
, i
.op
[op
].regs
->reg_name
,
8218 update_imm (unsigned int j
)
8220 i386_operand_type overlap
= i
.types
[j
];
8222 if (i
.tm
.operand_types
[j
].bitfield
.imm8
8223 && i
.tm
.operand_types
[j
].bitfield
.imm8s
8224 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
8226 /* This combination is used on 8-bit immediates where e.g. $~0 is
8227 desirable to permit. We're past operand type matching, so simply
8228 put things back in the shape they were before introducing the
8229 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
8230 overlap
.bitfield
.imm8s
= 0;
8233 if (overlap
.bitfield
.imm8
8234 + overlap
.bitfield
.imm8s
8235 + overlap
.bitfield
.imm16
8236 + overlap
.bitfield
.imm32
8237 + overlap
.bitfield
.imm32s
8238 + overlap
.bitfield
.imm64
> 1)
8240 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
8241 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
8242 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
8243 static const i386_operand_type imm16_32
= { .bitfield
=
8244 { .imm16
= 1, .imm32
= 1 }
8246 static const i386_operand_type imm16_32s
= { .bitfield
=
8247 { .imm16
= 1, .imm32s
= 1 }
8249 static const i386_operand_type imm16_32_32s
= { .bitfield
=
8250 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
8255 i386_operand_type temp
;
8257 operand_type_set (&temp
, 0);
8258 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
8260 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
8261 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
8263 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
8264 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
8265 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
8267 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
8268 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
8271 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
8274 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
8275 || operand_type_equal (&overlap
, &imm16_32
)
8276 || operand_type_equal (&overlap
, &imm16_32s
))
8278 if ((flag_code
== CODE_16BIT
)
8279 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
8284 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
8285 overlap
= operand_type_and (overlap
, imm32s
);
8286 else if (i
.prefix
[DATA_PREFIX
])
8287 overlap
= operand_type_and (overlap
,
8288 flag_code
!= CODE_16BIT
? imm16
: imm32
);
8289 if (overlap
.bitfield
.imm8
8290 + overlap
.bitfield
.imm8s
8291 + overlap
.bitfield
.imm16
8292 + overlap
.bitfield
.imm32
8293 + overlap
.bitfield
.imm32s
8294 + overlap
.bitfield
.imm64
!= 1)
8296 as_bad (_("no instruction mnemonic suffix given; "
8297 "can't determine immediate size"));
8301 i
.types
[j
] = overlap
;
8311 /* Update the first 2 immediate operands. */
8312 n
= i
.operands
> 2 ? 2 : i
.operands
;
8315 for (j
= 0; j
< n
; j
++)
8316 if (update_imm (j
) == 0)
8319 /* The 3rd operand can't be immediate operand. */
8320 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
8326 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8329 if (r
->reg_flags
& RegRex
)
8331 if (i
.rex
& rex_bit
)
8332 as_bad (_("same type of prefix used twice"));
8335 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8337 gas_assert (i
.vex
.register_specifier
== r
);
8338 i
.vex
.register_specifier
+= 8;
8341 if (r
->reg_flags
& RegVRex
)
8346 process_operands (void)
8348 /* Default segment register this instruction will use for memory
8349 accesses. 0 means unknown. This is only for optimizing out
8350 unnecessary segment overrides. */
8351 const reg_entry
*default_seg
= NULL
;
8353 /* We only need to check those implicit registers for instructions
8354 with 3 operands or less. */
8355 if (i
.operands
<= 3)
8356 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8357 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8360 if (i
.tm
.opcode_modifier
.sse2avx
)
8362 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8364 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8365 i
.prefix
[REX_PREFIX
] = 0;
8368 /* ImmExt should be processed after SSE2AVX. */
8369 else if (i
.tm
.opcode_modifier
.immext
)
8372 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8373 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8374 new destination operand here, while converting the source one to register
8376 if (i
.tm
.mnem_off
== MN_tilezero
)
8378 i
.op
[1].regs
= i
.op
[0].regs
;
8379 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8380 i
.types
[1] = i
.types
[0];
8381 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8382 i
.flags
[1] = i
.flags
[0];
8388 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8390 static const i386_operand_type regxmm
= {
8391 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8393 unsigned int dupl
= i
.operands
;
8394 unsigned int dest
= dupl
- 1;
8397 /* The destination must be an xmm register. */
8398 gas_assert (i
.reg_operands
8399 && MAX_OPERANDS
> dupl
8400 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8402 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8403 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8405 /* Keep xmm0 for instructions with VEX prefix and 3
8407 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8408 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8413 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8415 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8417 /* Add the implicit xmm0 for instructions with VEX prefix
8419 for (j
= i
.operands
; j
> 0; j
--)
8421 i
.op
[j
] = i
.op
[j
- 1];
8422 i
.types
[j
] = i
.types
[j
- 1];
8423 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8424 i
.flags
[j
] = i
.flags
[j
- 1];
8427 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8428 i
.types
[0] = regxmm
;
8429 i
.tm
.operand_types
[0] = regxmm
;
8432 i
.reg_operands
+= 2;
8437 i
.op
[dupl
] = i
.op
[dest
];
8438 i
.types
[dupl
] = i
.types
[dest
];
8439 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8440 i
.flags
[dupl
] = i
.flags
[dest
];
8449 i
.op
[dupl
] = i
.op
[dest
];
8450 i
.types
[dupl
] = i
.types
[dest
];
8451 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8452 i
.flags
[dupl
] = i
.flags
[dest
];
8455 if (i
.tm
.opcode_modifier
.immext
)
8458 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8459 && i
.tm
.opcode_modifier
.modrm
)
8463 for (j
= 1; j
< i
.operands
; j
++)
8465 i
.op
[j
- 1] = i
.op
[j
];
8466 i
.types
[j
- 1] = i
.types
[j
];
8468 /* We need to adjust fields in i.tm since they are used by
8469 build_modrm_byte. */
8470 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8472 i
.flags
[j
- 1] = i
.flags
[j
];
8475 /* No adjustment to i.reg_operands: This was already done at the top
8480 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8482 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8484 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8485 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8486 regnum
= register_number (i
.op
[1].regs
);
8487 first_reg_in_group
= regnum
& ~3;
8488 last_reg_in_group
= first_reg_in_group
+ 3;
8489 if (regnum
!= first_reg_in_group
)
8490 as_warn (_("source register `%s%s' implicitly denotes"
8491 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8492 register_prefix
, i
.op
[1].regs
->reg_name
,
8493 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8494 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8497 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8499 /* The imul $imm, %reg instruction is converted into
8500 imul $imm, %reg, %reg, and the clr %reg instruction
8501 is converted into xor %reg, %reg. */
8503 unsigned int first_reg_op
;
8505 if (operand_type_check (i
.types
[0], reg
))
8509 /* Pretend we saw the extra register operand. */
8510 gas_assert (i
.reg_operands
== 1
8511 && i
.op
[first_reg_op
+ 1].regs
== 0);
8512 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8513 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8518 if (i
.tm
.opcode_modifier
.modrm
)
8520 /* The opcode is completed (modulo i.tm.extension_opcode which
8521 must be put into the modrm byte). Now, we make the modrm and
8522 index base bytes based on all the info we've collected. */
8524 default_seg
= build_modrm_byte ();
8526 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8528 /* Warn about some common errors, but press on regardless. */
8529 if (i
.operands
== 2)
8531 /* Reversed arguments on faddp or fmulp. */
8532 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8533 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8534 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8536 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8538 /* Extraneous `l' suffix on fp insn. */
8539 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8540 register_prefix
, i
.op
[0].regs
->reg_name
);
8544 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
8546 if (flag_code
!= CODE_64BIT
8547 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8548 && i
.op
[0].regs
->reg_num
== 1
8549 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8550 && i
.op
[0].regs
->reg_num
< 4)
8552 as_bad (_("you can't `%s %s%s'"),
8553 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8556 if (i
.op
[0].regs
->reg_num
> 3
8557 && i
.tm
.opcode_space
== SPACE_BASE
)
8559 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8560 i
.tm
.opcode_space
= SPACE_0F
;
8562 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8564 else if (i
.tm
.opcode_space
== SPACE_BASE
8565 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8567 default_seg
= reg_ds
;
8569 else if (i
.tm
.opcode_modifier
.isstring
)
8571 /* For the string instructions that allow a segment override
8572 on one of their operands, the default segment is ds. */
8573 default_seg
= reg_ds
;
8575 else if (i
.short_form
)
8577 /* The register operand is in the 1st or 2nd non-immediate operand. */
8578 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
8581 && r
->reg_type
.bitfield
.instance
== Accum
8582 && i
.op
[i
.imm_operands
+ 1].regs
)
8583 r
= i
.op
[i
.imm_operands
+ 1].regs
;
8584 /* Register goes in low 3 bits of opcode. */
8585 i
.tm
.base_opcode
|= r
->reg_num
;
8586 set_rex_vrex (r
, REX_B
, false);
8588 if (dot_insn () && i
.reg_operands
== 2)
8590 gas_assert (is_any_vex_encoding (&i
.tm
)
8591 || i
.vec_encoding
!= vex_encoding_default
);
8592 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8595 else if (i
.reg_operands
== 1
8596 && !i
.flags
[i
.operands
- 1]
8597 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
8600 gas_assert (is_any_vex_encoding (&i
.tm
)
8601 || i
.vec_encoding
!= vex_encoding_default
);
8602 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8605 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8606 && i
.tm
.mnem_off
== MN_lea
)
8608 if (!quiet_warnings
)
8609 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8610 if (optimize
&& !i
.no_optimize
)
8613 i
.prefix
[SEG_PREFIX
] = 0;
8617 /* If a segment was explicitly specified, and the specified segment
8618 is neither the default nor the one already recorded from a prefix,
8619 use an opcode prefix to select it. If we never figured out what
8620 the default segment is, then default_seg will be zero at this
8621 point, and the specified segment prefix will always be used. */
8623 && i
.seg
[0] != default_seg
8624 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8626 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8632 static const reg_entry
*
8633 build_modrm_byte (void)
8635 const reg_entry
*default_seg
= NULL
;
8636 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8637 /* Compensate for kludge in md_assemble(). */
8638 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8639 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8640 unsigned int v
, op
, reg_slot
= ~0;
8642 /* Accumulator (in particular %st), shift count (%cl), and alike need
8643 to be skipped just like immediate operands do. */
8644 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8646 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8649 for (op
= source
; op
< i
.operands
; ++op
)
8650 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8653 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8657 /* There are 2 kinds of instructions:
8658 1. 5 operands: 4 register operands or 3 register operands
8659 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8660 VexW0 or VexW1. The destination must be either XMM, YMM or
8662 2. 4 operands: 4 register operands or 3 register operands
8663 plus 1 memory operand, with VexXDS.
8664 3. Other equivalent combinations when coming from s_insn(). */
8665 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8666 && i
.tm
.opcode_modifier
.vexw
);
8667 gas_assert (dot_insn ()
8668 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8670 /* Of the first two non-immediate operands the one with the template
8671 not allowing for a memory one is encoded in the immediate operand. */
8673 reg_slot
= source
+ 1;
8675 reg_slot
= source
++;
8679 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8680 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
8683 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
8685 if (i
.imm_operands
== 0)
8687 /* When there is no immediate operand, generate an 8bit
8688 immediate operand to encode the first operand. */
8689 exp
= &im_expressions
[i
.imm_operands
++];
8690 i
.op
[i
.operands
].imms
= exp
;
8691 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8694 exp
->X_op
= O_constant
;
8698 gas_assert (i
.imm_operands
== 1);
8699 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8700 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8702 /* Turn on Imm8 again so that output_imm will generate it. */
8703 i
.types
[0].bitfield
.imm8
= 1;
8707 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
8708 << (3 + !(i
.tm
.opcode_modifier
.evex
8709 || i
.vec_encoding
== vex_encoding_evex
));
8712 for (v
= source
+ 1; v
< dest
; ++v
)
8717 if (i
.tm
.extension_opcode
!= None
)
8723 gas_assert (source
< dest
);
8724 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8727 unsigned int tmp
= source
;
8733 if (v
< MAX_OPERANDS
)
8735 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8736 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8739 if (op
< i
.operands
)
8743 unsigned int fake_zero_displacement
= 0;
8745 gas_assert (i
.flags
[op
] & Operand_Mem
);
8747 if (i
.tm
.opcode_modifier
.sib
)
8749 /* The index register of VSIB shouldn't be RegIZ. */
8750 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8751 && i
.index_reg
->reg_num
== RegIZ
)
8754 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8757 i
.sib
.base
= NO_BASE_REGISTER
;
8758 i
.sib
.scale
= i
.log2_scale_factor
;
8759 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8760 i
.types
[op
].bitfield
.disp32
= 1;
8763 /* Since the mandatory SIB always has index register, so
8764 the code logic remains unchanged. The non-mandatory SIB
8765 without index register is allowed and will be handled
8769 if (i
.index_reg
->reg_num
== RegIZ
)
8770 i
.sib
.index
= NO_INDEX_REGISTER
;
8772 i
.sib
.index
= i
.index_reg
->reg_num
;
8773 set_rex_vrex (i
.index_reg
, REX_X
, false);
8777 default_seg
= reg_ds
;
8779 if (i
.base_reg
== 0)
8782 if (!i
.disp_operands
)
8783 fake_zero_displacement
= 1;
8784 if (i
.index_reg
== 0)
8786 /* Both check for VSIB and mandatory non-vector SIB. */
8787 gas_assert (!i
.tm
.opcode_modifier
.sib
8788 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8789 /* Operand is just <disp> */
8790 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8791 if (flag_code
== CODE_64BIT
)
8793 /* 64bit mode overwrites the 32bit absolute
8794 addressing by RIP relative addressing and
8795 absolute addressing is encoded by one of the
8796 redundant SIB forms. */
8797 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8798 i
.sib
.base
= NO_BASE_REGISTER
;
8799 i
.sib
.index
= NO_INDEX_REGISTER
;
8800 i
.types
[op
].bitfield
.disp32
= 1;
8802 else if ((flag_code
== CODE_16BIT
)
8803 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8805 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8806 i
.types
[op
].bitfield
.disp16
= 1;
8810 i
.rm
.regmem
= NO_BASE_REGISTER
;
8811 i
.types
[op
].bitfield
.disp32
= 1;
8814 else if (!i
.tm
.opcode_modifier
.sib
)
8816 /* !i.base_reg && i.index_reg */
8817 if (i
.index_reg
->reg_num
== RegIZ
)
8818 i
.sib
.index
= NO_INDEX_REGISTER
;
8820 i
.sib
.index
= i
.index_reg
->reg_num
;
8821 i
.sib
.base
= NO_BASE_REGISTER
;
8822 i
.sib
.scale
= i
.log2_scale_factor
;
8823 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8824 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8825 i
.types
[op
].bitfield
.disp32
= 1;
8826 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8830 /* RIP addressing for 64bit mode. */
8831 else if (i
.base_reg
->reg_num
== RegIP
)
8833 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8834 i
.rm
.regmem
= NO_BASE_REGISTER
;
8835 i
.types
[op
].bitfield
.disp8
= 0;
8836 i
.types
[op
].bitfield
.disp16
= 0;
8837 i
.types
[op
].bitfield
.disp32
= 1;
8838 i
.types
[op
].bitfield
.disp64
= 0;
8839 i
.flags
[op
] |= Operand_PCrel
;
8840 if (! i
.disp_operands
)
8841 fake_zero_displacement
= 1;
8843 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8845 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8846 switch (i
.base_reg
->reg_num
)
8849 if (i
.index_reg
== 0)
8851 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8852 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8855 default_seg
= reg_ss
;
8856 if (i
.index_reg
== 0)
8859 if (operand_type_check (i
.types
[op
], disp
) == 0)
8861 /* fake (%bp) into 0(%bp) */
8862 if (i
.disp_encoding
== disp_encoding_16bit
)
8863 i
.types
[op
].bitfield
.disp16
= 1;
8865 i
.types
[op
].bitfield
.disp8
= 1;
8866 fake_zero_displacement
= 1;
8869 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8870 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8872 default: /* (%si) -> 4 or (%di) -> 5 */
8873 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8875 if (!fake_zero_displacement
8879 fake_zero_displacement
= 1;
8880 if (i
.disp_encoding
== disp_encoding_8bit
)
8881 i
.types
[op
].bitfield
.disp8
= 1;
8883 i
.types
[op
].bitfield
.disp16
= 1;
8885 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8887 else /* i.base_reg and 32/64 bit mode */
8889 if (operand_type_check (i
.types
[op
], disp
))
8891 i
.types
[op
].bitfield
.disp16
= 0;
8892 i
.types
[op
].bitfield
.disp64
= 0;
8893 i
.types
[op
].bitfield
.disp32
= 1;
8896 if (!i
.tm
.opcode_modifier
.sib
)
8897 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8898 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8900 i
.sib
.base
= i
.base_reg
->reg_num
;
8901 /* x86-64 ignores REX prefix bit here to avoid decoder
8903 if (!(i
.base_reg
->reg_flags
& RegRex
)
8904 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8905 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8906 default_seg
= reg_ss
;
8907 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8909 fake_zero_displacement
= 1;
8910 if (i
.disp_encoding
== disp_encoding_32bit
)
8911 i
.types
[op
].bitfield
.disp32
= 1;
8913 i
.types
[op
].bitfield
.disp8
= 1;
8915 i
.sib
.scale
= i
.log2_scale_factor
;
8916 if (i
.index_reg
== 0)
8918 /* Only check for VSIB. */
8919 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8920 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8921 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8923 /* <disp>(%esp) becomes two byte modrm with no index
8924 register. We've already stored the code for esp
8925 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8926 Any base register besides %esp will not use the
8927 extra modrm byte. */
8928 i
.sib
.index
= NO_INDEX_REGISTER
;
8930 else if (!i
.tm
.opcode_modifier
.sib
)
8932 if (i
.index_reg
->reg_num
== RegIZ
)
8933 i
.sib
.index
= NO_INDEX_REGISTER
;
8935 i
.sib
.index
= i
.index_reg
->reg_num
;
8936 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8937 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8942 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8943 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8947 if (!fake_zero_displacement
8951 fake_zero_displacement
= 1;
8952 if (i
.disp_encoding
== disp_encoding_8bit
)
8953 i
.types
[op
].bitfield
.disp8
= 1;
8955 i
.types
[op
].bitfield
.disp32
= 1;
8957 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8961 if (fake_zero_displacement
)
8963 /* Fakes a zero displacement assuming that i.types[op]
8964 holds the correct displacement size. */
8967 gas_assert (i
.op
[op
].disps
== 0);
8968 exp
= &disp_expressions
[i
.disp_operands
++];
8969 i
.op
[op
].disps
= exp
;
8970 exp
->X_op
= O_constant
;
8971 exp
->X_add_number
= 0;
8972 exp
->X_add_symbol
= (symbolS
*) 0;
8973 exp
->X_op_symbol
= (symbolS
*) 0;
8979 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8980 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
8991 if (!i
.tm
.opcode_modifier
.regmem
)
8993 gas_assert (source
< MAX_OPERANDS
);
8994 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8995 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
8996 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
9001 gas_assert (dest
< MAX_OPERANDS
);
9002 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
9003 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
9008 /* Fill in i.rm.reg field with extension opcode (if any) or the
9009 appropriate register. */
9010 if (i
.tm
.extension_opcode
!= None
)
9011 i
.rm
.reg
= i
.tm
.extension_opcode
;
9012 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
9014 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
9015 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
9019 gas_assert (source
< MAX_OPERANDS
);
9020 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
9021 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
9024 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
9026 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
9028 add_prefix (LOCK_PREFIX_OPCODE
);
9035 frag_opcode_byte (unsigned char byte
)
9037 if (now_seg
!= absolute_section
)
9038 FRAG_APPEND_1_CHAR (byte
);
9040 ++abs_section_offset
;
9044 flip_code16 (unsigned int code16
)
9046 gas_assert (i
.tm
.operands
== 1);
9048 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
9049 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
9050 : i
.tm
.operand_types
[0].bitfield
.disp16
)
9055 output_branch (void)
9061 relax_substateT subtype
;
9065 if (now_seg
== absolute_section
)
9067 as_bad (_("relaxable branches not supported in absolute section"));
9071 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
9072 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
9075 if (i
.prefix
[DATA_PREFIX
] != 0)
9079 code16
^= flip_code16(code16
);
9081 /* Pentium4 branch hints. */
9082 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9083 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9088 if (i
.prefix
[REX_PREFIX
] != 0)
9094 /* BND prefixed jump. */
9095 if (i
.prefix
[BND_PREFIX
] != 0)
9101 if (i
.prefixes
!= 0)
9102 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9104 /* It's always a symbol; End frag & setup for relax.
9105 Make sure there is enough room in this frag for the largest
9106 instruction we may generate in md_convert_frag. This is 2
9107 bytes for the opcode and room for the prefix and largest
9109 frag_grow (prefix
+ 2 + 4);
9110 /* Prefix and 1 opcode byte go in fr_fix. */
9111 p
= frag_more (prefix
+ 1);
9112 if (i
.prefix
[DATA_PREFIX
] != 0)
9113 *p
++ = DATA_PREFIX_OPCODE
;
9114 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
9115 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
9116 *p
++ = i
.prefix
[SEG_PREFIX
];
9117 if (i
.prefix
[BND_PREFIX
] != 0)
9118 *p
++ = BND_PREFIX_OPCODE
;
9119 if (i
.prefix
[REX_PREFIX
] != 0)
9120 *p
++ = i
.prefix
[REX_PREFIX
];
9121 *p
= i
.tm
.base_opcode
;
9123 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
9124 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
9125 else if (cpu_arch_flags
.bitfield
.cpui386
)
9126 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
9128 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
9131 sym
= i
.op
[0].disps
->X_add_symbol
;
9132 off
= i
.op
[0].disps
->X_add_number
;
9134 if (i
.op
[0].disps
->X_op
!= O_constant
9135 && i
.op
[0].disps
->X_op
!= O_symbol
)
9137 /* Handle complex expressions. */
9138 sym
= make_expr_symbol (i
.op
[0].disps
);
9142 /* 1 possible extra opcode + 4 byte displacement go in var part.
9143 Pass reloc in fr_var. */
9144 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
9147 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9148 /* Return TRUE iff PLT32 relocation should be used for branching to
9152 need_plt32_p (symbolS
*s
)
9154 /* PLT32 relocation is ELF only. */
9159 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
9160 krtld support it. */
9164 /* Since there is no need to prepare for PLT branch on x86-64, we
9165 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
9166 be used as a marker for 32-bit PC-relative branches. */
9173 /* Weak or undefined symbol need PLT32 relocation. */
9174 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
9177 /* Non-global symbol doesn't need PLT32 relocation. */
9178 if (! S_IS_EXTERNAL (s
))
9181 /* Other global symbols need PLT32 relocation. NB: Symbol with
9182 non-default visibilities are treated as normal global symbol
9183 so that PLT32 relocation can be used as a marker for 32-bit
9184 PC-relative branches. It is useful for linker relaxation. */
9195 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
9197 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
9199 /* This is a loop or jecxz type instruction. */
9201 if (i
.prefix
[ADDR_PREFIX
] != 0)
9203 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
9206 /* Pentium4 branch hints. */
9207 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9208 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9210 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
9219 if (flag_code
== CODE_16BIT
)
9222 if (i
.prefix
[DATA_PREFIX
] != 0)
9224 frag_opcode_byte (DATA_PREFIX_OPCODE
);
9226 code16
^= flip_code16(code16
);
9234 /* BND prefixed jump. */
9235 if (i
.prefix
[BND_PREFIX
] != 0)
9237 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
9241 if (i
.prefix
[REX_PREFIX
] != 0)
9243 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
9247 if (i
.prefixes
!= 0)
9248 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9250 if (now_seg
== absolute_section
)
9252 abs_section_offset
+= i
.opcode_length
+ size
;
9256 p
= frag_more (i
.opcode_length
+ size
);
9257 switch (i
.opcode_length
)
9260 *p
++ = i
.tm
.base_opcode
>> 8;
9263 *p
++ = i
.tm
.base_opcode
;
9269 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9270 if (flag_code
== CODE_64BIT
&& size
== 4
9271 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
9272 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
9273 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
9276 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
9278 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9279 i
.op
[0].disps
, 1, jump_reloc
);
9281 /* All jumps handled here are signed, but don't unconditionally use a
9282 signed limit check for 32 and 16 bit jumps as we want to allow wrap
9283 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
9288 fixP
->fx_signed
= 1;
9292 if (i
.tm
.mnem_off
== MN_xbegin
)
9293 fixP
->fx_signed
= 1;
9297 if (flag_code
== CODE_64BIT
)
9298 fixP
->fx_signed
= 1;
9304 output_interseg_jump (void)
9312 if (flag_code
== CODE_16BIT
)
9316 if (i
.prefix
[DATA_PREFIX
] != 0)
9323 gas_assert (!i
.prefix
[REX_PREFIX
]);
9329 if (i
.prefixes
!= 0)
9330 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9332 if (now_seg
== absolute_section
)
9334 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9338 /* 1 opcode; 2 segment; offset */
9339 p
= frag_more (prefix
+ 1 + 2 + size
);
9341 if (i
.prefix
[DATA_PREFIX
] != 0)
9342 *p
++ = DATA_PREFIX_OPCODE
;
9344 if (i
.prefix
[REX_PREFIX
] != 0)
9345 *p
++ = i
.prefix
[REX_PREFIX
];
9347 *p
++ = i
.tm
.base_opcode
;
9348 if (i
.op
[1].imms
->X_op
== O_constant
)
9350 offsetT n
= i
.op
[1].imms
->X_add_number
;
9353 && !fits_in_unsigned_word (n
)
9354 && !fits_in_signed_word (n
))
9356 as_bad (_("16-bit jump out of range"));
9359 md_number_to_chars (p
, n
, size
);
9362 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9363 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9366 if (i
.op
[0].imms
->X_op
== O_constant
)
9367 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9369 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9370 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9373 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9378 asection
*seg
= now_seg
;
9379 subsegT subseg
= now_subseg
;
9381 unsigned int alignment
, align_size_1
;
9382 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9383 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9384 unsigned int padding
;
9386 if (!IS_ELF
|| !x86_used_note
)
9389 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9391 /* The .note.gnu.property section layout:
9393 Field Length Contents
9396 n_descsz 4 The note descriptor size
9397 n_type 4 NT_GNU_PROPERTY_TYPE_0
9399 n_desc n_descsz The program property array
9403 /* Create the .note.gnu.property section. */
9404 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9405 bfd_set_section_flags (sec
,
9412 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9423 bfd_set_section_alignment (sec
, alignment
);
9424 elf_section_type (sec
) = SHT_NOTE
;
9426 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9428 isa_1_descsz_raw
= 4 + 4 + 4;
9429 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9430 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9432 feature_2_descsz_raw
= isa_1_descsz
;
9433 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9435 feature_2_descsz_raw
+= 4 + 4 + 4;
9436 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9437 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9440 descsz
= feature_2_descsz
;
9441 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9442 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9444 /* Write n_namsz. */
9445 md_number_to_chars (p
, (valueT
) 4, 4);
9447 /* Write n_descsz. */
9448 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9451 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9454 memcpy (p
+ 4 * 3, "GNU", 4);
9456 /* Write 4-byte type. */
9457 md_number_to_chars (p
+ 4 * 4,
9458 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9460 /* Write 4-byte data size. */
9461 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9463 /* Write 4-byte data. */
9464 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9466 /* Zero out paddings. */
9467 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9469 memset (p
+ 4 * 7, 0, padding
);
9471 /* Write 4-byte type. */
9472 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9473 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9475 /* Write 4-byte data size. */
9476 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9478 /* Write 4-byte data. */
9479 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9480 (valueT
) x86_feature_2_used
, 4);
9482 /* Zero out paddings. */
9483 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9485 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9487 /* We probably can't restore the current segment, for there likely
9490 subseg_set (seg
, subseg
);
9494 x86_support_sframe_p (void)
9496 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9497 return (x86_elf_abi
== X86_64_ABI
);
9501 x86_sframe_ra_tracking_p (void)
9503 /* In AMD64, return address is always stored on the stack at a fixed offset
9504 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9505 Do not track explicitly via an SFrame Frame Row Entry. */
9510 x86_sframe_cfa_ra_offset (void)
9512 gas_assert (x86_elf_abi
== X86_64_ABI
);
9513 return (offsetT
) -8;
9517 x86_sframe_get_abi_arch (void)
9519 unsigned char sframe_abi_arch
= 0;
9521 if (x86_support_sframe_p ())
9523 gas_assert (!target_big_endian
);
9524 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9527 return sframe_abi_arch
;
9533 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9534 const char *frag_now_ptr
)
9536 unsigned int len
= 0;
9538 if (start_frag
!= frag_now
)
9540 const fragS
*fr
= start_frag
;
9545 } while (fr
&& fr
!= frag_now
);
9548 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9551 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9552 be macro-fused with conditional jumps.
9553 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9554 or is one of the following format:
9567 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9569 /* No RIP address. */
9570 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9573 /* No opcodes outside of base encoding space. */
9574 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9577 /* add, sub without add/sub m, imm. */
9578 if (i
.tm
.base_opcode
<= 5
9579 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9580 || ((i
.tm
.base_opcode
| 3) == 0x83
9581 && (i
.tm
.extension_opcode
== 0x5
9582 || i
.tm
.extension_opcode
== 0x0)))
9584 *mf_cmp_p
= mf_cmp_alu_cmp
;
9585 return !(i
.mem_operands
&& i
.imm_operands
);
9588 /* and without and m, imm. */
9589 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9590 || ((i
.tm
.base_opcode
| 3) == 0x83
9591 && i
.tm
.extension_opcode
== 0x4))
9593 *mf_cmp_p
= mf_cmp_test_and
;
9594 return !(i
.mem_operands
&& i
.imm_operands
);
9597 /* test without test m imm. */
9598 if ((i
.tm
.base_opcode
| 1) == 0x85
9599 || (i
.tm
.base_opcode
| 1) == 0xa9
9600 || ((i
.tm
.base_opcode
| 1) == 0xf7
9601 && i
.tm
.extension_opcode
== 0))
9603 *mf_cmp_p
= mf_cmp_test_and
;
9604 return !(i
.mem_operands
&& i
.imm_operands
);
9607 /* cmp without cmp m, imm. */
9608 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9609 || ((i
.tm
.base_opcode
| 3) == 0x83
9610 && (i
.tm
.extension_opcode
== 0x7)))
9612 *mf_cmp_p
= mf_cmp_alu_cmp
;
9613 return !(i
.mem_operands
&& i
.imm_operands
);
9616 /* inc, dec without inc/dec m. */
9617 if ((is_cpu (&i
.tm
, CpuNo64
)
9618 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9619 || ((i
.tm
.base_opcode
| 1) == 0xff
9620 && i
.tm
.extension_opcode
<= 0x1))
9622 *mf_cmp_p
= mf_cmp_incdec
;
9623 return !i
.mem_operands
;
9629 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9632 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9634 /* NB: Don't work with COND_JUMP86 without i386. */
9635 if (!align_branch_power
9636 || now_seg
== absolute_section
9637 || !cpu_arch_flags
.bitfield
.cpui386
9638 || !(align_branch
& align_branch_fused_bit
))
9641 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9643 if (last_insn
.kind
== last_insn_other
9644 || last_insn
.seg
!= now_seg
)
9647 as_warn_where (last_insn
.file
, last_insn
.line
,
9648 _("`%s` skips -malign-branch-boundary on `%s`"),
9649 last_insn
.name
, insn_name (&i
.tm
));
9655 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9658 add_branch_prefix_frag_p (void)
9660 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9661 to PadLock instructions since they include prefixes in opcode. */
9662 if (!align_branch_power
9663 || !align_branch_prefix_size
9664 || now_seg
== absolute_section
9665 || is_cpu (&i
.tm
, CpuPadLock
)
9666 || !cpu_arch_flags
.bitfield
.cpui386
)
9669 /* Don't add prefix if it is a prefix or there is no operand in case
9670 that segment prefix is special. */
9671 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9674 if (last_insn
.kind
== last_insn_other
9675 || last_insn
.seg
!= now_seg
)
9679 as_warn_where (last_insn
.file
, last_insn
.line
,
9680 _("`%s` skips -malign-branch-boundary on `%s`"),
9681 last_insn
.name
, insn_name (&i
.tm
));
9686 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9689 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9690 enum mf_jcc_kind
*mf_jcc_p
)
9694 /* NB: Don't work with COND_JUMP86 without i386. */
9695 if (!align_branch_power
9696 || now_seg
== absolute_section
9697 || !cpu_arch_flags
.bitfield
.cpui386
9698 || i
.tm
.opcode_space
!= SPACE_BASE
)
9703 /* Check for jcc and direct jmp. */
9704 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9706 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9708 *branch_p
= align_branch_jmp
;
9709 add_padding
= align_branch
& align_branch_jmp_bit
;
9713 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9714 igore the lowest bit. */
9715 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9716 *branch_p
= align_branch_jcc
;
9717 if ((align_branch
& align_branch_jcc_bit
))
9721 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9724 *branch_p
= align_branch_ret
;
9725 if ((align_branch
& align_branch_ret_bit
))
9730 /* Check for indirect jmp, direct and indirect calls. */
9731 if (i
.tm
.base_opcode
== 0xe8)
9734 *branch_p
= align_branch_call
;
9735 if ((align_branch
& align_branch_call_bit
))
9738 else if (i
.tm
.base_opcode
== 0xff
9739 && (i
.tm
.extension_opcode
== 2
9740 || i
.tm
.extension_opcode
== 4))
9742 /* Indirect call and jmp. */
9743 *branch_p
= align_branch_indirect
;
9744 if ((align_branch
& align_branch_indirect_bit
))
9751 && (i
.op
[0].disps
->X_op
== O_symbol
9752 || (i
.op
[0].disps
->X_op
== O_subtract
9753 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9755 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9756 /* No padding to call to global or undefined tls_get_addr. */
9757 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9758 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9764 && last_insn
.kind
!= last_insn_other
9765 && last_insn
.seg
== now_seg
)
9768 as_warn_where (last_insn
.file
, last_insn
.line
,
9769 _("`%s` skips -malign-branch-boundary on `%s`"),
9770 last_insn
.name
, insn_name (&i
.tm
));
9780 fragS
*insn_start_frag
;
9781 offsetT insn_start_off
;
9782 fragS
*fragP
= NULL
;
9783 enum align_branch_kind branch
= align_branch_none
;
9784 /* The initializer is arbitrary just to avoid uninitialized error.
9785 it's actually either assigned in add_branch_padding_frag_p
9786 or never be used. */
9787 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9789 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9790 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9792 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9793 || is_cpu (&i
.tm
, CpuAMX_TILE
))
9794 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9796 if (is_cpu (&i
.tm
, Cpu8087
)
9797 || is_cpu (&i
.tm
, Cpu287
)
9798 || is_cpu (&i
.tm
, Cpu387
)
9799 || is_cpu (&i
.tm
, Cpu687
)
9800 || is_cpu (&i
.tm
, CpuFISTTP
))
9801 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9803 if ((i
.xstate
& xstate_mmx
)
9804 || i
.tm
.mnem_off
== MN_emms
9805 || i
.tm
.mnem_off
== MN_femms
)
9806 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9810 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9811 i
.xstate
|= xstate_zmm
;
9812 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9813 i
.xstate
|= xstate_ymm
;
9814 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9815 i
.xstate
|= xstate_xmm
;
9818 /* vzeroall / vzeroupper */
9819 if (i
.tm
.base_opcode
== 0x77 && is_cpu (&i
.tm
, CpuAVX
))
9820 i
.xstate
|= xstate_ymm
;
9822 if ((i
.xstate
& xstate_xmm
)
9823 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9824 || (i
.tm
.base_opcode
== 0xae
9825 && (is_cpu (&i
.tm
, CpuSSE
)
9826 || is_cpu (&i
.tm
, CpuAVX
)))
9827 || is_cpu (&i
.tm
, CpuWideKL
)
9828 || is_cpu (&i
.tm
, CpuKL
))
9829 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9831 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9832 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9833 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9834 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9835 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9836 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9837 if (is_cpu (&i
.tm
, CpuFXSR
))
9838 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9839 if (is_cpu (&i
.tm
, CpuXsave
))
9840 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9841 if (is_cpu (&i
.tm
, CpuXsaveopt
))
9842 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9843 if (is_cpu (&i
.tm
, CpuXSAVEC
))
9844 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9846 if (x86_feature_2_used
9847 || is_cpu (&i
.tm
, CpuCMOV
)
9848 || is_cpu (&i
.tm
, CpuSYSCALL
)
9849 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9850 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9851 if (is_cpu (&i
.tm
, CpuSSE3
)
9852 || is_cpu (&i
.tm
, CpuSSSE3
)
9853 || is_cpu (&i
.tm
, CpuSSE4_1
)
9854 || is_cpu (&i
.tm
, CpuSSE4_2
)
9855 || is_cpu (&i
.tm
, CpuCX16
)
9856 || is_cpu (&i
.tm
, CpuPOPCNT
)
9857 /* LAHF-SAHF insns in 64-bit mode. */
9858 || (flag_code
== CODE_64BIT
9859 && (i
.tm
.base_opcode
| 1) == 0x9f
9860 && i
.tm
.opcode_space
== SPACE_BASE
))
9861 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9862 if (is_cpu (&i
.tm
, CpuAVX
)
9863 || is_cpu (&i
.tm
, CpuAVX2
)
9864 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9865 XOP, FMA4, LPW, TBM, and AMX. */
9866 || (i
.tm
.opcode_modifier
.vex
9867 && !is_cpu (&i
.tm
, CpuAVX512F
)
9868 && !is_cpu (&i
.tm
, CpuAVX512BW
)
9869 && !is_cpu (&i
.tm
, CpuAVX512DQ
)
9870 && !is_cpu (&i
.tm
, CpuXOP
)
9871 && !is_cpu (&i
.tm
, CpuFMA4
)
9872 && !is_cpu (&i
.tm
, CpuLWP
)
9873 && !is_cpu (&i
.tm
, CpuTBM
)
9874 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9875 || is_cpu (&i
.tm
, CpuF16C
)
9876 || is_cpu (&i
.tm
, CpuFMA
)
9877 || is_cpu (&i
.tm
, CpuLZCNT
)
9878 || is_cpu (&i
.tm
, CpuMovbe
)
9879 || is_cpu (&i
.tm
, CpuXSAVES
)
9880 || (x86_feature_2_used
9881 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9882 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9883 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9884 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9885 if (is_cpu (&i
.tm
, CpuAVX512F
)
9886 || is_cpu (&i
.tm
, CpuAVX512BW
)
9887 || is_cpu (&i
.tm
, CpuAVX512DQ
)
9888 || is_cpu (&i
.tm
, CpuAVX512VL
)
9889 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9890 AVX512-4FMAPS, and AVX512-4VNNIW. */
9891 || (i
.tm
.opcode_modifier
.evex
9892 && !is_cpu (&i
.tm
, CpuAVX512ER
)
9893 && !is_cpu (&i
.tm
, CpuAVX512PF
)
9894 && !is_cpu (&i
.tm
, CpuAVX512_4FMAPS
)
9895 && !is_cpu (&i
.tm
, CpuAVX512_4VNNIW
)))
9896 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9900 /* Tie dwarf2 debug info to the address at the start of the insn.
9901 We can't do this after the insn has been output as the current
9902 frag may have been closed off. eg. by frag_var. */
9903 dwarf2_emit_insn (0);
9905 insn_start_frag
= frag_now
;
9906 insn_start_off
= frag_now_fix ();
9908 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9911 /* Branch can be 8 bytes. Leave some room for prefixes. */
9912 unsigned int max_branch_padding_size
= 14;
9914 /* Align section to boundary. */
9915 record_alignment (now_seg
, align_branch_power
);
9917 /* Make room for padding. */
9918 frag_grow (max_branch_padding_size
);
9920 /* Start of the padding. */
9925 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9926 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9929 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9930 fragP
->tc_frag_data
.branch_type
= branch
;
9931 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9934 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9935 && !pre_386_16bit_warned
)
9937 as_warn (_("use .code16 to ensure correct addressing mode"));
9938 pre_386_16bit_warned
= true;
9942 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9944 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9945 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9947 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9948 output_interseg_jump ();
9951 /* Output normal instructions here. */
9955 enum mf_cmp_kind mf_cmp
;
9958 && (i
.tm
.base_opcode
== 0xaee8
9959 || i
.tm
.base_opcode
== 0xaef0
9960 || i
.tm
.base_opcode
== 0xaef8))
9962 /* Encode lfence, mfence, and sfence as
9963 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9964 if (flag_code
== CODE_16BIT
)
9965 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9966 else if (omit_lock_prefix
)
9967 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9969 else if (now_seg
!= absolute_section
)
9971 offsetT val
= 0x240483f0ULL
;
9974 md_number_to_chars (p
, val
, 5);
9977 abs_section_offset
+= 5;
9981 /* Some processors fail on LOCK prefix. This options makes
9982 assembler ignore LOCK prefix and serves as a workaround. */
9983 if (omit_lock_prefix
)
9985 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9986 && i
.tm
.opcode_modifier
.isprefix
)
9988 i
.prefix
[LOCK_PREFIX
] = 0;
9992 /* Skip if this is a branch. */
9994 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9996 /* Make room for padding. */
9997 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
10002 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
10003 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
10006 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
10007 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
10008 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
10010 else if (add_branch_prefix_frag_p ())
10012 unsigned int max_prefix_size
= align_branch_prefix_size
;
10014 /* Make room for padding. */
10015 frag_grow (max_prefix_size
);
10020 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
10021 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
10024 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
10027 /* Since the VEX/EVEX prefix contains the implicit prefix, we
10028 don't need the explicit prefix. */
10029 if (!is_any_vex_encoding (&i
.tm
))
10031 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
10040 if (!is_cpu (&i
.tm
, CpuPadLock
)
10041 || (i
.prefix
[REP_PREFIX
] != 0xf3))
10045 switch (i
.opcode_length
)
10050 /* Check for pseudo prefixes. */
10051 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
10053 as_bad_where (insn_start_frag
->fr_file
,
10054 insn_start_frag
->fr_line
,
10055 _("pseudo prefix without instruction"));
10065 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10066 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
10067 R_X86_64_GOTTPOFF relocation so that linker can safely
10068 perform IE->LE optimization. A dummy REX_OPCODE prefix
10069 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
10070 relocation for GDesc -> IE/LE optimization. */
10071 if (x86_elf_abi
== X86_64_X32_ABI
10073 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
10074 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
10075 && i
.prefix
[REX_PREFIX
] == 0)
10076 add_prefix (REX_OPCODE
);
10079 /* The prefix bytes. */
10080 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
10082 frag_opcode_byte (*q
);
10086 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
10092 frag_opcode_byte (*q
);
10095 /* There should be no other prefixes for instructions
10096 with VEX prefix. */
10100 /* For EVEX instructions i.vrex should become 0 after
10101 build_evex_prefix. For VEX instructions upper 16 registers
10102 aren't available, so VREX should be 0. */
10105 /* Now the VEX prefix. */
10106 if (now_seg
!= absolute_section
)
10108 p
= frag_more (i
.vex
.length
);
10109 for (j
= 0; j
< i
.vex
.length
; j
++)
10110 p
[j
] = i
.vex
.bytes
[j
];
10113 abs_section_offset
+= i
.vex
.length
;
10116 /* Now the opcode; be careful about word order here! */
10117 j
= i
.opcode_length
;
10119 switch (i
.tm
.opcode_space
)
10134 if (now_seg
== absolute_section
)
10135 abs_section_offset
+= j
;
10138 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
10144 && i
.tm
.opcode_space
!= SPACE_BASE
)
10147 if (i
.tm
.opcode_space
!= SPACE_0F
)
10148 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
10152 switch (i
.opcode_length
)
10155 /* Put out high byte first: can't use md_number_to_chars! */
10156 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
10157 /* Fall through. */
10159 *p
= i
.tm
.base_opcode
& 0xff;
10168 /* Now the modrm byte and sib byte (if present). */
10169 if (i
.tm
.opcode_modifier
.modrm
)
10171 frag_opcode_byte ((i
.rm
.regmem
<< 0)
10173 | (i
.rm
.mode
<< 6));
10174 /* If i.rm.regmem == ESP (4)
10175 && i.rm.mode != (Register mode)
10177 ==> need second modrm byte. */
10178 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
10180 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
10181 frag_opcode_byte ((i
.sib
.base
<< 0)
10182 | (i
.sib
.index
<< 3)
10183 | (i
.sib
.scale
<< 6));
10186 if (i
.disp_operands
)
10187 output_disp (insn_start_frag
, insn_start_off
);
10189 if (i
.imm_operands
)
10190 output_imm (insn_start_frag
, insn_start_off
);
10193 * frag_now_fix () returning plain abs_section_offset when we're in the
10194 * absolute section, and abs_section_offset not getting updated as data
10195 * gets added to the frag breaks the logic below.
10197 if (now_seg
!= absolute_section
)
10199 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
10201 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
10205 /* NB: Don't add prefix with GOTPC relocation since
10206 output_disp() above depends on the fixed encoding
10207 length. Can't add prefix with TLS relocation since
10208 it breaks TLS linker optimization. */
10209 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
10210 /* Prefix count on the current instruction. */
10211 unsigned int count
= i
.vex
.length
;
10213 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
10214 /* REX byte is encoded in VEX/EVEX prefix. */
10215 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
10218 /* Count prefixes for extended opcode maps. */
10220 switch (i
.tm
.opcode_space
)
10235 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10238 /* Set the maximum prefix size in BRANCH_PREFIX
10240 if (fragP
->tc_frag_data
.max_bytes
> max
)
10241 fragP
->tc_frag_data
.max_bytes
= max
;
10242 if (fragP
->tc_frag_data
.max_bytes
> count
)
10243 fragP
->tc_frag_data
.max_bytes
-= count
;
10245 fragP
->tc_frag_data
.max_bytes
= 0;
10249 /* Remember the maximum prefix size in FUSED_JCC_PADDING
10251 unsigned int max_prefix_size
;
10252 if (align_branch_prefix_size
> max
)
10253 max_prefix_size
= max
;
10255 max_prefix_size
= align_branch_prefix_size
;
10256 if (max_prefix_size
> count
)
10257 fragP
->tc_frag_data
.max_prefix_length
10258 = max_prefix_size
- count
;
10261 /* Use existing segment prefix if possible. Use CS
10262 segment prefix in 64-bit mode. In 32-bit mode, use SS
10263 segment prefix with ESP/EBP base register and use DS
10264 segment prefix without ESP/EBP base register. */
10265 if (i
.prefix
[SEG_PREFIX
])
10266 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
10267 else if (flag_code
== CODE_64BIT
)
10268 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
10269 else if (i
.base_reg
10270 && (i
.base_reg
->reg_num
== 4
10271 || i
.base_reg
->reg_num
== 5))
10272 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
10274 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
10279 /* NB: Don't work with COND_JUMP86 without i386. */
10280 if (align_branch_power
10281 && now_seg
!= absolute_section
10282 && cpu_arch_flags
.bitfield
.cpui386
)
10284 /* Terminate each frag so that we can add prefix and check for
10286 frag_wane (frag_now
);
10293 pi ("" /*line*/, &i
);
10295 #endif /* DEBUG386 */
10298 /* Return the size of the displacement operand N. */
10301 disp_size (unsigned int n
)
10305 if (i
.types
[n
].bitfield
.disp64
)
10307 else if (i
.types
[n
].bitfield
.disp8
)
10309 else if (i
.types
[n
].bitfield
.disp16
)
10314 /* Return the size of the immediate operand N. */
10317 imm_size (unsigned int n
)
10320 if (i
.types
[n
].bitfield
.imm64
)
10322 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10324 else if (i
.types
[n
].bitfield
.imm16
)
10330 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10335 for (n
= 0; n
< i
.operands
; n
++)
10337 if (operand_type_check (i
.types
[n
], disp
))
10339 int size
= disp_size (n
);
10341 if (now_seg
== absolute_section
)
10342 abs_section_offset
+= size
;
10343 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10345 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10347 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10349 p
= frag_more (size
);
10350 md_number_to_chars (p
, val
, size
);
10354 enum bfd_reloc_code_real reloc_type
;
10355 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10356 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10357 && (!want_disp32 (&i
.tm
)
10358 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10359 && !i
.types
[n
].bitfield
.baseindex
)))
10363 /* We can't have 8 bit displacement here. */
10364 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10366 /* The PC relative address is computed relative
10367 to the instruction boundary, so in case immediate
10368 fields follows, we need to adjust the value. */
10369 if (pcrel
&& i
.imm_operands
)
10374 for (n1
= 0; n1
< i
.operands
; n1
++)
10375 if (operand_type_check (i
.types
[n1
], imm
))
10377 /* Only one immediate is allowed for PC
10378 relative address, except with .insn. */
10379 gas_assert (sz
== 0 || dot_insn ());
10380 sz
+= imm_size (n1
);
10382 /* We should find at least one immediate. */
10383 gas_assert (sz
!= 0);
10384 i
.op
[n
].disps
->X_add_number
-= sz
;
10387 p
= frag_more (size
);
10388 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10390 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10391 && (((reloc_type
== BFD_RELOC_32
10392 || reloc_type
== BFD_RELOC_X86_64_32S
10393 || (reloc_type
== BFD_RELOC_64
10395 && (i
.op
[n
].disps
->X_op
== O_symbol
10396 || (i
.op
[n
].disps
->X_op
== O_add
10397 && ((symbol_get_value_expression
10398 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10400 || reloc_type
== BFD_RELOC_32_PCREL
))
10404 reloc_type
= BFD_RELOC_386_GOTPC
;
10405 i
.has_gotpc_tls_reloc
= true;
10406 i
.op
[n
].disps
->X_add_number
+=
10407 encoding_length (insn_start_frag
, insn_start_off
, p
);
10409 else if (reloc_type
== BFD_RELOC_64
)
10410 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10412 /* Don't do the adjustment for x86-64, as there
10413 the pcrel addressing is relative to the _next_
10414 insn, and that is taken care of in other code. */
10415 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10417 else if (align_branch_power
)
10419 switch (reloc_type
)
10421 case BFD_RELOC_386_TLS_GD
:
10422 case BFD_RELOC_386_TLS_LDM
:
10423 case BFD_RELOC_386_TLS_IE
:
10424 case BFD_RELOC_386_TLS_IE_32
:
10425 case BFD_RELOC_386_TLS_GOTIE
:
10426 case BFD_RELOC_386_TLS_GOTDESC
:
10427 case BFD_RELOC_386_TLS_DESC_CALL
:
10428 case BFD_RELOC_X86_64_TLSGD
:
10429 case BFD_RELOC_X86_64_TLSLD
:
10430 case BFD_RELOC_X86_64_GOTTPOFF
:
10431 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10432 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10433 i
.has_gotpc_tls_reloc
= true;
10438 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10439 size
, i
.op
[n
].disps
, pcrel
,
10442 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10443 && !i
.prefix
[ADDR_PREFIX
])
10444 fixP
->fx_signed
= 1;
10446 /* Check for "call/jmp *mem", "mov mem, %reg",
10447 "test %reg, mem" and "binop mem, %reg" where binop
10448 is one of adc, add, and, cmp, or, sbb, sub, xor
10449 instructions without data prefix. Always generate
10450 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10451 if (i
.prefix
[DATA_PREFIX
] == 0
10452 && (generate_relax_relocations
10455 && i
.rm
.regmem
== 5))
10457 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10458 && i
.tm
.opcode_space
== SPACE_BASE
10459 && ((i
.operands
== 1
10460 && i
.tm
.base_opcode
== 0xff
10461 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10462 || (i
.operands
== 2
10463 && (i
.tm
.base_opcode
== 0x8b
10464 || i
.tm
.base_opcode
== 0x85
10465 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10469 fixP
->fx_tcbit
= i
.rex
!= 0;
10471 && (i
.base_reg
->reg_num
== RegIP
))
10472 fixP
->fx_tcbit2
= 1;
10475 fixP
->fx_tcbit2
= 1;
10483 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10488 for (n
= 0; n
< i
.operands
; n
++)
10490 if (operand_type_check (i
.types
[n
], imm
))
10492 int size
= imm_size (n
);
10494 if (now_seg
== absolute_section
)
10495 abs_section_offset
+= size
;
10496 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10500 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10502 p
= frag_more (size
);
10503 md_number_to_chars (p
, val
, size
);
10507 /* Not absolute_section.
10508 Need a 32-bit fixup (don't support 8bit
10509 non-absolute imms). Try to support other
10511 enum bfd_reloc_code_real reloc_type
;
10514 if (i
.types
[n
].bitfield
.imm32s
10515 && (i
.suffix
== QWORD_MNEM_SUFFIX
10516 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
10517 || (i
.prefix
[REX_PREFIX
] & REX_W
)
10523 p
= frag_more (size
);
10524 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10526 /* This is tough to explain. We end up with this one if we
10527 * have operands that look like
10528 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10529 * obtain the absolute address of the GOT, and it is strongly
10530 * preferable from a performance point of view to avoid using
10531 * a runtime relocation for this. The actual sequence of
10532 * instructions often look something like:
10537 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10539 * The call and pop essentially return the absolute address
10540 * of the label .L66 and store it in %ebx. The linker itself
10541 * will ultimately change the first operand of the addl so
10542 * that %ebx points to the GOT, but to keep things simple, the
10543 * .o file must have this operand set so that it generates not
10544 * the absolute address of .L66, but the absolute address of
10545 * itself. This allows the linker itself simply treat a GOTPC
10546 * relocation as asking for a pcrel offset to the GOT to be
10547 * added in, and the addend of the relocation is stored in the
10548 * operand field for the instruction itself.
10550 * Our job here is to fix the operand so that it would add
10551 * the correct offset so that %ebx would point to itself. The
10552 * thing that is tricky is that .-.L66 will point to the
10553 * beginning of the instruction, so we need to further modify
10554 * the operand so that it will point to itself. There are
10555 * other cases where you have something like:
10557 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10559 * and here no correction would be required. Internally in
10560 * the assembler we treat operands of this form as not being
10561 * pcrel since the '.' is explicitly mentioned, and I wonder
10562 * whether it would simplify matters to do it this way. Who
10563 * knows. In earlier versions of the PIC patches, the
10564 * pcrel_adjust field was used to store the correction, but
10565 * since the expression is not pcrel, I felt it would be
10566 * confusing to do it this way. */
10568 if ((reloc_type
== BFD_RELOC_32
10569 || reloc_type
== BFD_RELOC_X86_64_32S
10570 || reloc_type
== BFD_RELOC_64
)
10572 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10573 && (i
.op
[n
].imms
->X_op
== O_symbol
10574 || (i
.op
[n
].imms
->X_op
== O_add
10575 && ((symbol_get_value_expression
10576 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10580 reloc_type
= BFD_RELOC_386_GOTPC
;
10581 else if (size
== 4)
10582 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10583 else if (size
== 8)
10584 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10585 i
.has_gotpc_tls_reloc
= true;
10586 i
.op
[n
].imms
->X_add_number
+=
10587 encoding_length (insn_start_frag
, insn_start_off
, p
);
10589 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10590 i
.op
[n
].imms
, 0, reloc_type
);
10596 /* x86_cons_fix_new is called via the expression parsing code when a
10597 reloc is needed. We use this hook to get the correct .got reloc. */
10598 static int cons_sign
= -1;
10601 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10602 expressionS
*exp
, bfd_reloc_code_real_type r
)
10604 r
= reloc (len
, 0, cons_sign
, r
);
10607 if (exp
->X_op
== O_secrel
)
10609 exp
->X_op
= O_symbol
;
10610 r
= BFD_RELOC_32_SECREL
;
10612 else if (exp
->X_op
== O_secidx
)
10613 r
= BFD_RELOC_16_SECIDX
;
10616 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10619 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10620 purpose of the `.dc.a' internal pseudo-op. */
10623 x86_address_bytes (void)
10625 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10627 return stdoutput
->arch_info
->bits_per_address
/ 8;
10630 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10631 || defined (LEX_AT)) && !defined (TE_PE)
10632 # define lex_got(reloc, adjust, types) NULL
10634 /* Parse operands of the form
10635 <symbol>@GOTOFF+<nnn>
10636 and similar .plt or .got references.
10638 If we find one, set up the correct relocation in RELOC and copy the
10639 input string, minus the `@GOTOFF' into a malloc'd buffer for
10640 parsing by the calling routine. Return this buffer, and if ADJUST
10641 is non-null set it to the length of the string we removed from the
10642 input line. Otherwise return NULL. */
10644 lex_got (enum bfd_reloc_code_real
*rel
,
10646 i386_operand_type
*types
)
10648 /* Some of the relocations depend on the size of what field is to
10649 be relocated. But in our callers i386_immediate and i386_displacement
10650 we don't yet know the operand size (this will be set by insn
10651 matching). Hence we record the word32 relocation here,
10652 and adjust the reloc according to the real size in reloc(). */
10653 static const struct
10657 const enum bfd_reloc_code_real rel
[2];
10658 const i386_operand_type types64
;
10659 bool need_GOT_symbol
;
10664 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10665 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10666 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10667 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10668 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10669 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10670 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10671 { .imm64 = 1, .disp64 = 1 } }
10674 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10675 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10676 BFD_RELOC_SIZE32
},
10677 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10679 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10680 BFD_RELOC_X86_64_PLTOFF64
},
10681 { .bitfield
= { .imm64
= 1 } }, true },
10682 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10683 BFD_RELOC_X86_64_PLT32
},
10684 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10685 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10686 BFD_RELOC_X86_64_GOTPLT64
},
10687 OPERAND_TYPE_IMM64_DISP64
, true },
10688 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10689 BFD_RELOC_X86_64_GOTOFF64
},
10690 OPERAND_TYPE_IMM64_DISP64
, true },
10691 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10692 BFD_RELOC_X86_64_GOTPCREL
},
10693 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10694 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10695 BFD_RELOC_X86_64_TLSGD
},
10696 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10697 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10698 _dummy_first_bfd_reloc_code_real
},
10699 OPERAND_TYPE_NONE
, true },
10700 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10701 BFD_RELOC_X86_64_TLSLD
},
10702 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10703 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10704 BFD_RELOC_X86_64_GOTTPOFF
},
10705 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10706 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10707 BFD_RELOC_X86_64_TPOFF32
},
10708 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10709 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10710 _dummy_first_bfd_reloc_code_real
},
10711 OPERAND_TYPE_NONE
, true },
10712 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10713 BFD_RELOC_X86_64_DTPOFF32
},
10714 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10715 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10716 _dummy_first_bfd_reloc_code_real
},
10717 OPERAND_TYPE_NONE
, true },
10718 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10719 _dummy_first_bfd_reloc_code_real
},
10720 OPERAND_TYPE_NONE
, true },
10721 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10722 BFD_RELOC_X86_64_GOT32
},
10723 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10724 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10725 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10726 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10727 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10728 BFD_RELOC_X86_64_TLSDESC_CALL
},
10729 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10731 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10732 BFD_RELOC_32_SECREL
},
10733 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10736 #undef OPERAND_TYPE_IMM32_32S_DISP32
10737 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10738 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10739 #undef OPERAND_TYPE_IMM64_DISP64
10745 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10750 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10751 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10754 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10756 int len
= gotrel
[j
].len
;
10757 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10759 if (gotrel
[j
].rel
[object_64bit
] != 0)
10762 char *tmpbuf
, *past_reloc
;
10764 *rel
= gotrel
[j
].rel
[object_64bit
];
10768 if (flag_code
!= CODE_64BIT
)
10770 types
->bitfield
.imm32
= 1;
10771 types
->bitfield
.disp32
= 1;
10774 *types
= gotrel
[j
].types64
;
10777 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10778 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10780 /* The length of the first part of our input line. */
10781 first
= cp
- input_line_pointer
;
10783 /* The second part goes from after the reloc token until
10784 (and including) an end_of_line char or comma. */
10785 past_reloc
= cp
+ 1 + len
;
10787 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10789 second
= cp
+ 1 - past_reloc
;
10791 /* Allocate and copy string. The trailing NUL shouldn't
10792 be necessary, but be safe. */
10793 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10794 memcpy (tmpbuf
, input_line_pointer
, first
);
10795 if (second
!= 0 && *past_reloc
!= ' ')
10796 /* Replace the relocation token with ' ', so that
10797 errors like foo@GOTOFF1 will be detected. */
10798 tmpbuf
[first
++] = ' ';
10800 /* Increment length by 1 if the relocation token is
10805 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10806 tmpbuf
[first
+ second
] = '\0';
10810 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10811 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10816 /* Might be a symbol version string. Don't as_bad here. */
10821 bfd_reloc_code_real_type
10822 x86_cons (expressionS
*exp
, int size
)
10824 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10826 intel_syntax
= -intel_syntax
;
10828 expr_mode
= expr_operator_none
;
10830 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10831 && !defined (LEX_AT)) \
10833 if (size
== 4 || (object_64bit
&& size
== 8))
10835 /* Handle @GOTOFF and the like in an expression. */
10837 char *gotfree_input_line
;
10840 save
= input_line_pointer
;
10841 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10842 if (gotfree_input_line
)
10843 input_line_pointer
= gotfree_input_line
;
10847 if (gotfree_input_line
)
10849 /* expression () has merrily parsed up to the end of line,
10850 or a comma - in the wrong buffer. Transfer how far
10851 input_line_pointer has moved to the right buffer. */
10852 input_line_pointer
= (save
10853 + (input_line_pointer
- gotfree_input_line
)
10855 free (gotfree_input_line
);
10856 if (exp
->X_op
== O_constant
10857 || exp
->X_op
== O_absent
10858 || exp
->X_op
== O_illegal
10859 || exp
->X_op
== O_register
10860 || exp
->X_op
== O_big
)
10862 char c
= *input_line_pointer
;
10863 *input_line_pointer
= 0;
10864 as_bad (_("missing or invalid expression `%s'"), save
);
10865 *input_line_pointer
= c
;
10867 else if ((got_reloc
== BFD_RELOC_386_PLT32
10868 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10869 && exp
->X_op
!= O_symbol
)
10871 char c
= *input_line_pointer
;
10872 *input_line_pointer
= 0;
10873 as_bad (_("invalid PLT expression `%s'"), save
);
10874 *input_line_pointer
= c
;
10882 intel_syntax
= -intel_syntax
;
10885 i386_intel_simplify (exp
);
10887 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10888 if (size
<= 4 && expr_mode
== expr_operator_present
10889 && exp
->X_op
== O_constant
&& !object_64bit
)
10890 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10896 signed_cons (int size
)
10905 s_insn (int dummy ATTRIBUTE_UNUSED
)
10907 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
10908 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10912 bool vex
= false, xop
= false, evex
= false;
10913 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10917 saved_char
= *saved_ilp
;
10920 end
= parse_insn (line
, mnemonic
, true);
10924 *saved_ilp
= saved_char
;
10925 ignore_rest_of_line ();
10929 line
+= end
- line
;
10931 current_templates
= &tt
;
10932 i
.tm
.mnem_off
= MN__insn
;
10933 i
.tm
.extension_opcode
= None
;
10935 if (startswith (line
, "VEX")
10936 && (line
[3] == '.' || is_space_char (line
[3])))
10941 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10944 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10946 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10947 && (*e
== '.' || is_space_char (*e
)))
10950 /* Arrange for build_vex_prefix() to emit 0x8f. */
10951 i
.tm
.opcode_space
= SPACE_XOP08
;
10952 i
.insn_opcode_space
= n
;
10956 else if (startswith (line
, "EVEX")
10957 && (line
[4] == '.' || is_space_char (line
[4])))
10964 ? i
.vec_encoding
== vex_encoding_evex
10966 ? i
.vec_encoding
== vex_encoding_vex
10967 || i
.vec_encoding
== vex_encoding_vex3
10968 : i
.vec_encoding
!= vex_encoding_default
)
10970 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
10974 if (line
> end
&& i
.vec_encoding
== vex_encoding_default
)
10975 i
.vec_encoding
= evex
? vex_encoding_evex
: vex_encoding_vex
;
10977 if (i
.vec_encoding
!= vex_encoding_default
)
10979 /* Only address size and segment override prefixes are permitted with
10980 VEX/XOP/EVEX encodings. */
10981 const unsigned char *p
= i
.prefix
;
10983 for (j
= 0; j
< ARRAY_SIZE (i
.prefix
); ++j
, ++p
)
10994 as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
11000 if (line
> end
&& *line
== '.')
11002 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
11010 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11012 i
.tm
.opcode_modifier
.vex
= VEX128
;
11017 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11019 i
.tm
.opcode_modifier
.vex
= VEX256
;
11024 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11029 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
11033 if (line
[3] == 'G')
11036 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11038 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11044 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
11049 if (line
[2] == '2' && line
[3] == '8')
11052 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11054 i
.tm
.opcode_modifier
.vex
= VEX128
;
11060 if (line
[2] == '5' && line
[3] == '6')
11063 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11065 i
.tm
.opcode_modifier
.vex
= VEX256
;
11071 if (evex
&& line
[2] == '1' && line
[3] == '2')
11073 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11080 if (line
> end
&& *line
== '.')
11082 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
11086 if (line
[2] == 'P')
11091 if (line
[2] == '6')
11093 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
11098 case 'F': case 'f':
11099 if (line
[2] == '3')
11101 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
11104 else if (line
[2] == '2')
11106 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
11113 if (line
> end
&& !xop
&& *line
== '.')
11115 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
11119 if (TOUPPER (line
[2]) != 'F')
11121 if (line
[3] == '.' || is_space_char (line
[3]))
11123 i
.insn_opcode_space
= SPACE_0F
;
11126 else if (line
[3] == '3'
11127 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
11128 && (line
[5] == '.' || is_space_char (line
[5])))
11130 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
11136 if (ISDIGIT (line
[2]) && line
[2] != '0')
11139 unsigned long n
= strtoul (line
+ 2, &e
, 10);
11141 if (n
<= (evex
? 15 : 31)
11142 && (*e
== '.' || is_space_char (*e
)))
11144 i
.insn_opcode_space
= n
;
11152 if (line
> end
&& *line
== '.' && line
[1] == 'W')
11154 /* VEX.W, XOP.W, EVEX.W */
11158 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11162 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11166 if (line
[3] == 'G')
11168 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11174 if (i
.tm
.opcode_modifier
.vexw
)
11178 if (line
> end
&& *line
&& !is_space_char (*line
))
11180 /* Improve diagnostic a little. */
11181 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
11186 /* Before processing the opcode expression, find trailing "+r" or
11187 "/<digit>" specifiers. */
11188 for (ptr
= line
; ; ++ptr
)
11193 ptr
= strpbrk (ptr
, "+/,");
11194 if (ptr
== NULL
|| *ptr
== ',')
11197 if (*ptr
== '+' && ptr
[1] == 'r'
11198 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11202 i
.short_form
= true;
11206 if (*ptr
== '/' && ISDIGIT (ptr
[1])
11207 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
11209 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11213 i
.tm
.extension_opcode
= n
;
11214 i
.tm
.opcode_modifier
.modrm
= 1;
11219 input_line_pointer
= line
;
11220 val
= get_absolute_expression ();
11221 line
= input_line_pointer
;
11223 if (i
.short_form
&& (val
& 7))
11224 as_warn ("`+r' assumes low three opcode bits to be clear");
11226 for (j
= 1; j
< sizeof(val
); ++j
)
11227 if (!(val
>> (j
* 8)))
11230 /* Trim off a prefix if present. */
11231 if (j
> 1 && !vex
&& !xop
&& !evex
)
11233 uint8_t byte
= val
>> ((j
- 1) * 8);
11237 case DATA_PREFIX_OPCODE
:
11238 case REPE_PREFIX_OPCODE
:
11239 case REPNE_PREFIX_OPCODE
:
11240 if (!add_prefix (byte
))
11242 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
11247 /* Trim off encoding space. */
11248 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
11250 uint8_t byte
= val
>> ((--j
- 1) * 8);
11252 i
.insn_opcode_space
= SPACE_0F
;
11253 switch (byte
& -(j
> 1))
11256 i
.insn_opcode_space
= SPACE_0F38
;
11260 i
.insn_opcode_space
= SPACE_0F3A
;
11264 i
.tm
.opcode_space
= i
.insn_opcode_space
;
11265 val
&= ((uint64_t)1 << (j
* 8)) - 1;
11267 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
11268 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
11269 Also avoid hitting abort() there or in build_evex_prefix(). */
11270 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
11275 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
11278 i
.opcode_length
= j
;
11280 /* Handle operands, if any. */
11283 i386_operand_type combined
;
11284 expressionS
*disp_exp
= NULL
;
11289 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
11297 as_bad (_("expecting operand after ','; got nothing"));
11301 if (i
.mem_operands
> 1)
11303 as_bad (_("too many memory references for `%s'"),
11304 &i386_mnemonics
[MN__insn
]);
11308 /* No need to distinguish vex_encoding_evex and vex_encoding_evex512. */
11309 if (i
.vec_encoding
== vex_encoding_evex512
)
11310 i
.vec_encoding
= vex_encoding_evex
;
11312 /* Are we to emit ModR/M encoding? */
11315 || i
.reg_operands
> (i
.vec_encoding
!= vex_encoding_default
)
11316 || i
.tm
.extension_opcode
!= None
))
11317 i
.tm
.opcode_modifier
.modrm
= 1;
11319 if (!i
.tm
.opcode_modifier
.modrm
11321 > i
.short_form
+ 0U + (i
.vec_encoding
!= vex_encoding_default
)
11322 || i
.mem_operands
))
11324 as_bad (_("too many register/memory operands"));
11328 /* Enforce certain constraints on operands. */
11329 switch (i
.reg_operands
+ i
.mem_operands
11330 + (i
.tm
.extension_opcode
!= None
))
11335 as_bad (_("too few register/memory operands"));
11338 /* Fall through. */
11340 if (i
.tm
.opcode_modifier
.modrm
)
11342 as_bad (_("too few register/memory operands"));
11352 && (i
.op
[0].imms
->X_op
!= O_constant
11353 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
11355 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
11358 /* Fall through. */
11360 if (i
.vec_encoding
!= vex_encoding_default
)
11362 i
.tm
.opcode_modifier
.vexvvvv
= 1;
11365 /* Fall through. */
11367 as_bad (_("too many register/memory operands"));
11371 /* Bring operands into canonical order (imm, mem, reg). */
11376 for (j
= 1; j
< i
.operands
; ++j
)
11378 if ((!operand_type_check (i
.types
[j
- 1], imm
)
11379 && operand_type_check (i
.types
[j
], imm
))
11380 || (i
.types
[j
- 1].bitfield
.class != ClassNone
11381 && i
.types
[j
].bitfield
.class == ClassNone
))
11383 swap_2_operands (j
- 1, j
);
11390 /* For Intel syntax swap the order of register operands. */
11392 switch (i
.reg_operands
)
11399 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
11400 /* Fall through. */
11403 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
11410 /* Enforce constraints when using VSIB. */
11412 && (i
.index_reg
->reg_type
.bitfield
.xmmword
11413 || i
.index_reg
->reg_type
.bitfield
.ymmword
11414 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
11416 if (i
.vec_encoding
== vex_encoding_default
)
11418 as_bad (_("VSIB unavailable with legacy encoding"));
11422 if (i
.vec_encoding
== vex_encoding_evex
11423 && i
.reg_operands
> 1)
11425 /* We could allow two register operands, encoding the 2nd one in
11426 an 8-bit immediate like for 4-register-operand insns, but that
11427 would require ugly fiddling with process_operands() and/or
11428 build_modrm_byte(). */
11429 as_bad (_("too many register operands with VSIB"));
11433 i
.tm
.opcode_modifier
.sib
= 1;
11436 /* Establish operand size encoding. */
11437 operand_type_set (&combined
, 0);
11439 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
11441 i
.types
[j
].bitfield
.instance
= InstanceNone
;
11443 if (operand_type_check (i
.types
[j
], disp
))
11445 i
.types
[j
].bitfield
.baseindex
= 1;
11446 disp_exp
= i
.op
[j
].disps
;
11449 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
11451 unsigned int n
= i
.memshift
;
11453 if (i
.types
[j
].bitfield
.byte
)
11455 else if (i
.types
[j
].bitfield
.word
)
11457 else if (i
.types
[j
].bitfield
.dword
)
11459 else if (i
.types
[j
].bitfield
.qword
)
11461 else if (i
.types
[j
].bitfield
.xmmword
)
11463 else if (i
.types
[j
].bitfield
.ymmword
)
11465 else if (i
.types
[j
].bitfield
.zmmword
)
11468 if (i
.memshift
< 32 && n
!= i
.memshift
)
11469 as_warn ("conflicting memory operand size specifiers");
11473 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11474 && j
== i
.broadcast
.operand
)
11477 combined
= operand_type_or (combined
, i
.types
[j
]);
11478 combined
.bitfield
.class = ClassNone
;
11481 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
11482 << (i
.memshift
< 32 ? i
.memshift
: 0))
11484 case 64: combined
.bitfield
.zmmword
= 1; break;
11485 case 32: combined
.bitfield
.ymmword
= 1; break;
11486 case 16: combined
.bitfield
.xmmword
= 1; break;
11487 case 8: combined
.bitfield
.qword
= 1; break;
11488 case 4: combined
.bitfield
.dword
= 1; break;
11491 if (i
.vec_encoding
== vex_encoding_default
)
11493 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
11495 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
11496 : combined
.bitfield
.word
)
11497 && !add_prefix (DATA_PREFIX_OPCODE
))
11500 else if (!i
.tm
.opcode_modifier
.vexw
)
11502 if (flag_code
== CODE_64BIT
)
11504 if (combined
.bitfield
.qword
)
11505 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11506 else if (combined
.bitfield
.dword
)
11507 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11510 if (!i
.tm
.opcode_modifier
.vexw
)
11511 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11516 if (!i
.tm
.opcode_modifier
.vex
)
11518 if (combined
.bitfield
.ymmword
)
11519 i
.tm
.opcode_modifier
.vex
= VEX256
;
11520 else if (combined
.bitfield
.xmmword
)
11521 i
.tm
.opcode_modifier
.vex
= VEX128
;
11526 if (!i
.tm
.opcode_modifier
.evex
)
11528 /* Do _not_ consider AVX512VL here. */
11529 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
11530 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11531 else if (combined
.bitfield
.ymmword
)
11532 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11533 else if (combined
.bitfield
.xmmword
)
11534 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11537 if (i
.memshift
>= 32)
11539 unsigned int n
= 0;
11541 switch (i
.tm
.opcode_modifier
.evex
)
11543 case EVEX512
: n
= 64; break;
11544 case EVEX256
: n
= 32; break;
11545 case EVEX128
: n
= 16; break;
11548 if (i
.broadcast
.type
)
11549 n
/= i
.broadcast
.type
;
11552 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11554 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
11555 && disp_exp
->X_add_number
!= 0
11556 && i
.disp_encoding
!= disp_encoding_32bit
)
11558 if (!quiet_warnings
)
11559 as_warn ("cannot determine memory operand size");
11560 i
.disp_encoding
= disp_encoding_32bit
;
11565 if (i
.memshift
>= 32)
11568 i
.vec_encoding
= vex_encoding_error
;
11570 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
11573 /* Establish size for immediate operands. */
11574 for (j
= 0; j
< i
.imm_operands
; ++j
)
11576 expressionS
*expP
= i
.op
[j
].imms
;
11578 gas_assert (operand_type_check (i
.types
[j
], imm
));
11579 operand_type_set (&i
.types
[j
], 0);
11581 if (i
.imm_bits
[j
] > 32)
11582 i
.types
[j
].bitfield
.imm64
= 1;
11583 else if (i
.imm_bits
[j
] > 16)
11585 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
11586 i
.types
[j
].bitfield
.imm32s
= 1;
11588 i
.types
[j
].bitfield
.imm32
= 1;
11590 else if (i
.imm_bits
[j
] > 8)
11591 i
.types
[j
].bitfield
.imm16
= 1;
11592 else if (i
.imm_bits
[j
] > 0)
11594 if (i
.flags
[j
] & Operand_Signed
)
11595 i
.types
[j
].bitfield
.imm8s
= 1;
11597 i
.types
[j
].bitfield
.imm8
= 1;
11599 else if (expP
->X_op
== O_constant
)
11601 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
11602 i
.types
[j
].bitfield
.imm1
= 0;
11603 /* Oddly enough imm_size() checks imm64 first, so the bit needs
11604 zapping since smallest_imm_type() sets it unconditionally. */
11605 if (flag_code
!= CODE_64BIT
)
11607 i
.types
[j
].bitfield
.imm64
= 0;
11608 i
.types
[j
].bitfield
.imm32s
= 0;
11609 i
.types
[j
].bitfield
.imm32
= 1;
11611 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
11612 i
.types
[j
].bitfield
.imm64
= 0;
11615 /* Non-constant expressions are sized heuristically. */
11618 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
11619 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
11620 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
11624 for (j
= 0; j
< i
.operands
; ++j
)
11625 i
.tm
.operand_types
[j
] = i
.types
[j
];
11627 process_operands ();
11630 /* Don't set opcode until after processing operands, to avoid any
11631 potential special casing there. */
11632 i
.tm
.base_opcode
|= val
;
11634 if (i
.vec_encoding
== vex_encoding_error
11635 || (i
.vec_encoding
!= vex_encoding_evex
11636 ? i
.broadcast
.type
|| i
.broadcast
.bytes
11637 || i
.rounding
.type
!= rc_none
11639 : (i
.mem_operands
&& i
.rounding
.type
!= rc_none
)
11640 || ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11641 && !(i
.flags
[i
.broadcast
.operand
] & Operand_Mem
))))
11643 as_bad (_("conflicting .insn operands"));
11649 if (!i
.tm
.opcode_modifier
.vex
)
11650 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11652 build_vex_prefix (NULL
);
11653 i
.rex
&= REX_OPCODE
;
11657 if (!i
.tm
.opcode_modifier
.evex
)
11658 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11660 build_evex_prefix ();
11661 i
.rex
&= REX_OPCODE
;
11663 else if (i
.rex
!= 0)
11664 add_prefix (REX_OPCODE
| i
.rex
);
11669 *saved_ilp
= saved_char
;
11670 input_line_pointer
= line
;
11672 demand_empty_rest_of_line ();
11674 /* Make sure dot_insn() won't yield "true" anymore. */
11680 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
11687 if (exp
.X_op
== O_symbol
)
11688 exp
.X_op
= O_secrel
;
11690 emit_expr (&exp
, 4);
11692 while (*input_line_pointer
++ == ',');
11694 input_line_pointer
--;
11695 demand_empty_rest_of_line ();
11699 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
11706 if (exp
.X_op
== O_symbol
)
11707 exp
.X_op
= O_secidx
;
11709 emit_expr (&exp
, 2);
11711 while (*input_line_pointer
++ == ',');
11713 input_line_pointer
--;
11714 demand_empty_rest_of_line ();
11718 /* Handle Rounding Control / SAE specifiers. */
11721 RC_SAE_specifier (const char *pstr
)
11725 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11727 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11729 if (i
.rounding
.type
!= rc_none
)
11731 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
11735 if (i
.vec_encoding
== vex_encoding_default
)
11736 i
.vec_encoding
= vex_encoding_evex512
;
11737 else if (i
.vec_encoding
!= vex_encoding_evex
11738 && i
.vec_encoding
!= vex_encoding_evex512
)
11741 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11743 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
11750 /* Handle Vector operations. */
11753 check_VecOperations (char *op_string
)
11755 const reg_entry
*mask
;
11762 if (*op_string
== '{')
11766 /* Check broadcasts. */
11767 if (startswith (op_string
, "1to"))
11769 unsigned int bcst_type
;
11771 if (i
.broadcast
.type
)
11772 goto duplicated_vec_op
;
11775 if (*op_string
== '8')
11777 else if (*op_string
== '4')
11779 else if (*op_string
== '2')
11781 else if (*op_string
== '1'
11782 && *(op_string
+1) == '6')
11787 else if (*op_string
== '3'
11788 && *(op_string
+1) == '2')
11795 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11800 if (i
.vec_encoding
== vex_encoding_default
)
11801 i
.vec_encoding
= vex_encoding_evex
;
11802 else if (i
.vec_encoding
!= vex_encoding_evex
11803 && i
.vec_encoding
!= vex_encoding_evex512
)
11804 goto unknown_vec_op
;
11806 i
.broadcast
.type
= bcst_type
;
11807 i
.broadcast
.operand
= this_operand
;
11809 /* For .insn a data size specifier may be appended. */
11810 if (dot_insn () && *op_string
== ':')
11811 goto dot_insn_modifier
;
11813 /* Check .insn special cases. */
11814 else if (dot_insn () && *op_string
== ':')
11817 switch (op_string
[1])
11822 if (i
.memshift
< 32)
11823 goto duplicated_vec_op
;
11825 n
= strtoul (op_string
+ 2, &end_op
, 0);
11827 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11829 if (i
.memshift
< 32 && n
== 1)
11830 op_string
= end_op
;
11833 case 's': case 'u':
11834 /* This isn't really a "vector" operation, but a sign/size
11835 specifier for immediate operands of .insn. Note that AT&T
11836 syntax handles the same in i386_immediate(). */
11840 if (i
.imm_bits
[this_operand
])
11841 goto duplicated_vec_op
;
11843 n
= strtoul (op_string
+ 2, &end_op
, 0);
11844 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11846 i
.imm_bits
[this_operand
] = n
;
11847 if (op_string
[1] == 's')
11848 i
.flags
[this_operand
] |= Operand_Signed
;
11849 op_string
= end_op
;
11854 /* Check masking operation. */
11855 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11857 if (mask
== &bad_reg
)
11860 /* k0 can't be used for write mask. */
11861 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11863 as_bad (_("`%s%s' can't be used for write mask"),
11864 register_prefix
, mask
->reg_name
);
11871 i
.mask
.operand
= this_operand
;
11873 else if (i
.mask
.reg
->reg_num
)
11874 goto duplicated_vec_op
;
11879 /* Only "{z}" is allowed here. No need to check
11880 zeroing mask explicitly. */
11881 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11883 as_bad (_("invalid write mask `%s'"), saved
);
11888 op_string
= end_op
;
11890 /* Check zeroing-flag for masking operation. */
11891 else if (*op_string
== 'z')
11895 i
.mask
.reg
= reg_k0
;
11896 i
.mask
.zeroing
= 1;
11897 i
.mask
.operand
= this_operand
;
11901 if (i
.mask
.zeroing
)
11904 as_bad (_("duplicated `%s'"), saved
);
11908 i
.mask
.zeroing
= 1;
11910 /* Only "{%k}" is allowed here. No need to check mask
11911 register explicitly. */
11912 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11914 as_bad (_("invalid zeroing-masking `%s'"),
11922 else if (intel_syntax
11923 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11924 i
.rounding
.modifier
= true;
11926 goto unknown_vec_op
;
11928 if (*op_string
!= '}')
11930 as_bad (_("missing `}' in `%s'"), saved
);
11935 /* Strip whitespace since the addition of pseudo prefixes
11936 changed how the scrubber treats '{'. */
11937 if (is_space_char (*op_string
))
11943 /* We don't know this one. */
11944 as_bad (_("unknown vector operation: `%s'"), saved
);
11948 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11950 as_bad (_("zeroing-masking only allowed with write mask"));
11958 i386_immediate (char *imm_start
)
11960 char *save_input_line_pointer
;
11961 char *gotfree_input_line
;
11964 i386_operand_type types
;
11966 operand_type_set (&types
, ~0);
11968 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
11970 as_bad (_("at most %d immediate operands are allowed"),
11971 MAX_IMMEDIATE_OPERANDS
);
11975 exp
= &im_expressions
[i
.imm_operands
++];
11976 i
.op
[this_operand
].imms
= exp
;
11978 if (is_space_char (*imm_start
))
11981 save_input_line_pointer
= input_line_pointer
;
11982 input_line_pointer
= imm_start
;
11984 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11985 if (gotfree_input_line
)
11986 input_line_pointer
= gotfree_input_line
;
11988 expr_mode
= expr_operator_none
;
11989 exp_seg
= expression (exp
);
11991 /* For .insn immediates there may be a size specifier. */
11992 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
11993 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
11996 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
11998 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
12000 i
.imm_bits
[this_operand
] = n
;
12001 if (input_line_pointer
[2] == 's')
12002 i
.flags
[this_operand
] |= Operand_Signed
;
12003 input_line_pointer
= e
+ 1;
12007 SKIP_WHITESPACE ();
12008 if (*input_line_pointer
)
12009 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12011 input_line_pointer
= save_input_line_pointer
;
12012 if (gotfree_input_line
)
12014 free (gotfree_input_line
);
12016 if (exp
->X_op
== O_constant
)
12017 exp
->X_op
= O_illegal
;
12020 if (exp_seg
== reg_section
)
12022 as_bad (_("illegal immediate register operand %s"), imm_start
);
12026 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
12030 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12031 i386_operand_type types
, const char *imm_start
)
12033 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
12036 as_bad (_("missing or invalid immediate expression `%s'"),
12040 else if (exp
->X_op
== O_constant
)
12042 /* Size it properly later. */
12043 i
.types
[this_operand
].bitfield
.imm64
= 1;
12045 /* If not 64bit, sign/zero extend val, to account for wraparound
12047 if (expr_mode
== expr_operator_present
12048 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12049 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12051 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12052 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12053 && exp_seg
!= absolute_section
12054 && exp_seg
!= text_section
12055 && exp_seg
!= data_section
12056 && exp_seg
!= bss_section
12057 && exp_seg
!= undefined_section
12058 && !bfd_is_com_section (exp_seg
))
12060 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12066 /* This is an address. The size of the address will be
12067 determined later, depending on destination register,
12068 suffix, or the default for the section. */
12069 i
.types
[this_operand
].bitfield
.imm8
= 1;
12070 i
.types
[this_operand
].bitfield
.imm16
= 1;
12071 i
.types
[this_operand
].bitfield
.imm32
= 1;
12072 i
.types
[this_operand
].bitfield
.imm32s
= 1;
12073 i
.types
[this_operand
].bitfield
.imm64
= 1;
12074 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
12082 i386_scale (char *scale
)
12085 char *save
= input_line_pointer
;
12087 input_line_pointer
= scale
;
12088 val
= get_absolute_expression ();
12093 i
.log2_scale_factor
= 0;
12096 i
.log2_scale_factor
= 1;
12099 i
.log2_scale_factor
= 2;
12102 i
.log2_scale_factor
= 3;
12106 char sep
= *input_line_pointer
;
12108 *input_line_pointer
= '\0';
12109 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
12111 *input_line_pointer
= sep
;
12112 input_line_pointer
= save
;
12116 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
12118 as_warn (_("scale factor of %d without an index register"),
12119 1 << i
.log2_scale_factor
);
12120 i
.log2_scale_factor
= 0;
12122 scale
= input_line_pointer
;
12123 input_line_pointer
= save
;
12128 i386_displacement (char *disp_start
, char *disp_end
)
12132 char *save_input_line_pointer
;
12133 char *gotfree_input_line
;
12135 i386_operand_type bigdisp
, types
= anydisp
;
12138 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
12140 as_bad (_("at most %d displacement operands are allowed"),
12141 MAX_MEMORY_OPERANDS
);
12145 operand_type_set (&bigdisp
, 0);
12147 || i
.types
[this_operand
].bitfield
.baseindex
12148 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
12149 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
12151 i386_addressing_mode ();
12152 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
12153 if (flag_code
== CODE_64BIT
)
12155 bigdisp
.bitfield
.disp32
= 1;
12157 bigdisp
.bitfield
.disp64
= 1;
12159 else if ((flag_code
== CODE_16BIT
) ^ override
)
12160 bigdisp
.bitfield
.disp16
= 1;
12162 bigdisp
.bitfield
.disp32
= 1;
12166 /* For PC-relative branches, the width of the displacement may be
12167 dependent upon data size, but is never dependent upon address size.
12168 Also make sure to not unintentionally match against a non-PC-relative
12169 branch template. */
12170 static templates aux_templates
;
12171 const insn_template
*t
= current_templates
->start
;
12172 bool has_intel64
= false;
12174 aux_templates
.start
= t
;
12175 while (++t
< current_templates
->end
)
12177 if (t
->opcode_modifier
.jump
12178 != current_templates
->start
->opcode_modifier
.jump
)
12180 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
12181 has_intel64
= true;
12183 if (t
< current_templates
->end
)
12185 aux_templates
.end
= t
;
12186 current_templates
= &aux_templates
;
12189 override
= (i
.prefix
[DATA_PREFIX
] != 0);
12190 if (flag_code
== CODE_64BIT
)
12192 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
12193 && (!intel64
|| !has_intel64
))
12194 bigdisp
.bitfield
.disp16
= 1;
12196 bigdisp
.bitfield
.disp32
= 1;
12201 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
12203 : LONG_MNEM_SUFFIX
));
12204 bigdisp
.bitfield
.disp32
= 1;
12205 if ((flag_code
== CODE_16BIT
) ^ override
)
12207 bigdisp
.bitfield
.disp32
= 0;
12208 bigdisp
.bitfield
.disp16
= 1;
12212 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12215 exp
= &disp_expressions
[i
.disp_operands
];
12216 i
.op
[this_operand
].disps
= exp
;
12218 save_input_line_pointer
= input_line_pointer
;
12219 input_line_pointer
= disp_start
;
12220 END_STRING_AND_SAVE (disp_end
);
12222 #ifndef GCC_ASM_O_HACK
12223 #define GCC_ASM_O_HACK 0
12226 END_STRING_AND_SAVE (disp_end
+ 1);
12227 if (i
.types
[this_operand
].bitfield
.baseIndex
12228 && displacement_string_end
[-1] == '+')
12230 /* This hack is to avoid a warning when using the "o"
12231 constraint within gcc asm statements.
12234 #define _set_tssldt_desc(n,addr,limit,type) \
12235 __asm__ __volatile__ ( \
12236 "movw %w2,%0\n\t" \
12237 "movw %w1,2+%0\n\t" \
12238 "rorl $16,%1\n\t" \
12239 "movb %b1,4+%0\n\t" \
12240 "movb %4,5+%0\n\t" \
12241 "movb $0,6+%0\n\t" \
12242 "movb %h1,7+%0\n\t" \
12244 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
12246 This works great except that the output assembler ends
12247 up looking a bit weird if it turns out that there is
12248 no offset. You end up producing code that looks like:
12261 So here we provide the missing zero. */
12263 *displacement_string_end
= '0';
12266 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12267 if (gotfree_input_line
)
12268 input_line_pointer
= gotfree_input_line
;
12270 expr_mode
= expr_operator_none
;
12271 exp_seg
= expression (exp
);
12273 SKIP_WHITESPACE ();
12274 if (*input_line_pointer
)
12275 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12277 RESTORE_END_STRING (disp_end
+ 1);
12279 input_line_pointer
= save_input_line_pointer
;
12280 if (gotfree_input_line
)
12282 free (gotfree_input_line
);
12284 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
12285 exp
->X_op
= O_illegal
;
12288 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
12290 RESTORE_END_STRING (disp_end
);
12296 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12297 i386_operand_type types
, const char *disp_start
)
12301 /* We do this to make sure that the section symbol is in
12302 the symbol table. We will ultimately change the relocation
12303 to be relative to the beginning of the section. */
12304 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
12305 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
12306 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12308 if (exp
->X_op
!= O_symbol
)
12311 if (S_IS_LOCAL (exp
->X_add_symbol
)
12312 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
12313 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
12314 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
12315 exp
->X_op
= O_subtract
;
12316 exp
->X_op_symbol
= GOT_symbol
;
12317 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
12318 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
12319 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12320 i
.reloc
[this_operand
] = BFD_RELOC_64
;
12322 i
.reloc
[this_operand
] = BFD_RELOC_32
;
12325 else if (exp
->X_op
== O_absent
12326 || exp
->X_op
== O_illegal
12327 || exp
->X_op
== O_big
)
12330 as_bad (_("missing or invalid displacement expression `%s'"),
12335 else if (exp
->X_op
== O_constant
)
12337 /* Sizing gets taken care of by optimize_disp().
12339 If not 64bit, sign/zero extend val, to account for wraparound
12341 if (expr_mode
== expr_operator_present
12342 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12343 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12346 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12347 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12348 && exp_seg
!= absolute_section
12349 && exp_seg
!= text_section
12350 && exp_seg
!= data_section
12351 && exp_seg
!= bss_section
12352 && exp_seg
!= undefined_section
12353 && !bfd_is_com_section (exp_seg
))
12355 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12360 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
12361 i
.types
[this_operand
].bitfield
.disp8
= 1;
12363 /* Check if this is a displacement only operand. */
12364 if (!i
.types
[this_operand
].bitfield
.baseindex
)
12365 i
.types
[this_operand
] =
12366 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
12367 operand_type_and (i
.types
[this_operand
], types
));
12372 /* Return the active addressing mode, taking address override and
12373 registers forming the address into consideration. Update the
12374 address override prefix if necessary. */
12376 static enum flag_code
12377 i386_addressing_mode (void)
12379 enum flag_code addr_mode
;
12381 if (i
.prefix
[ADDR_PREFIX
])
12382 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
12383 else if (flag_code
== CODE_16BIT
12384 && is_cpu (current_templates
->start
, CpuMPX
)
12385 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
12386 from md_assemble() by "is not a valid base/index expression"
12387 when there is a base and/or index. */
12388 && !i
.types
[this_operand
].bitfield
.baseindex
)
12390 /* MPX insn memory operands with neither base nor index must be forced
12391 to use 32-bit addressing in 16-bit mode. */
12392 addr_mode
= CODE_32BIT
;
12393 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12395 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
12396 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
12400 addr_mode
= flag_code
;
12402 #if INFER_ADDR_PREFIX
12403 if (i
.mem_operands
== 0)
12405 /* Infer address prefix from the first memory operand. */
12406 const reg_entry
*addr_reg
= i
.base_reg
;
12408 if (addr_reg
== NULL
)
12409 addr_reg
= i
.index_reg
;
12413 if (addr_reg
->reg_type
.bitfield
.dword
)
12414 addr_mode
= CODE_32BIT
;
12415 else if (flag_code
!= CODE_64BIT
12416 && addr_reg
->reg_type
.bitfield
.word
)
12417 addr_mode
= CODE_16BIT
;
12419 if (addr_mode
!= flag_code
)
12421 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12423 /* Change the size of any displacement too. At most one
12424 of Disp16 or Disp32 is set.
12425 FIXME. There doesn't seem to be any real need for
12426 separate Disp16 and Disp32 flags. The same goes for
12427 Imm16 and Imm32. Removing them would probably clean
12428 up the code quite a lot. */
12429 if (flag_code
!= CODE_64BIT
12430 && (i
.types
[this_operand
].bitfield
.disp16
12431 || i
.types
[this_operand
].bitfield
.disp32
))
12433 static const i386_operand_type disp16_32
= {
12434 .bitfield
= { .disp16
= 1, .disp32
= 1 }
12437 i
.types
[this_operand
]
12438 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
12449 /* Make sure the memory operand we've been dealt is valid.
12450 Return 1 on success, 0 on a failure. */
12453 i386_index_check (const char *operand_string
)
12455 const char *kind
= "base/index";
12456 enum flag_code addr_mode
= i386_addressing_mode ();
12457 const insn_template
*t
= current_templates
->end
- 1;
12459 if (t
->opcode_modifier
.isstring
)
12461 /* Memory operands of string insns are special in that they only allow
12462 a single register (rDI, rSI, or rBX) as their memory address. */
12463 const reg_entry
*expected_reg
;
12464 static const char di_si
[][2][4] =
12470 static const char bx
[][4] = { "ebx", "bx", "rbx" };
12472 kind
= "string address";
12474 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
12476 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
12479 if (!t
->operand_types
[0].bitfield
.baseindex
12480 || ((!i
.mem_operands
!= !intel_syntax
)
12481 && t
->operand_types
[1].bitfield
.baseindex
))
12484 = (const reg_entry
*) str_hash_find (reg_hash
,
12485 di_si
[addr_mode
][op
== es_op
]);
12489 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
12491 if (i
.base_reg
!= expected_reg
12493 || operand_type_check (i
.types
[this_operand
], disp
))
12495 /* The second memory operand must have the same size as
12499 && !((addr_mode
== CODE_64BIT
12500 && i
.base_reg
->reg_type
.bitfield
.qword
)
12501 || (addr_mode
== CODE_32BIT
12502 ? i
.base_reg
->reg_type
.bitfield
.dword
12503 : i
.base_reg
->reg_type
.bitfield
.word
)))
12506 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
12508 intel_syntax
? '[' : '(',
12510 expected_reg
->reg_name
,
12511 intel_syntax
? ']' : ')');
12518 as_bad (_("`%s' is not a valid %s expression"),
12519 operand_string
, kind
);
12524 t
= current_templates
->start
;
12526 if (addr_mode
!= CODE_16BIT
)
12528 /* 32-bit/64-bit checks. */
12529 if (i
.disp_encoding
== disp_encoding_16bit
)
12532 as_bad (_("invalid `%s' prefix"),
12533 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
12538 && ((addr_mode
== CODE_64BIT
12539 ? !i
.base_reg
->reg_type
.bitfield
.qword
12540 : !i
.base_reg
->reg_type
.bitfield
.dword
)
12541 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
12542 || i
.base_reg
->reg_num
== RegIZ
))
12544 && !i
.index_reg
->reg_type
.bitfield
.xmmword
12545 && !i
.index_reg
->reg_type
.bitfield
.ymmword
12546 && !i
.index_reg
->reg_type
.bitfield
.zmmword
12547 && ((addr_mode
== CODE_64BIT
12548 ? !i
.index_reg
->reg_type
.bitfield
.qword
12549 : !i
.index_reg
->reg_type
.bitfield
.dword
)
12550 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
12553 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
12554 if (t
->mnem_off
== MN_bndmk
12555 || t
->mnem_off
== MN_bndldx
12556 || t
->mnem_off
== MN_bndstx
12557 || t
->opcode_modifier
.sib
== SIBMEM
)
12559 /* They cannot use RIP-relative addressing. */
12560 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12562 as_bad (_("`%s' cannot be used here"), operand_string
);
12566 /* bndldx and bndstx ignore their scale factor. */
12567 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
12568 && i
.log2_scale_factor
)
12569 as_warn (_("register scaling is being ignored here"));
12574 /* 16-bit checks. */
12575 if (i
.disp_encoding
== disp_encoding_32bit
)
12579 && (!i
.base_reg
->reg_type
.bitfield
.word
12580 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
12582 && (!i
.index_reg
->reg_type
.bitfield
.word
12583 || !i
.index_reg
->reg_type
.bitfield
.baseindex
12585 && i
.base_reg
->reg_num
< 6
12586 && i
.index_reg
->reg_num
>= 6
12587 && i
.log2_scale_factor
== 0))))
12594 /* Handle vector immediates. */
12597 RC_SAE_immediate (const char *imm_start
)
12599 const char *pstr
= imm_start
;
12604 pstr
= RC_SAE_specifier (pstr
+ 1);
12608 if (*pstr
++ != '}')
12610 as_bad (_("Missing '}': '%s'"), imm_start
);
12613 /* RC/SAE immediate string should contain nothing more. */;
12616 as_bad (_("Junk after '}': '%s'"), imm_start
);
12620 /* Internally this doesn't count as an operand. */
12626 static INLINE
bool starts_memory_operand (char c
)
12629 || is_name_beginner (c
)
12630 || strchr ("([\"+-!~", c
);
12633 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
12637 i386_att_operand (char *operand_string
)
12639 const reg_entry
*r
;
12641 char *op_string
= operand_string
;
12643 if (is_space_char (*op_string
))
12646 /* We check for an absolute prefix (differentiating,
12647 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
12648 if (*op_string
== ABSOLUTE_PREFIX
12649 && current_templates
->start
->opcode_modifier
.jump
)
12652 if (is_space_char (*op_string
))
12654 i
.jumpabsolute
= true;
12657 /* Check if operand is a register. */
12658 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
12660 i386_operand_type temp
;
12665 /* Check for a segment override by searching for ':' after a
12666 segment register. */
12667 op_string
= end_op
;
12668 if (is_space_char (*op_string
))
12670 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
12672 i
.seg
[i
.mem_operands
] = r
;
12674 /* Skip the ':' and whitespace. */
12676 if (is_space_char (*op_string
))
12679 /* Handle case of %es:*foo. */
12680 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
12681 && current_templates
->start
->opcode_modifier
.jump
)
12684 if (is_space_char (*op_string
))
12686 i
.jumpabsolute
= true;
12689 if (!starts_memory_operand (*op_string
))
12691 as_bad (_("bad memory operand `%s'"), op_string
);
12694 goto do_memory_reference
;
12697 /* Handle vector operations. */
12698 if (*op_string
== '{')
12700 op_string
= check_VecOperations (op_string
);
12701 if (op_string
== NULL
)
12707 as_bad (_("junk `%s' after register"), op_string
);
12711 /* Reject pseudo registers for .insn. */
12712 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
12714 as_bad (_("`%s%s' cannot be used here"),
12715 register_prefix
, r
->reg_name
);
12719 temp
= r
->reg_type
;
12720 temp
.bitfield
.baseindex
= 0;
12721 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12723 i
.types
[this_operand
].bitfield
.unspecified
= 0;
12724 i
.op
[this_operand
].regs
= r
;
12727 /* A GPR may follow an RC or SAE immediate only if a (vector) register
12728 operand was also present earlier on. */
12729 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
12730 && i
.reg_operands
== 1)
12734 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
12735 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
12737 as_bad (_("`%s': misplaced `{%s}'"),
12738 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
12742 else if (*op_string
== REGISTER_PREFIX
)
12744 as_bad (_("bad register name `%s'"), op_string
);
12747 else if (*op_string
== IMMEDIATE_PREFIX
)
12750 if (i
.jumpabsolute
)
12752 as_bad (_("immediate operand illegal with absolute jump"));
12755 if (!i386_immediate (op_string
))
12757 if (i
.rounding
.type
!= rc_none
)
12759 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
12760 insn_name (current_templates
->start
));
12764 else if (RC_SAE_immediate (operand_string
))
12766 /* If it is a RC or SAE immediate, do the necessary placement check:
12767 Only another immediate or a GPR may precede it. */
12768 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
12769 || (i
.reg_operands
== 1
12770 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
12772 as_bad (_("`%s': misplaced `%s'"),
12773 insn_name (current_templates
->start
), operand_string
);
12777 else if (starts_memory_operand (*op_string
))
12779 /* This is a memory reference of some sort. */
12782 /* Start and end of displacement string expression (if found). */
12783 char *displacement_string_start
;
12784 char *displacement_string_end
;
12786 do_memory_reference
:
12787 /* Check for base index form. We detect the base index form by
12788 looking for an ')' at the end of the operand, searching
12789 for the '(' matching it, and finding a REGISTER_PREFIX or ','
12791 base_string
= op_string
+ strlen (op_string
);
12793 /* Handle vector operations. */
12795 if (is_space_char (*base_string
))
12798 if (*base_string
== '}')
12800 char *vop_start
= NULL
;
12802 while (base_string
-- > op_string
)
12804 if (*base_string
== '"')
12806 if (*base_string
!= '{')
12809 vop_start
= base_string
;
12812 if (is_space_char (*base_string
))
12815 if (*base_string
!= '}')
12823 as_bad (_("unbalanced figure braces"));
12827 if (check_VecOperations (vop_start
) == NULL
)
12831 /* If we only have a displacement, set-up for it to be parsed later. */
12832 displacement_string_start
= op_string
;
12833 displacement_string_end
= base_string
+ 1;
12835 if (*base_string
== ')')
12838 unsigned int parens_not_balanced
= 0;
12839 bool in_quotes
= false;
12841 /* We've already checked that the number of left & right ()'s are
12842 equal, and that there's a matching set of double quotes. */
12843 end_op
= base_string
;
12844 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
12846 if (*temp_string
== '\\' && temp_string
[1] == '"')
12848 else if (*temp_string
== '"')
12849 in_quotes
= !in_quotes
;
12850 else if (!in_quotes
)
12852 if (*temp_string
== '(' && !parens_not_balanced
++)
12853 base_string
= temp_string
;
12854 if (*temp_string
== ')')
12855 --parens_not_balanced
;
12859 temp_string
= base_string
;
12861 /* Skip past '(' and whitespace. */
12862 gas_assert (*base_string
== '(');
12864 if (is_space_char (*base_string
))
12867 if (*base_string
== ','
12868 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12871 displacement_string_end
= temp_string
;
12873 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12877 if (i
.base_reg
== &bad_reg
)
12879 base_string
= end_op
;
12880 if (is_space_char (*base_string
))
12884 /* There may be an index reg or scale factor here. */
12885 if (*base_string
== ',')
12888 if (is_space_char (*base_string
))
12891 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12894 if (i
.index_reg
== &bad_reg
)
12896 base_string
= end_op
;
12897 if (is_space_char (*base_string
))
12899 if (*base_string
== ',')
12902 if (is_space_char (*base_string
))
12905 else if (*base_string
!= ')')
12907 as_bad (_("expecting `,' or `)' "
12908 "after index register in `%s'"),
12913 else if (*base_string
== REGISTER_PREFIX
)
12915 end_op
= strchr (base_string
, ',');
12918 as_bad (_("bad register name `%s'"), base_string
);
12922 /* Check for scale factor. */
12923 if (*base_string
!= ')')
12925 char *end_scale
= i386_scale (base_string
);
12930 base_string
= end_scale
;
12931 if (is_space_char (*base_string
))
12933 if (*base_string
!= ')')
12935 as_bad (_("expecting `)' "
12936 "after scale factor in `%s'"),
12941 else if (!i
.index_reg
)
12943 as_bad (_("expecting index register or scale factor "
12944 "after `,'; got '%c'"),
12949 else if (*base_string
!= ')')
12951 as_bad (_("expecting `,' or `)' "
12952 "after base register in `%s'"),
12957 else if (*base_string
== REGISTER_PREFIX
)
12959 end_op
= strchr (base_string
, ',');
12962 as_bad (_("bad register name `%s'"), base_string
);
12967 /* If there's an expression beginning the operand, parse it,
12968 assuming displacement_string_start and
12969 displacement_string_end are meaningful. */
12970 if (displacement_string_start
!= displacement_string_end
)
12972 if (!i386_displacement (displacement_string_start
,
12973 displacement_string_end
))
12977 /* Special case for (%dx) while doing input/output op. */
12979 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
12980 && i
.base_reg
->reg_type
.bitfield
.word
12981 && i
.index_reg
== 0
12982 && i
.log2_scale_factor
== 0
12983 && i
.seg
[i
.mem_operands
] == 0
12984 && !operand_type_check (i
.types
[this_operand
], disp
))
12986 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
12987 i
.input_output_operand
= true;
12991 if (i386_index_check (operand_string
) == 0)
12993 i
.flags
[this_operand
] |= Operand_Mem
;
12998 /* It's not a memory operand; argh! */
12999 as_bad (_("invalid char %s beginning operand %d `%s'"),
13000 output_invalid (*op_string
),
13005 return 1; /* Normal return. */
13008 /* Calculate the maximum variable size (i.e., excluding fr_fix)
13009 that an rs_machine_dependent frag may reach. */
13012 i386_frag_max_var (fragS
*frag
)
13014 /* The only relaxable frags are for jumps.
13015 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
13016 gas_assert (frag
->fr_type
== rs_machine_dependent
);
13017 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
13020 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13022 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
13024 /* STT_GNU_IFUNC symbol must go through PLT. */
13025 if ((symbol_get_bfdsym (fr_symbol
)->flags
13026 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
13029 if (!S_IS_EXTERNAL (fr_symbol
))
13030 /* Symbol may be weak or local. */
13031 return !S_IS_WEAK (fr_symbol
);
13033 /* Global symbols with non-default visibility can't be preempted. */
13034 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
13037 if (fr_var
!= NO_RELOC
)
13038 switch ((enum bfd_reloc_code_real
) fr_var
)
13040 case BFD_RELOC_386_PLT32
:
13041 case BFD_RELOC_X86_64_PLT32
:
13042 /* Symbol with PLT relocation may be preempted. */
13048 /* Global symbols with default visibility in a shared library may be
13049 preempted by another definition. */
13054 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
13055 Note also work for Skylake and Cascadelake.
13056 ---------------------------------------------------------------------
13057 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
13058 | ------ | ----------- | ------- | -------- |
13060 | Jno | N | N | Y |
13061 | Jc/Jb | Y | N | Y |
13062 | Jae/Jnb | Y | N | Y |
13063 | Je/Jz | Y | Y | Y |
13064 | Jne/Jnz | Y | Y | Y |
13065 | Jna/Jbe | Y | N | Y |
13066 | Ja/Jnbe | Y | N | Y |
13068 | Jns | N | N | Y |
13069 | Jp/Jpe | N | N | Y |
13070 | Jnp/Jpo | N | N | Y |
13071 | Jl/Jnge | Y | Y | Y |
13072 | Jge/Jnl | Y | Y | Y |
13073 | Jle/Jng | Y | Y | Y |
13074 | Jg/Jnle | Y | Y | Y |
13075 --------------------------------------------------------------------- */
13077 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
13079 if (mf_cmp
== mf_cmp_alu_cmp
)
13080 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
13081 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
13082 if (mf_cmp
== mf_cmp_incdec
)
13083 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
13084 || mf_jcc
== mf_jcc_jle
);
13085 if (mf_cmp
== mf_cmp_test_and
)
13090 /* Return the next non-empty frag. */
13093 i386_next_non_empty_frag (fragS
*fragP
)
13095 /* There may be a frag with a ".fill 0" when there is no room in
13096 the current frag for frag_grow in output_insn. */
13097 for (fragP
= fragP
->fr_next
;
13099 && fragP
->fr_type
== rs_fill
13100 && fragP
->fr_fix
== 0);
13101 fragP
= fragP
->fr_next
)
13106 /* Return the next jcc frag after BRANCH_PADDING. */
13109 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
13111 fragS
*branch_fragP
;
13115 if (pad_fragP
->fr_type
== rs_machine_dependent
13116 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
13117 == BRANCH_PADDING
))
13119 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
13120 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
13122 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
13123 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
13124 pad_fragP
->tc_frag_data
.mf_type
))
13125 return branch_fragP
;
13131 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
13134 i386_classify_machine_dependent_frag (fragS
*fragP
)
13138 fragS
*branch_fragP
;
13140 unsigned int max_prefix_length
;
13142 if (fragP
->tc_frag_data
.classified
)
13145 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
13146 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
13147 for (next_fragP
= fragP
;
13148 next_fragP
!= NULL
;
13149 next_fragP
= next_fragP
->fr_next
)
13151 next_fragP
->tc_frag_data
.classified
= 1;
13152 if (next_fragP
->fr_type
== rs_machine_dependent
)
13153 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
13155 case BRANCH_PADDING
:
13156 /* The BRANCH_PADDING frag must be followed by a branch
13158 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
13159 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13161 case FUSED_JCC_PADDING
:
13162 /* Check if this is a fused jcc:
13164 CMP like instruction
13168 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
13169 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
13170 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
13173 /* The BRANCH_PADDING frag is merged with the
13174 FUSED_JCC_PADDING frag. */
13175 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13176 /* CMP like instruction size. */
13177 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
13178 frag_wane (pad_fragP
);
13179 /* Skip to branch_fragP. */
13180 next_fragP
= branch_fragP
;
13182 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
13184 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
13186 next_fragP
->fr_subtype
13187 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
13188 next_fragP
->tc_frag_data
.max_bytes
13189 = next_fragP
->tc_frag_data
.max_prefix_length
;
13190 /* This will be updated in the BRANCH_PREFIX scan. */
13191 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
13194 frag_wane (next_fragP
);
13199 /* Stop if there is no BRANCH_PREFIX. */
13200 if (!align_branch_prefix_size
)
13203 /* Scan for BRANCH_PREFIX. */
13204 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
13206 if (fragP
->fr_type
!= rs_machine_dependent
13207 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13211 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
13212 COND_JUMP_PREFIX. */
13213 max_prefix_length
= 0;
13214 for (next_fragP
= fragP
;
13215 next_fragP
!= NULL
;
13216 next_fragP
= next_fragP
->fr_next
)
13218 if (next_fragP
->fr_type
== rs_fill
)
13219 /* Skip rs_fill frags. */
13221 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
13222 /* Stop for all other frags. */
13225 /* rs_machine_dependent frags. */
13226 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13229 /* Count BRANCH_PREFIX frags. */
13230 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
13232 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
13233 frag_wane (next_fragP
);
13237 += next_fragP
->tc_frag_data
.max_bytes
;
13239 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13241 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13242 == FUSED_JCC_PADDING
))
13244 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
13245 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
13249 /* Stop for other rs_machine_dependent frags. */
13253 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
13255 /* Skip to the next frag. */
13256 fragP
= next_fragP
;
13260 /* Compute padding size for
13263 CMP like instruction
13265 COND_JUMP/UNCOND_JUMP
13270 COND_JUMP/UNCOND_JUMP
13274 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
13276 unsigned int offset
, size
, padding_size
;
13277 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
13279 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
13281 address
= fragP
->fr_address
;
13282 address
+= fragP
->fr_fix
;
13284 /* CMP like instrunction size. */
13285 size
= fragP
->tc_frag_data
.cmp_size
;
13287 /* The base size of the branch frag. */
13288 size
+= branch_fragP
->fr_fix
;
13290 /* Add opcode and displacement bytes for the rs_machine_dependent
13292 if (branch_fragP
->fr_type
== rs_machine_dependent
)
13293 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
13295 /* Check if branch is within boundary and doesn't end at the last
13297 offset
= address
& ((1U << align_branch_power
) - 1);
13298 if ((offset
+ size
) >= (1U << align_branch_power
))
13299 /* Padding needed to avoid crossing boundary. */
13300 padding_size
= (1U << align_branch_power
) - offset
;
13302 /* No padding needed. */
13305 /* The return value may be saved in tc_frag_data.length which is
13307 if (!fits_in_unsigned_byte (padding_size
))
13310 return padding_size
;
13313 /* i386_generic_table_relax_frag()
13315 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
13316 grow/shrink padding to align branch frags. Hand others to
13320 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
13322 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13323 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13325 long padding_size
= i386_branch_padding_size (fragP
, 0);
13326 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
13328 /* When the BRANCH_PREFIX frag is used, the computed address
13329 must match the actual address and there should be no padding. */
13330 if (fragP
->tc_frag_data
.padding_address
13331 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
13335 /* Update the padding size. */
13337 fragP
->tc_frag_data
.length
= padding_size
;
13341 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13343 fragS
*padding_fragP
, *next_fragP
;
13344 long padding_size
, left_size
, last_size
;
13346 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13347 if (!padding_fragP
)
13348 /* Use the padding set by the leading BRANCH_PREFIX frag. */
13349 return (fragP
->tc_frag_data
.length
13350 - fragP
->tc_frag_data
.last_length
);
13352 /* Compute the relative address of the padding frag in the very
13353 first time where the BRANCH_PREFIX frag sizes are zero. */
13354 if (!fragP
->tc_frag_data
.padding_address
)
13355 fragP
->tc_frag_data
.padding_address
13356 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
13358 /* First update the last length from the previous interation. */
13359 left_size
= fragP
->tc_frag_data
.prefix_length
;
13360 for (next_fragP
= fragP
;
13361 next_fragP
!= padding_fragP
;
13362 next_fragP
= next_fragP
->fr_next
)
13363 if (next_fragP
->fr_type
== rs_machine_dependent
13364 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13369 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13373 if (max
> left_size
)
13378 next_fragP
->tc_frag_data
.last_length
= size
;
13382 next_fragP
->tc_frag_data
.last_length
= 0;
13385 /* Check the padding size for the padding frag. */
13386 padding_size
= i386_branch_padding_size
13387 (padding_fragP
, (fragP
->fr_address
13388 + fragP
->tc_frag_data
.padding_address
));
13390 last_size
= fragP
->tc_frag_data
.prefix_length
;
13391 /* Check if there is change from the last interation. */
13392 if (padding_size
== last_size
)
13394 /* Update the expected address of the padding frag. */
13395 padding_fragP
->tc_frag_data
.padding_address
13396 = (fragP
->fr_address
+ padding_size
13397 + fragP
->tc_frag_data
.padding_address
);
13401 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
13403 /* No padding if there is no sufficient room. Clear the
13404 expected address of the padding frag. */
13405 padding_fragP
->tc_frag_data
.padding_address
= 0;
13409 /* Store the expected address of the padding frag. */
13410 padding_fragP
->tc_frag_data
.padding_address
13411 = (fragP
->fr_address
+ padding_size
13412 + fragP
->tc_frag_data
.padding_address
);
13414 fragP
->tc_frag_data
.prefix_length
= padding_size
;
13416 /* Update the length for the current interation. */
13417 left_size
= padding_size
;
13418 for (next_fragP
= fragP
;
13419 next_fragP
!= padding_fragP
;
13420 next_fragP
= next_fragP
->fr_next
)
13421 if (next_fragP
->fr_type
== rs_machine_dependent
13422 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13427 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13431 if (max
> left_size
)
13436 next_fragP
->tc_frag_data
.length
= size
;
13440 next_fragP
->tc_frag_data
.length
= 0;
13443 return (fragP
->tc_frag_data
.length
13444 - fragP
->tc_frag_data
.last_length
);
13446 return relax_frag (segment
, fragP
, stretch
);
13449 /* md_estimate_size_before_relax()
13451 Called just before relax() for rs_machine_dependent frags. The x86
13452 assembler uses these frags to handle variable size jump
13455 Any symbol that is now undefined will not become defined.
13456 Return the correct fr_subtype in the frag.
13457 Return the initial "guess for variable size of frag" to caller.
13458 The guess is actually the growth beyond the fixed part. Whatever
13459 we do to grow the fixed or variable part contributes to our
13463 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
13465 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13466 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
13467 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13469 i386_classify_machine_dependent_frag (fragP
);
13470 return fragP
->tc_frag_data
.length
;
13473 /* We've already got fragP->fr_subtype right; all we have to do is
13474 check for un-relaxable symbols. On an ELF system, we can't relax
13475 an externally visible symbol, because it may be overridden by a
13477 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
13478 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13480 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
13483 #if defined (OBJ_COFF) && defined (TE_PE)
13484 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
13485 && S_IS_WEAK (fragP
->fr_symbol
))
13489 /* Symbol is undefined in this segment, or we need to keep a
13490 reloc so that weak symbols can be overridden. */
13491 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
13492 enum bfd_reloc_code_real reloc_type
;
13493 unsigned char *opcode
;
13497 if (fragP
->fr_var
!= NO_RELOC
)
13498 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
13499 else if (size
== 2)
13500 reloc_type
= BFD_RELOC_16_PCREL
;
13501 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13502 else if (fragP
->tc_frag_data
.code
== CODE_64BIT
13503 && fragP
->fr_offset
== 0
13504 && need_plt32_p (fragP
->fr_symbol
))
13505 reloc_type
= BFD_RELOC_X86_64_PLT32
;
13508 reloc_type
= BFD_RELOC_32_PCREL
;
13510 old_fr_fix
= fragP
->fr_fix
;
13511 opcode
= (unsigned char *) fragP
->fr_opcode
;
13513 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
13516 /* Make jmp (0xeb) a (d)word displacement jump. */
13518 fragP
->fr_fix
+= size
;
13519 fixP
= fix_new (fragP
, old_fr_fix
, size
,
13521 fragP
->fr_offset
, 1,
13527 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
13529 /* Negate the condition, and branch past an
13530 unconditional jump. */
13533 /* Insert an unconditional jump. */
13535 /* We added two extra opcode bytes, and have a two byte
13537 fragP
->fr_fix
+= 2 + 2;
13538 fix_new (fragP
, old_fr_fix
+ 2, 2,
13540 fragP
->fr_offset
, 1,
13544 /* Fall through. */
13547 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
13549 fragP
->fr_fix
+= 1;
13550 fixP
= fix_new (fragP
, old_fr_fix
, 1,
13552 fragP
->fr_offset
, 1,
13553 BFD_RELOC_8_PCREL
);
13554 fixP
->fx_signed
= 1;
13558 /* This changes the byte-displacement jump 0x7N
13559 to the (d)word-displacement jump 0x0f,0x8N. */
13560 opcode
[1] = opcode
[0] + 0x10;
13561 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13562 /* We've added an opcode byte. */
13563 fragP
->fr_fix
+= 1 + size
;
13564 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
13566 fragP
->fr_offset
, 1,
13571 BAD_CASE (fragP
->fr_subtype
);
13575 /* All jumps handled here are signed, but don't unconditionally use a
13576 signed limit check for 32 and 16 bit jumps as we want to allow wrap
13577 around at 4G (outside of 64-bit mode) and 64k. */
13578 if (size
== 4 && flag_code
== CODE_64BIT
)
13579 fixP
->fx_signed
= 1;
13582 return fragP
->fr_fix
- old_fr_fix
;
13585 /* Guess size depending on current relax state. Initially the relax
13586 state will correspond to a short jump and we return 1, because
13587 the variable part of the frag (the branch offset) is one byte
13588 long. However, we can relax a section more than once and in that
13589 case we must either set fr_subtype back to the unrelaxed state,
13590 or return the value for the appropriate branch. */
13591 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
13594 /* Called after relax() is finished.
13596 In: Address of frag.
13597 fr_type == rs_machine_dependent.
13598 fr_subtype is what the address relaxed to.
13600 Out: Any fixSs and constants are set up.
13601 Caller will turn frag into a ".space 0". */
13604 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
13607 unsigned char *opcode
;
13608 unsigned char *where_to_put_displacement
= NULL
;
13609 offsetT target_address
;
13610 offsetT opcode_address
;
13611 unsigned int extension
= 0;
13612 offsetT displacement_from_opcode_start
;
13614 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13615 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
13616 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13618 /* Generate nop padding. */
13619 unsigned int size
= fragP
->tc_frag_data
.length
;
13622 if (size
> fragP
->tc_frag_data
.max_bytes
)
13628 const char *branch
= "branch";
13629 const char *prefix
= "";
13630 fragS
*padding_fragP
;
13631 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13634 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13635 switch (fragP
->tc_frag_data
.default_prefix
)
13640 case CS_PREFIX_OPCODE
:
13643 case DS_PREFIX_OPCODE
:
13646 case ES_PREFIX_OPCODE
:
13649 case FS_PREFIX_OPCODE
:
13652 case GS_PREFIX_OPCODE
:
13655 case SS_PREFIX_OPCODE
:
13660 msg
= _("%s:%u: add %d%s at 0x%llx to align "
13661 "%s within %d-byte boundary\n");
13663 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
13664 "align %s within %d-byte boundary\n");
13668 padding_fragP
= fragP
;
13669 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
13670 "%s within %d-byte boundary\n");
13674 switch (padding_fragP
->tc_frag_data
.branch_type
)
13676 case align_branch_jcc
:
13679 case align_branch_fused
:
13680 branch
= "fused jcc";
13682 case align_branch_jmp
:
13685 case align_branch_call
:
13688 case align_branch_indirect
:
13689 branch
= "indiret branch";
13691 case align_branch_ret
:
13698 fprintf (stdout
, msg
,
13699 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
13700 (long long) fragP
->fr_address
, branch
,
13701 1 << align_branch_power
);
13703 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13704 memset (fragP
->fr_opcode
,
13705 fragP
->tc_frag_data
.default_prefix
, size
);
13707 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
13709 fragP
->fr_fix
+= size
;
13714 opcode
= (unsigned char *) fragP
->fr_opcode
;
13716 /* Address we want to reach in file space. */
13717 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
13719 /* Address opcode resides at in file space. */
13720 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
13722 /* Displacement from opcode start to fill into instruction. */
13723 displacement_from_opcode_start
= target_address
- opcode_address
;
13725 if ((fragP
->fr_subtype
& BIG
) == 0)
13727 /* Don't have to change opcode. */
13728 extension
= 1; /* 1 opcode + 1 displacement */
13729 where_to_put_displacement
= &opcode
[1];
13733 if (no_cond_jump_promotion
13734 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
13735 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
13736 _("long jump required"));
13738 switch (fragP
->fr_subtype
)
13740 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
13741 extension
= 4; /* 1 opcode + 4 displacement */
13743 where_to_put_displacement
= &opcode
[1];
13746 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
13747 extension
= 2; /* 1 opcode + 2 displacement */
13749 where_to_put_displacement
= &opcode
[1];
13752 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
13753 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
13754 extension
= 5; /* 2 opcode + 4 displacement */
13755 opcode
[1] = opcode
[0] + 0x10;
13756 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13757 where_to_put_displacement
= &opcode
[2];
13760 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
13761 extension
= 3; /* 2 opcode + 2 displacement */
13762 opcode
[1] = opcode
[0] + 0x10;
13763 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13764 where_to_put_displacement
= &opcode
[2];
13767 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
13772 where_to_put_displacement
= &opcode
[3];
13776 BAD_CASE (fragP
->fr_subtype
);
13781 /* If size if less then four we are sure that the operand fits,
13782 but if it's 4, then it could be that the displacement is larger
13784 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
13786 && ((addressT
) (displacement_from_opcode_start
- extension
13787 + ((addressT
) 1 << 31))
13788 > (((addressT
) 2 << 31) - 1)))
13790 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
13791 _("jump target out of range"));
13792 /* Make us emit 0. */
13793 displacement_from_opcode_start
= extension
;
13795 /* Now put displacement after opcode. */
13796 md_number_to_chars ((char *) where_to_put_displacement
,
13797 (valueT
) (displacement_from_opcode_start
- extension
),
13798 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
13799 fragP
->fr_fix
+= extension
;
13802 /* Apply a fixup (fixP) to segment data, once it has been determined
13803 by our caller that we have all the info we need to fix it up.
13805 Parameter valP is the pointer to the value of the bits.
13807 On the 386, immediates, displacements, and data pointers are all in
13808 the same (little-endian) format, so we don't need to care about which
13809 we are handling. */
13812 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13814 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
13815 valueT value
= *valP
;
13817 #if !defined (TE_Mach)
13818 if (fixP
->fx_pcrel
)
13820 switch (fixP
->fx_r_type
)
13826 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
13829 case BFD_RELOC_X86_64_32S
:
13830 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
13833 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
13836 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
13841 if (fixP
->fx_addsy
!= NULL
13842 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
13843 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
13844 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
13845 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
13846 && !use_rela_relocations
)
13848 /* This is a hack. There should be a better way to handle this.
13849 This covers for the fact that bfd_install_relocation will
13850 subtract the current location (for partial_inplace, PC relative
13851 relocations); see more below. */
13855 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
13858 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13860 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13863 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
13865 if ((sym_seg
== seg
13866 || (symbol_section_p (fixP
->fx_addsy
)
13867 && sym_seg
!= absolute_section
))
13868 && !generic_force_reloc (fixP
))
13870 /* Yes, we add the values in twice. This is because
13871 bfd_install_relocation subtracts them out again. I think
13872 bfd_install_relocation is broken, but I don't dare change
13874 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13878 #if defined (OBJ_COFF) && defined (TE_PE)
13879 /* For some reason, the PE format does not store a
13880 section address offset for a PC relative symbol. */
13881 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13882 || S_IS_WEAK (fixP
->fx_addsy
))
13883 value
+= md_pcrel_from (fixP
);
13886 #if defined (OBJ_COFF) && defined (TE_PE)
13887 if (fixP
->fx_addsy
!= NULL
13888 && S_IS_WEAK (fixP
->fx_addsy
)
13889 /* PR 16858: Do not modify weak function references. */
13890 && ! fixP
->fx_pcrel
)
13892 #if !defined (TE_PEP)
13893 /* For x86 PE weak function symbols are neither PC-relative
13894 nor do they set S_IS_FUNCTION. So the only reliable way
13895 to detect them is to check the flags of their containing
13897 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13898 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13902 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13906 /* Fix a few things - the dynamic linker expects certain values here,
13907 and we must not disappoint it. */
13908 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13909 if (IS_ELF
&& fixP
->fx_addsy
)
13910 switch (fixP
->fx_r_type
)
13912 case BFD_RELOC_386_PLT32
:
13913 case BFD_RELOC_X86_64_PLT32
:
13914 /* Make the jump instruction point to the address of the operand.
13915 At runtime we merely add the offset to the actual PLT entry.
13916 NB: Subtract the offset size only for jump instructions. */
13917 if (fixP
->fx_pcrel
)
13921 case BFD_RELOC_386_TLS_GD
:
13922 case BFD_RELOC_386_TLS_LDM
:
13923 case BFD_RELOC_386_TLS_IE_32
:
13924 case BFD_RELOC_386_TLS_IE
:
13925 case BFD_RELOC_386_TLS_GOTIE
:
13926 case BFD_RELOC_386_TLS_GOTDESC
:
13927 case BFD_RELOC_X86_64_TLSGD
:
13928 case BFD_RELOC_X86_64_TLSLD
:
13929 case BFD_RELOC_X86_64_GOTTPOFF
:
13930 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13931 value
= 0; /* Fully resolved at runtime. No addend. */
13933 case BFD_RELOC_386_TLS_LE
:
13934 case BFD_RELOC_386_TLS_LDO_32
:
13935 case BFD_RELOC_386_TLS_LE_32
:
13936 case BFD_RELOC_X86_64_DTPOFF32
:
13937 case BFD_RELOC_X86_64_DTPOFF64
:
13938 case BFD_RELOC_X86_64_TPOFF32
:
13939 case BFD_RELOC_X86_64_TPOFF64
:
13940 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13943 case BFD_RELOC_386_TLS_DESC_CALL
:
13944 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13945 value
= 0; /* Fully resolved at runtime. No addend. */
13946 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13950 case BFD_RELOC_VTABLE_INHERIT
:
13951 case BFD_RELOC_VTABLE_ENTRY
:
13958 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13960 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13962 value
= extend_to_32bit_address (value
);
13965 #endif /* !defined (TE_Mach) */
13967 /* Are we finished with this relocation now? */
13968 if (fixP
->fx_addsy
== NULL
)
13971 switch (fixP
->fx_r_type
)
13973 case BFD_RELOC_X86_64_32S
:
13974 fixP
->fx_signed
= 1;
13981 #if defined (OBJ_COFF) && defined (TE_PE)
13982 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
13985 /* Remember value for tc_gen_reloc. */
13986 fixP
->fx_addnumber
= value
;
13987 /* Clear out the frag for now. */
13991 else if (use_rela_relocations
)
13993 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
13994 fixP
->fx_no_overflow
= 1;
13995 /* Remember value for tc_gen_reloc. */
13996 fixP
->fx_addnumber
= value
;
14000 md_number_to_chars (p
, value
, fixP
->fx_size
);
14004 md_atof (int type
, char *litP
, int *sizeP
)
14006 /* This outputs the LITTLENUMs in REVERSE order;
14007 in accord with the bigendian 386. */
14008 return ieee_md_atof (type
, litP
, sizeP
, false);
14011 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
14014 output_invalid (int c
)
14017 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14020 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14021 "(0x%x)", (unsigned char) c
);
14022 return output_invalid_buf
;
14025 /* Verify that @r can be used in the current context. */
14027 static bool check_register (const reg_entry
*r
)
14029 if (allow_pseudo_reg
)
14032 if (operand_type_all_zero (&r
->reg_type
))
14035 if ((r
->reg_type
.bitfield
.dword
14036 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
14037 || r
->reg_type
.bitfield
.class == RegCR
14038 || r
->reg_type
.bitfield
.class == RegDR
)
14039 && !cpu_arch_flags
.bitfield
.cpui386
)
14042 if (r
->reg_type
.bitfield
.class == RegTR
14043 && (flag_code
== CODE_64BIT
14044 || !cpu_arch_flags
.bitfield
.cpui386
14045 || cpu_arch_isa_flags
.bitfield
.cpui586
14046 || cpu_arch_isa_flags
.bitfield
.cpui686
))
14049 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
14052 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
14054 if (r
->reg_type
.bitfield
.zmmword
14055 || r
->reg_type
.bitfield
.class == RegMask
)
14058 if (!cpu_arch_flags
.bitfield
.cpuavx
)
14060 if (r
->reg_type
.bitfield
.ymmword
)
14063 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
14068 if (r
->reg_type
.bitfield
.zmmword
)
14070 if (vector_size
< VSZ512
)
14073 if (i
.vec_encoding
== vex_encoding_default
)
14074 i
.vec_encoding
= vex_encoding_evex512
;
14075 else if (i
.vec_encoding
!= vex_encoding_evex
14076 && i
.vec_encoding
!= vex_encoding_evex512
)
14077 i
.vec_encoding
= vex_encoding_error
;
14080 if (vector_size
< VSZ256
&& r
->reg_type
.bitfield
.ymmword
)
14083 if (r
->reg_type
.bitfield
.tmmword
14084 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
14085 || flag_code
!= CODE_64BIT
))
14088 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
14091 /* Don't allow fake index register unless allow_index_reg isn't 0. */
14092 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
14095 /* Upper 16 vector registers are only available with VREX in 64bit
14096 mode, and require EVEX encoding. */
14097 if (r
->reg_flags
& RegVRex
)
14099 if (!cpu_arch_flags
.bitfield
.cpuavx512f
14100 || flag_code
!= CODE_64BIT
)
14103 if (i
.vec_encoding
== vex_encoding_default
14104 || i
.vec_encoding
== vex_encoding_evex512
)
14105 i
.vec_encoding
= vex_encoding_evex
;
14106 else if (i
.vec_encoding
!= vex_encoding_evex
)
14107 i
.vec_encoding
= vex_encoding_error
;
14110 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
14111 && (!cpu_arch_flags
.bitfield
.cpu64
14112 || r
->reg_type
.bitfield
.class != RegCR
14114 && flag_code
!= CODE_64BIT
)
14117 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
14124 /* REG_STRING starts *before* REGISTER_PREFIX. */
14126 static const reg_entry
*
14127 parse_real_register (const char *reg_string
, char **end_op
)
14129 const char *s
= reg_string
;
14131 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
14132 const reg_entry
*r
;
14134 /* Skip possible REGISTER_PREFIX and possible whitespace. */
14135 if (*s
== REGISTER_PREFIX
)
14138 if (is_space_char (*s
))
14141 p
= reg_name_given
;
14142 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
14144 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
14145 return (const reg_entry
*) NULL
;
14149 if (is_part_of_name (*s
))
14150 return (const reg_entry
*) NULL
;
14152 *end_op
= (char *) s
;
14154 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
14156 /* Handle floating point regs, allowing spaces in the (i) part. */
14159 if (!cpu_arch_flags
.bitfield
.cpu8087
14160 && !cpu_arch_flags
.bitfield
.cpu287
14161 && !cpu_arch_flags
.bitfield
.cpu387
14162 && !allow_pseudo_reg
)
14163 return (const reg_entry
*) NULL
;
14165 if (is_space_char (*s
))
14170 if (is_space_char (*s
))
14172 if (*s
>= '0' && *s
<= '7')
14174 int fpr
= *s
- '0';
14176 if (is_space_char (*s
))
14180 *end_op
= (char *) s
+ 1;
14181 know (r
[fpr
].reg_num
== fpr
);
14185 /* We have "%st(" then garbage. */
14186 return (const reg_entry
*) NULL
;
14190 return r
&& check_register (r
) ? r
: NULL
;
14193 /* REG_STRING starts *before* REGISTER_PREFIX. */
14195 static const reg_entry
*
14196 parse_register (const char *reg_string
, char **end_op
)
14198 const reg_entry
*r
;
14200 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
14201 r
= parse_real_register (reg_string
, end_op
);
14206 char *save
= input_line_pointer
;
14207 char *buf
= xstrdup (reg_string
), *name
;
14210 input_line_pointer
= buf
;
14211 get_symbol_name (&name
);
14212 symbolP
= symbol_find (name
);
14213 while (symbolP
&& symbol_equated_p (symbolP
))
14215 const expressionS
*e
= symbol_get_value_expression(symbolP
);
14217 if (e
->X_add_number
)
14219 symbolP
= e
->X_add_symbol
;
14221 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
14223 const expressionS
*e
= symbol_get_value_expression (symbolP
);
14225 if (e
->X_op
== O_register
)
14227 know (e
->X_add_number
>= 0
14228 && (valueT
) e
->X_add_number
< i386_regtab_size
);
14229 r
= i386_regtab
+ e
->X_add_number
;
14230 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
14232 if (r
&& !check_register (r
))
14234 as_bad (_("register '%s%s' cannot be used here"),
14235 register_prefix
, r
->reg_name
);
14239 input_line_pointer
= save
;
14246 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
14248 const reg_entry
*r
= NULL
;
14249 char *end
= input_line_pointer
;
14251 /* We only know the terminating character here. It being double quote could
14252 be the closing one of a quoted symbol name, or an opening one from a
14253 following string (or another quoted symbol name). Since the latter can't
14254 be valid syntax for anything, bailing in either case is good enough. */
14255 if (*nextcharP
== '"')
14259 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
14260 r
= parse_real_register (name
, &input_line_pointer
);
14261 if (r
&& end
<= input_line_pointer
)
14263 *nextcharP
= *input_line_pointer
;
14264 *input_line_pointer
= 0;
14265 e
->X_op
= O_register
;
14266 e
->X_add_number
= r
- i386_regtab
;
14269 input_line_pointer
= end
;
14271 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
14275 md_operand (expressionS
*e
)
14278 const reg_entry
*r
;
14280 switch (*input_line_pointer
)
14282 case REGISTER_PREFIX
:
14283 r
= parse_real_register (input_line_pointer
, &end
);
14286 e
->X_op
= O_register
;
14287 e
->X_add_number
= r
- i386_regtab
;
14288 input_line_pointer
= end
;
14293 gas_assert (intel_syntax
);
14294 end
= input_line_pointer
++;
14296 if (*input_line_pointer
== ']')
14298 ++input_line_pointer
;
14299 e
->X_op_symbol
= make_expr_symbol (e
);
14300 e
->X_add_symbol
= NULL
;
14301 e
->X_add_number
= 0;
14306 e
->X_op
= O_absent
;
14307 input_line_pointer
= end
;
14314 /* To maintain consistency with !BFD64 builds of gas record, whether any
14315 (binary) operator was involved in an expression. As expressions are
14316 evaluated in only 32 bits when !BFD64, we use this to decide whether to
14317 truncate results. */
14318 bool i386_record_operator (operatorT op
,
14319 const expressionS
*left
,
14320 const expressionS
*right
)
14322 if (op
== O_absent
)
14327 /* Since the expression parser applies unary operators fine to bignum
14328 operands, we don't need to be concerned of respective operands not
14329 fitting in 32 bits. */
14330 if (right
->X_op
== O_constant
&& right
->X_unsigned
14331 && !fits_in_unsigned_long (right
->X_add_number
))
14334 /* This isn't entirely right: The pattern can also result when constant
14335 expressions are folded (e.g. 0xffffffff + 1). */
14336 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
14337 && !fits_in_unsigned_long (left
->X_add_number
))
14338 || (right
->X_op
== O_constant
&& right
->X_unsigned
14339 && !fits_in_unsigned_long (right
->X_add_number
)))
14340 expr_mode
= expr_large_value
;
14342 if (expr_mode
!= expr_large_value
)
14343 expr_mode
= expr_operator_present
;
14349 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14350 const char *md_shortopts
= "kVQ:sqnO::";
14352 const char *md_shortopts
= "qnO::";
14355 #define OPTION_32 (OPTION_MD_BASE + 0)
14356 #define OPTION_64 (OPTION_MD_BASE + 1)
14357 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
14358 #define OPTION_MARCH (OPTION_MD_BASE + 3)
14359 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
14360 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
14361 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
14362 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
14363 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
14364 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
14365 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
14366 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
14367 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
14368 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
14369 #define OPTION_X32 (OPTION_MD_BASE + 14)
14370 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
14371 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
14372 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
14373 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
14374 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
14375 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
14376 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
14377 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
14378 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
14379 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
14380 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
14381 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
14382 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
14383 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
14384 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
14385 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
14386 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
14387 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
14388 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
14389 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
14391 struct option md_longopts
[] =
14393 {"32", no_argument
, NULL
, OPTION_32
},
14394 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14395 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14396 {"64", no_argument
, NULL
, OPTION_64
},
14398 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14399 {"x32", no_argument
, NULL
, OPTION_X32
},
14400 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14401 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
14403 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
14404 {"march", required_argument
, NULL
, OPTION_MARCH
},
14405 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14406 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
14407 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
14408 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
14409 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
14410 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
14411 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
14412 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
14413 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
14414 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
14415 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
14416 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
14417 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
14418 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
14419 # if defined (TE_PE) || defined (TE_PEP)
14420 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
14422 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
14423 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
14424 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
14425 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
14426 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
14427 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
14428 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
14429 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
14430 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
14431 {"mlfence-before-indirect-branch", required_argument
, NULL
,
14432 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
14433 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
14434 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
14435 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
14436 {NULL
, no_argument
, NULL
, 0}
14438 size_t md_longopts_size
= sizeof (md_longopts
);
14441 md_parse_option (int c
, const char *arg
)
14444 char *arch
, *next
, *saved
, *type
;
14449 optimize_align_code
= 0;
14453 quiet_warnings
= 1;
14456 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14457 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
14458 should be emitted or not. FIXME: Not implemented. */
14460 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
14464 /* -V: SVR4 argument to print version ID. */
14466 print_version_id ();
14469 /* -k: Ignore for FreeBSD compatibility. */
14474 /* -s: On i386 Solaris, this tells the native assembler to use
14475 .stab instead of .stab.excl. We always use .stab anyhow. */
14478 case OPTION_MSHARED
:
14482 case OPTION_X86_USED_NOTE
:
14483 if (strcasecmp (arg
, "yes") == 0)
14485 else if (strcasecmp (arg
, "no") == 0)
14488 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
14493 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14494 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14497 const char **list
, **l
;
14499 list
= bfd_target_list ();
14500 for (l
= list
; *l
!= NULL
; l
++)
14501 if (startswith (*l
, "elf64-x86-64")
14502 || strcmp (*l
, "coff-x86-64") == 0
14503 || strcmp (*l
, "pe-x86-64") == 0
14504 || strcmp (*l
, "pei-x86-64") == 0
14505 || strcmp (*l
, "mach-o-x86-64") == 0)
14507 default_arch
= "x86_64";
14511 as_fatal (_("no compiled in support for x86_64"));
14517 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14521 const char **list
, **l
;
14523 list
= bfd_target_list ();
14524 for (l
= list
; *l
!= NULL
; l
++)
14525 if (startswith (*l
, "elf32-x86-64"))
14527 default_arch
= "x86_64:32";
14531 as_fatal (_("no compiled in support for 32bit x86_64"));
14535 as_fatal (_("32bit x86_64 is only supported for ELF"));
14541 const char **list
, **l
;
14543 list
= bfd_target_list ();
14544 for (l
= list
; *l
!= NULL
; l
++)
14545 if (strstr (*l
, "-i386")
14546 || strstr (*l
, "-go32"))
14548 default_arch
= "i386";
14552 as_fatal (_("no compiled in support for ix86"));
14557 case OPTION_DIVIDE
:
14558 #ifdef SVR4_COMMENT_CHARS
14563 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
14565 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
14569 i386_comment_chars
= n
;
14575 saved
= xstrdup (arg
);
14577 /* Allow -march=+nosse. */
14585 as_fatal (_("invalid -march= option: `%s'"), arg
);
14586 next
= strchr (arch
, '+');
14589 vsz
= strchr (arch
, '/');
14592 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14594 if (vsz
&& cpu_arch
[j
].vsz
!= vsz_set
)
14597 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
14598 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
14601 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14604 cpu_arch_name
= cpu_arch
[j
].name
;
14605 free (cpu_sub_arch_name
);
14606 cpu_sub_arch_name
= NULL
;
14607 cpu_arch_flags
= cpu_arch
[j
].enable
;
14608 cpu_arch_isa
= cpu_arch
[j
].type
;
14609 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
14610 if (!cpu_arch_tune_set
)
14611 cpu_arch_tune
= cpu_arch_isa
;
14612 vector_size
= VSZ_DEFAULT
;
14615 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
14616 && strcmp (arch
, cpu_arch
[j
].name
) == 0
14617 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14619 /* ISA extension. */
14622 switch (cpu_arch
[j
].vsz
)
14631 unsigned long val
= strtoul (vsz
, &end
, 0);
14637 case 512: vector_size
= VSZ512
; break;
14638 case 256: vector_size
= VSZ256
; break;
14639 case 128: vector_size
= VSZ128
; break;
14641 as_warn (_("Unrecognized vector size specifier ignored"));
14646 /* Fall through. */
14648 vector_size
= VSZ_DEFAULT
;
14656 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
14658 /* Disable an ISA extension. */
14659 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14660 if (cpu_arch
[j
].type
== PROCESSOR_NONE
14661 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
14664 if (cpu_arch
[j
].vsz
== vsz_set
)
14665 vector_size
= VSZ_DEFAULT
;
14670 if (j
>= ARRAY_SIZE (cpu_arch
))
14671 as_fatal (_("invalid -march= option: `%s'"), arg
);
14675 while (next
!= NULL
);
14681 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14682 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14684 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14685 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
14687 cpu_arch_tune_set
= 1;
14688 cpu_arch_tune
= cpu_arch
[j
].type
;
14692 if (j
>= ARRAY_SIZE (cpu_arch
))
14693 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14696 case OPTION_MMNEMONIC
:
14697 if (strcasecmp (arg
, "att") == 0)
14698 intel_mnemonic
= 0;
14699 else if (strcasecmp (arg
, "intel") == 0)
14700 intel_mnemonic
= 1;
14702 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
14705 case OPTION_MSYNTAX
:
14706 if (strcasecmp (arg
, "att") == 0)
14708 else if (strcasecmp (arg
, "intel") == 0)
14711 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
14714 case OPTION_MINDEX_REG
:
14715 allow_index_reg
= 1;
14718 case OPTION_MNAKED_REG
:
14719 allow_naked_reg
= 1;
14722 case OPTION_MSSE2AVX
:
14726 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
14727 use_unaligned_vector_move
= 1;
14730 case OPTION_MSSE_CHECK
:
14731 if (strcasecmp (arg
, "error") == 0)
14732 sse_check
= check_error
;
14733 else if (strcasecmp (arg
, "warning") == 0)
14734 sse_check
= check_warning
;
14735 else if (strcasecmp (arg
, "none") == 0)
14736 sse_check
= check_none
;
14738 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
14741 case OPTION_MOPERAND_CHECK
:
14742 if (strcasecmp (arg
, "error") == 0)
14743 operand_check
= check_error
;
14744 else if (strcasecmp (arg
, "warning") == 0)
14745 operand_check
= check_warning
;
14746 else if (strcasecmp (arg
, "none") == 0)
14747 operand_check
= check_none
;
14749 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
14752 case OPTION_MAVXSCALAR
:
14753 if (strcasecmp (arg
, "128") == 0)
14754 avxscalar
= vex128
;
14755 else if (strcasecmp (arg
, "256") == 0)
14756 avxscalar
= vex256
;
14758 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
14761 case OPTION_MVEXWIG
:
14762 if (strcmp (arg
, "0") == 0)
14764 else if (strcmp (arg
, "1") == 0)
14767 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
14770 case OPTION_MADD_BND_PREFIX
:
14771 add_bnd_prefix
= 1;
14774 case OPTION_MEVEXLIG
:
14775 if (strcmp (arg
, "128") == 0)
14776 evexlig
= evexl128
;
14777 else if (strcmp (arg
, "256") == 0)
14778 evexlig
= evexl256
;
14779 else if (strcmp (arg
, "512") == 0)
14780 evexlig
= evexl512
;
14782 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
14785 case OPTION_MEVEXRCIG
:
14786 if (strcmp (arg
, "rne") == 0)
14788 else if (strcmp (arg
, "rd") == 0)
14790 else if (strcmp (arg
, "ru") == 0)
14792 else if (strcmp (arg
, "rz") == 0)
14795 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
14798 case OPTION_MEVEXWIG
:
14799 if (strcmp (arg
, "0") == 0)
14801 else if (strcmp (arg
, "1") == 0)
14804 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
14807 # if defined (TE_PE) || defined (TE_PEP)
14808 case OPTION_MBIG_OBJ
:
14813 case OPTION_MOMIT_LOCK_PREFIX
:
14814 if (strcasecmp (arg
, "yes") == 0)
14815 omit_lock_prefix
= 1;
14816 else if (strcasecmp (arg
, "no") == 0)
14817 omit_lock_prefix
= 0;
14819 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
14822 case OPTION_MFENCE_AS_LOCK_ADD
:
14823 if (strcasecmp (arg
, "yes") == 0)
14825 else if (strcasecmp (arg
, "no") == 0)
14828 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
14831 case OPTION_MLFENCE_AFTER_LOAD
:
14832 if (strcasecmp (arg
, "yes") == 0)
14833 lfence_after_load
= 1;
14834 else if (strcasecmp (arg
, "no") == 0)
14835 lfence_after_load
= 0;
14837 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
14840 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
14841 if (strcasecmp (arg
, "all") == 0)
14843 lfence_before_indirect_branch
= lfence_branch_all
;
14844 if (lfence_before_ret
== lfence_before_ret_none
)
14845 lfence_before_ret
= lfence_before_ret_shl
;
14847 else if (strcasecmp (arg
, "memory") == 0)
14848 lfence_before_indirect_branch
= lfence_branch_memory
;
14849 else if (strcasecmp (arg
, "register") == 0)
14850 lfence_before_indirect_branch
= lfence_branch_register
;
14851 else if (strcasecmp (arg
, "none") == 0)
14852 lfence_before_indirect_branch
= lfence_branch_none
;
14854 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
14858 case OPTION_MLFENCE_BEFORE_RET
:
14859 if (strcasecmp (arg
, "or") == 0)
14860 lfence_before_ret
= lfence_before_ret_or
;
14861 else if (strcasecmp (arg
, "not") == 0)
14862 lfence_before_ret
= lfence_before_ret_not
;
14863 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
14864 lfence_before_ret
= lfence_before_ret_shl
;
14865 else if (strcasecmp (arg
, "none") == 0)
14866 lfence_before_ret
= lfence_before_ret_none
;
14868 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
14872 case OPTION_MRELAX_RELOCATIONS
:
14873 if (strcasecmp (arg
, "yes") == 0)
14874 generate_relax_relocations
= 1;
14875 else if (strcasecmp (arg
, "no") == 0)
14876 generate_relax_relocations
= 0;
14878 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
14881 case OPTION_MALIGN_BRANCH_BOUNDARY
:
14884 long int align
= strtoul (arg
, &end
, 0);
14889 align_branch_power
= 0;
14892 else if (align
>= 16)
14895 for (align_power
= 0;
14897 align
>>= 1, align_power
++)
14899 /* Limit alignment power to 31. */
14900 if (align
== 1 && align_power
< 32)
14902 align_branch_power
= align_power
;
14907 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
14911 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
14914 int align
= strtoul (arg
, &end
, 0);
14915 /* Some processors only support 5 prefixes. */
14916 if (*end
== '\0' && align
>= 0 && align
< 6)
14918 align_branch_prefix_size
= align
;
14921 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
14926 case OPTION_MALIGN_BRANCH
:
14928 saved
= xstrdup (arg
);
14932 next
= strchr (type
, '+');
14935 if (strcasecmp (type
, "jcc") == 0)
14936 align_branch
|= align_branch_jcc_bit
;
14937 else if (strcasecmp (type
, "fused") == 0)
14938 align_branch
|= align_branch_fused_bit
;
14939 else if (strcasecmp (type
, "jmp") == 0)
14940 align_branch
|= align_branch_jmp_bit
;
14941 else if (strcasecmp (type
, "call") == 0)
14942 align_branch
|= align_branch_call_bit
;
14943 else if (strcasecmp (type
, "ret") == 0)
14944 align_branch
|= align_branch_ret_bit
;
14945 else if (strcasecmp (type
, "indirect") == 0)
14946 align_branch
|= align_branch_indirect_bit
;
14948 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14951 while (next
!= NULL
);
14955 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14956 align_branch_power
= 5;
14957 align_branch_prefix_size
= 5;
14958 align_branch
= (align_branch_jcc_bit
14959 | align_branch_fused_bit
14960 | align_branch_jmp_bit
);
14963 case OPTION_MAMD64
:
14967 case OPTION_MINTEL64
:
14975 /* Turn off -Os. */
14976 optimize_for_space
= 0;
14978 else if (*arg
== 's')
14980 optimize_for_space
= 1;
14981 /* Turn on all encoding optimizations. */
14982 optimize
= INT_MAX
;
14986 optimize
= atoi (arg
);
14987 /* Turn off -Os. */
14988 optimize_for_space
= 0;
14998 #define MESSAGE_TEMPLATE \
15002 output_message (FILE *stream
, char *p
, char *message
, char *start
,
15003 int *left_p
, const char *name
, int len
)
15005 int size
= sizeof (MESSAGE_TEMPLATE
);
15006 int left
= *left_p
;
15008 /* Reserve 2 spaces for ", " or ",\0" */
15011 /* Check if there is any room. */
15019 p
= mempcpy (p
, name
, len
);
15023 /* Output the current message now and start a new one. */
15026 fprintf (stream
, "%s\n", message
);
15028 left
= size
- (start
- message
) - len
- 2;
15030 gas_assert (left
>= 0);
15032 p
= mempcpy (p
, name
, len
);
15040 show_arch (FILE *stream
, int ext
, int check
)
15042 static char message
[] = MESSAGE_TEMPLATE
;
15043 char *start
= message
+ 27;
15045 int size
= sizeof (MESSAGE_TEMPLATE
);
15052 left
= size
- (start
- message
);
15056 p
= output_message (stream
, p
, message
, start
, &left
,
15057 STRING_COMMA_LEN ("default"));
15058 p
= output_message (stream
, p
, message
, start
, &left
,
15059 STRING_COMMA_LEN ("push"));
15060 p
= output_message (stream
, p
, message
, start
, &left
,
15061 STRING_COMMA_LEN ("pop"));
15064 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15066 /* Should it be skipped? */
15067 if (cpu_arch
[j
].skip
)
15070 name
= cpu_arch
[j
].name
;
15071 len
= cpu_arch
[j
].len
;
15072 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
15074 /* It is an extension. Skip if we aren't asked to show it. */
15075 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15080 /* It is an processor. Skip if we show only extension. */
15083 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
15085 /* It is an impossible processor - skip. */
15089 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
15092 /* Display disabled extensions. */
15094 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15098 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
15099 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15101 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
15102 p
= output_message (stream
, p
, message
, start
, &left
, str
,
15108 fprintf (stream
, "%s\n", message
);
15112 md_show_usage (FILE *stream
)
15114 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15115 fprintf (stream
, _("\
15116 -Qy, -Qn ignored\n\
15117 -V print assembler version number\n\
15120 fprintf (stream
, _("\
15121 -n do not optimize code alignment\n\
15122 -O{012s} attempt some code optimizations\n\
15123 -q quieten some warnings\n"));
15124 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15125 fprintf (stream
, _("\
15129 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15130 fprintf (stream
, _("\
15131 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
15132 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
15133 fprintf (stream
, _("\
15134 --32/--64 generate 32bit/64bit object\n"));
15137 #ifdef SVR4_COMMENT_CHARS
15138 fprintf (stream
, _("\
15139 --divide do not treat `/' as a comment character\n"));
15141 fprintf (stream
, _("\
15142 --divide ignored\n"));
15144 fprintf (stream
, _("\
15145 -march=CPU[,+EXTENSION...]\n\
15146 generate code for CPU and EXTENSION, CPU is one of:\n"));
15147 show_arch (stream
, 0, 1);
15148 fprintf (stream
, _("\
15149 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
15150 show_arch (stream
, 1, 0);
15151 fprintf (stream
, _("\
15152 -mtune=CPU optimize for CPU, CPU is one of:\n"));
15153 show_arch (stream
, 0, 0);
15154 fprintf (stream
, _("\
15155 -msse2avx encode SSE instructions with VEX prefix\n"));
15156 fprintf (stream
, _("\
15157 -muse-unaligned-vector-move\n\
15158 encode aligned vector move as unaligned vector move\n"));
15159 fprintf (stream
, _("\
15160 -msse-check=[none|error|warning] (default: warning)\n\
15161 check SSE instructions\n"));
15162 fprintf (stream
, _("\
15163 -moperand-check=[none|error|warning] (default: warning)\n\
15164 check operand combinations for validity\n"));
15165 fprintf (stream
, _("\
15166 -mavxscalar=[128|256] (default: 128)\n\
15167 encode scalar AVX instructions with specific vector\n\
15169 fprintf (stream
, _("\
15170 -mvexwig=[0|1] (default: 0)\n\
15171 encode VEX instructions with specific VEX.W value\n\
15172 for VEX.W bit ignored instructions\n"));
15173 fprintf (stream
, _("\
15174 -mevexlig=[128|256|512] (default: 128)\n\
15175 encode scalar EVEX instructions with specific vector\n\
15177 fprintf (stream
, _("\
15178 -mevexwig=[0|1] (default: 0)\n\
15179 encode EVEX instructions with specific EVEX.W value\n\
15180 for EVEX.W bit ignored instructions\n"));
15181 fprintf (stream
, _("\
15182 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
15183 encode EVEX instructions with specific EVEX.RC value\n\
15184 for SAE-only ignored instructions\n"));
15185 fprintf (stream
, _("\
15186 -mmnemonic=[att|intel] "));
15187 if (SYSV386_COMPAT
)
15188 fprintf (stream
, _("(default: att)\n"));
15190 fprintf (stream
, _("(default: intel)\n"));
15191 fprintf (stream
, _("\
15192 use AT&T/Intel mnemonic\n"));
15193 fprintf (stream
, _("\
15194 -msyntax=[att|intel] (default: att)\n\
15195 use AT&T/Intel syntax\n"));
15196 fprintf (stream
, _("\
15197 -mindex-reg support pseudo index registers\n"));
15198 fprintf (stream
, _("\
15199 -mnaked-reg don't require `%%' prefix for registers\n"));
15200 fprintf (stream
, _("\
15201 -madd-bnd-prefix add BND prefix for all valid branches\n"));
15202 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15203 fprintf (stream
, _("\
15204 -mshared disable branch optimization for shared code\n"));
15205 fprintf (stream
, _("\
15206 -mx86-used-note=[no|yes] "));
15207 if (DEFAULT_X86_USED_NOTE
)
15208 fprintf (stream
, _("(default: yes)\n"));
15210 fprintf (stream
, _("(default: no)\n"));
15211 fprintf (stream
, _("\
15212 generate x86 used ISA and feature properties\n"));
15214 #if defined (TE_PE) || defined (TE_PEP)
15215 fprintf (stream
, _("\
15216 -mbig-obj generate big object files\n"));
15218 fprintf (stream
, _("\
15219 -momit-lock-prefix=[no|yes] (default: no)\n\
15220 strip all lock prefixes\n"));
15221 fprintf (stream
, _("\
15222 -mfence-as-lock-add=[no|yes] (default: no)\n\
15223 encode lfence, mfence and sfence as\n\
15224 lock addl $0x0, (%%{re}sp)\n"));
15225 fprintf (stream
, _("\
15226 -mrelax-relocations=[no|yes] "));
15227 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
15228 fprintf (stream
, _("(default: yes)\n"));
15230 fprintf (stream
, _("(default: no)\n"));
15231 fprintf (stream
, _("\
15232 generate relax relocations\n"));
15233 fprintf (stream
, _("\
15234 -malign-branch-boundary=NUM (default: 0)\n\
15235 align branches within NUM byte boundary\n"));
15236 fprintf (stream
, _("\
15237 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
15238 TYPE is combination of jcc, fused, jmp, call, ret,\n\
15240 specify types of branches to align\n"));
15241 fprintf (stream
, _("\
15242 -malign-branch-prefix-size=NUM (default: 5)\n\
15243 align branches with NUM prefixes per instruction\n"));
15244 fprintf (stream
, _("\
15245 -mbranches-within-32B-boundaries\n\
15246 align branches within 32 byte boundary\n"));
15247 fprintf (stream
, _("\
15248 -mlfence-after-load=[no|yes] (default: no)\n\
15249 generate lfence after load\n"));
15250 fprintf (stream
, _("\
15251 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
15252 generate lfence before indirect near branch\n"));
15253 fprintf (stream
, _("\
15254 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
15255 generate lfence before ret\n"));
15256 fprintf (stream
, _("\
15257 -mamd64 accept only AMD64 ISA [default]\n"));
15258 fprintf (stream
, _("\
15259 -mintel64 accept only Intel64 ISA\n"));
15262 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
15263 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
15264 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
15266 /* Pick the target format to use. */
15269 i386_target_format (void)
15271 if (startswith (default_arch
, "x86_64"))
15273 update_code_flag (CODE_64BIT
, 1);
15274 if (default_arch
[6] == '\0')
15275 x86_elf_abi
= X86_64_ABI
;
15277 x86_elf_abi
= X86_64_X32_ABI
;
15279 else if (!strcmp (default_arch
, "i386"))
15280 update_code_flag (CODE_32BIT
, 1);
15281 else if (!strcmp (default_arch
, "iamcu"))
15283 update_code_flag (CODE_32BIT
, 1);
15284 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
15286 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
15287 cpu_arch_name
= "iamcu";
15288 free (cpu_sub_arch_name
);
15289 cpu_sub_arch_name
= NULL
;
15290 cpu_arch_flags
= iamcu_flags
;
15291 cpu_arch_isa
= PROCESSOR_IAMCU
;
15292 cpu_arch_isa_flags
= iamcu_flags
;
15293 if (!cpu_arch_tune_set
)
15294 cpu_arch_tune
= PROCESSOR_IAMCU
;
15296 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
15297 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
15301 as_fatal (_("unknown architecture"));
15303 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
15304 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15306 switch (OUTPUT_FLAVOR
)
15308 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
15309 case bfd_target_aout_flavour
:
15310 return AOUT_TARGET_FORMAT
;
15312 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
15313 # if defined (TE_PE) || defined (TE_PEP)
15314 case bfd_target_coff_flavour
:
15315 if (flag_code
== CODE_64BIT
)
15318 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
15320 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
15321 # elif defined (TE_GO32)
15322 case bfd_target_coff_flavour
:
15323 return "coff-go32";
15325 case bfd_target_coff_flavour
:
15326 return "coff-i386";
15329 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15330 case bfd_target_elf_flavour
:
15332 const char *format
;
15334 switch (x86_elf_abi
)
15337 format
= ELF_TARGET_FORMAT
;
15339 tls_get_addr
= "___tls_get_addr";
15343 use_rela_relocations
= 1;
15346 tls_get_addr
= "__tls_get_addr";
15348 format
= ELF_TARGET_FORMAT64
;
15350 case X86_64_X32_ABI
:
15351 use_rela_relocations
= 1;
15354 tls_get_addr
= "__tls_get_addr";
15356 disallow_64bit_reloc
= 1;
15357 format
= ELF_TARGET_FORMAT32
;
15360 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
15362 if (x86_elf_abi
!= I386_ABI
)
15363 as_fatal (_("Intel MCU is 32bit only"));
15364 return ELF_TARGET_IAMCU_FORMAT
;
15370 #if defined (OBJ_MACH_O)
15371 case bfd_target_mach_o_flavour
:
15372 if (flag_code
== CODE_64BIT
)
15374 use_rela_relocations
= 1;
15376 return "mach-o-x86-64";
15379 return "mach-o-i386";
15387 #endif /* OBJ_MAYBE_ more than one */
15390 md_undefined_symbol (char *name
)
15392 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
15393 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
15394 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
15395 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
15399 if (symbol_find (name
))
15400 as_bad (_("GOT already in symbol table"));
15401 GOT_symbol
= symbol_new (name
, undefined_section
,
15402 &zero_address_frag
, 0);
15409 /* Round up a section size to the appropriate boundary. */
15412 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
15414 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
15415 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
15417 /* For a.out, force the section size to be aligned. If we don't do
15418 this, BFD will align it for us, but it will not write out the
15419 final bytes of the section. This may be a bug in BFD, but it is
15420 easier to fix it here since that is how the other a.out targets
15424 align
= bfd_section_alignment (segment
);
15425 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
15432 /* On the i386, PC-relative offsets are relative to the start of the
15433 next instruction. That is, the address of the offset, plus its
15434 size, since the offset is always the last part of the insn. */
15437 md_pcrel_from (fixS
*fixP
)
15439 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15445 s_bss (int ignore ATTRIBUTE_UNUSED
)
15449 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15451 obj_elf_section_change_hook ();
15453 temp
= get_absolute_expression ();
15454 subseg_set (bss_section
, (subsegT
) temp
);
15455 demand_empty_rest_of_line ();
15460 /* Remember constant directive. */
15463 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
15465 if (last_insn
.kind
!= last_insn_directive
15466 && (bfd_section_flags (now_seg
) & SEC_CODE
))
15468 last_insn
.seg
= now_seg
;
15469 last_insn
.kind
= last_insn_directive
;
15470 last_insn
.name
= "constant directive";
15471 last_insn
.file
= as_where (&last_insn
.line
);
15472 if (lfence_before_ret
!= lfence_before_ret_none
)
15474 if (lfence_before_indirect_branch
!= lfence_branch_none
)
15475 as_warn (_("constant directive skips -mlfence-before-ret "
15476 "and -mlfence-before-indirect-branch"));
15478 as_warn (_("constant directive skips -mlfence-before-ret"));
15480 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
15481 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
15486 i386_validate_fix (fixS
*fixp
)
15488 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
15490 reloc_howto_type
*howto
;
15492 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
15493 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15494 _("invalid %s relocation against register"),
15495 howto
? howto
->name
: "<unknown>");
15499 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15500 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15501 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
15502 return IS_ELF
&& fixp
->fx_addsy
15503 && (!S_IS_DEFINED (fixp
->fx_addsy
)
15504 || S_IS_EXTERNAL (fixp
->fx_addsy
));
15507 if (fixp
->fx_subsy
)
15509 if (fixp
->fx_subsy
== GOT_symbol
)
15511 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
15515 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15516 if (fixp
->fx_tcbit2
)
15517 fixp
->fx_r_type
= (fixp
->fx_tcbit
15518 ? BFD_RELOC_X86_64_REX_GOTPCRELX
15519 : BFD_RELOC_X86_64_GOTPCRELX
);
15522 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
15527 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
15529 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
15531 fixp
->fx_subsy
= 0;
15534 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15537 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
15538 to section. Since PLT32 relocation must be against symbols,
15539 turn such PLT32 relocation into PC32 relocation. */
15541 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
15542 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
15543 && symbol_section_p (fixp
->fx_addsy
))
15544 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
15547 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
15548 && fixp
->fx_tcbit2
)
15549 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
15558 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
15561 bfd_reloc_code_real_type code
;
15563 switch (fixp
->fx_r_type
)
15565 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15568 case BFD_RELOC_SIZE32
:
15569 case BFD_RELOC_SIZE64
:
15571 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
15572 && (!fixp
->fx_subsy
15573 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
15574 sym
= fixp
->fx_addsy
;
15575 else if (fixp
->fx_subsy
15576 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
15577 && (!fixp
->fx_addsy
15578 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
15579 sym
= fixp
->fx_subsy
;
15582 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
15584 /* Resolve size relocation against local symbol to size of
15585 the symbol plus addend. */
15586 valueT value
= S_GET_SIZE (sym
);
15588 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
15589 value
= bfd_section_size (S_GET_SEGMENT (sym
));
15590 if (sym
== fixp
->fx_subsy
)
15593 if (fixp
->fx_addsy
)
15594 value
+= S_GET_VALUE (fixp
->fx_addsy
);
15596 else if (fixp
->fx_subsy
)
15597 value
-= S_GET_VALUE (fixp
->fx_subsy
);
15598 value
+= fixp
->fx_offset
;
15599 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15601 && !fits_in_unsigned_long (value
))
15602 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15603 _("symbol size computation overflow"));
15604 fixp
->fx_addsy
= NULL
;
15605 fixp
->fx_subsy
= NULL
;
15606 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
15609 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
15611 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15612 "unsupported expression involving @size");
15616 /* Fall through. */
15618 case BFD_RELOC_X86_64_PLT32
:
15619 case BFD_RELOC_X86_64_GOT32
:
15620 case BFD_RELOC_X86_64_GOTPCREL
:
15621 case BFD_RELOC_X86_64_GOTPCRELX
:
15622 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15623 case BFD_RELOC_386_PLT32
:
15624 case BFD_RELOC_386_GOT32
:
15625 case BFD_RELOC_386_GOT32X
:
15626 case BFD_RELOC_386_GOTOFF
:
15627 case BFD_RELOC_386_GOTPC
:
15628 case BFD_RELOC_386_TLS_GD
:
15629 case BFD_RELOC_386_TLS_LDM
:
15630 case BFD_RELOC_386_TLS_LDO_32
:
15631 case BFD_RELOC_386_TLS_IE_32
:
15632 case BFD_RELOC_386_TLS_IE
:
15633 case BFD_RELOC_386_TLS_GOTIE
:
15634 case BFD_RELOC_386_TLS_LE_32
:
15635 case BFD_RELOC_386_TLS_LE
:
15636 case BFD_RELOC_386_TLS_GOTDESC
:
15637 case BFD_RELOC_386_TLS_DESC_CALL
:
15638 case BFD_RELOC_X86_64_TLSGD
:
15639 case BFD_RELOC_X86_64_TLSLD
:
15640 case BFD_RELOC_X86_64_DTPOFF32
:
15641 case BFD_RELOC_X86_64_DTPOFF64
:
15642 case BFD_RELOC_X86_64_GOTTPOFF
:
15643 case BFD_RELOC_X86_64_TPOFF32
:
15644 case BFD_RELOC_X86_64_TPOFF64
:
15645 case BFD_RELOC_X86_64_GOTOFF64
:
15646 case BFD_RELOC_X86_64_GOTPC32
:
15647 case BFD_RELOC_X86_64_GOT64
:
15648 case BFD_RELOC_X86_64_GOTPCREL64
:
15649 case BFD_RELOC_X86_64_GOTPC64
:
15650 case BFD_RELOC_X86_64_GOTPLT64
:
15651 case BFD_RELOC_X86_64_PLTOFF64
:
15652 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15653 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15654 case BFD_RELOC_RVA
:
15655 case BFD_RELOC_VTABLE_ENTRY
:
15656 case BFD_RELOC_VTABLE_INHERIT
:
15658 case BFD_RELOC_32_SECREL
:
15659 case BFD_RELOC_16_SECIDX
:
15661 code
= fixp
->fx_r_type
;
15663 case BFD_RELOC_X86_64_32S
:
15664 if (!fixp
->fx_pcrel
)
15666 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
15667 code
= fixp
->fx_r_type
;
15670 /* Fall through. */
15672 if (fixp
->fx_pcrel
)
15674 switch (fixp
->fx_size
)
15677 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15678 _("can not do %d byte pc-relative relocation"),
15680 code
= BFD_RELOC_32_PCREL
;
15682 case 1: code
= BFD_RELOC_8_PCREL
; break;
15683 case 2: code
= BFD_RELOC_16_PCREL
; break;
15684 case 4: code
= BFD_RELOC_32_PCREL
; break;
15686 case 8: code
= BFD_RELOC_64_PCREL
; break;
15692 switch (fixp
->fx_size
)
15695 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15696 _("can not do %d byte relocation"),
15698 code
= BFD_RELOC_32
;
15700 case 1: code
= BFD_RELOC_8
; break;
15701 case 2: code
= BFD_RELOC_16
; break;
15702 case 4: code
= BFD_RELOC_32
; break;
15704 case 8: code
= BFD_RELOC_64
; break;
15711 if ((code
== BFD_RELOC_32
15712 || code
== BFD_RELOC_32_PCREL
15713 || code
== BFD_RELOC_X86_64_32S
)
15715 && fixp
->fx_addsy
== GOT_symbol
)
15718 code
= BFD_RELOC_386_GOTPC
;
15720 code
= BFD_RELOC_X86_64_GOTPC32
;
15722 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
15724 && fixp
->fx_addsy
== GOT_symbol
)
15726 code
= BFD_RELOC_X86_64_GOTPC64
;
15729 rel
= XNEW (arelent
);
15730 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
15731 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
15733 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
15735 if (!use_rela_relocations
)
15737 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
15738 vtable entry to be used in the relocation's section offset. */
15739 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15740 rel
->address
= fixp
->fx_offset
;
15741 #if defined (OBJ_COFF) && defined (TE_PE)
15742 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
15743 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
15748 /* Use the rela in 64bit mode. */
15751 if (disallow_64bit_reloc
)
15754 case BFD_RELOC_X86_64_DTPOFF64
:
15755 case BFD_RELOC_X86_64_TPOFF64
:
15756 case BFD_RELOC_64_PCREL
:
15757 case BFD_RELOC_X86_64_GOTOFF64
:
15758 case BFD_RELOC_X86_64_GOT64
:
15759 case BFD_RELOC_X86_64_GOTPCREL64
:
15760 case BFD_RELOC_X86_64_GOTPC64
:
15761 case BFD_RELOC_X86_64_GOTPLT64
:
15762 case BFD_RELOC_X86_64_PLTOFF64
:
15763 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15764 _("cannot represent relocation type %s in x32 mode"),
15765 bfd_get_reloc_code_name (code
));
15771 if (!fixp
->fx_pcrel
)
15772 rel
->addend
= fixp
->fx_offset
;
15776 case BFD_RELOC_X86_64_PLT32
:
15777 case BFD_RELOC_X86_64_GOT32
:
15778 case BFD_RELOC_X86_64_GOTPCREL
:
15779 case BFD_RELOC_X86_64_GOTPCRELX
:
15780 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15781 case BFD_RELOC_X86_64_TLSGD
:
15782 case BFD_RELOC_X86_64_TLSLD
:
15783 case BFD_RELOC_X86_64_GOTTPOFF
:
15784 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15785 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15786 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
15789 rel
->addend
= (section
->vma
15791 + fixp
->fx_addnumber
15792 + md_pcrel_from (fixp
));
15797 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
15798 if (rel
->howto
== NULL
)
15800 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15801 _("cannot represent relocation type %s"),
15802 bfd_get_reloc_code_name (code
));
15803 /* Set howto to a garbage value so that we can keep going. */
15804 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
15805 gas_assert (rel
->howto
!= NULL
);
15811 #include "tc-i386-intel.c"
15814 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
15816 int saved_naked_reg
;
15817 char saved_register_dot
;
15819 saved_naked_reg
= allow_naked_reg
;
15820 allow_naked_reg
= 1;
15821 saved_register_dot
= register_chars
['.'];
15822 register_chars
['.'] = '.';
15823 allow_pseudo_reg
= 1;
15824 expression_and_evaluate (exp
);
15825 allow_pseudo_reg
= 0;
15826 register_chars
['.'] = saved_register_dot
;
15827 allow_naked_reg
= saved_naked_reg
;
15829 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
15831 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
15833 exp
->X_op
= O_constant
;
15834 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
15835 .dw2_regnum
[flag_code
>> 1];
15838 exp
->X_op
= O_illegal
;
15843 tc_x86_frame_initial_instructions (void)
15845 static unsigned int sp_regno
[2];
15847 if (!sp_regno
[flag_code
>> 1])
15849 char *saved_input
= input_line_pointer
;
15850 char sp
[][4] = {"esp", "rsp"};
15853 input_line_pointer
= sp
[flag_code
>> 1];
15854 tc_x86_parse_to_dw2regnum (&exp
);
15855 gas_assert (exp
.X_op
== O_constant
);
15856 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
15857 input_line_pointer
= saved_input
;
15860 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
15861 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
15865 x86_dwarf2_addr_size (void)
15867 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15868 if (x86_elf_abi
== X86_64_X32_ABI
)
15871 return bfd_arch_bits_per_address (stdoutput
) / 8;
15875 i386_elf_section_type (const char *str
, size_t len
)
15877 if (flag_code
== CODE_64BIT
15878 && len
== sizeof ("unwind") - 1
15879 && startswith (str
, "unwind"))
15880 return SHT_X86_64_UNWIND
;
15887 i386_solaris_fix_up_eh_frame (segT sec
)
15889 if (flag_code
== CODE_64BIT
)
15890 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
15896 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
15900 exp
.X_op
= O_secrel
;
15901 exp
.X_add_symbol
= symbol
;
15902 exp
.X_add_number
= 0;
15903 emit_expr (&exp
, size
);
15907 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15908 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
15911 x86_64_section_letter (int letter
, const char **ptr_msg
)
15913 if (flag_code
== CODE_64BIT
)
15916 return SHF_X86_64_LARGE
;
15918 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
15921 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
15926 handle_large_common (int small ATTRIBUTE_UNUSED
)
15928 if (flag_code
!= CODE_64BIT
)
15930 s_comm_internal (0, elf_common_parse
);
15931 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
15935 static segT lbss_section
;
15936 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15937 asection
*saved_bss_section
= bss_section
;
15939 if (lbss_section
== NULL
)
15941 flagword applicable
;
15942 segT seg
= now_seg
;
15943 subsegT subseg
= now_subseg
;
15945 /* The .lbss section is for local .largecomm symbols. */
15946 lbss_section
= subseg_new (".lbss", 0);
15947 applicable
= bfd_applicable_section_flags (stdoutput
);
15948 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15949 seg_info (lbss_section
)->bss
= 1;
15951 subseg_set (seg
, subseg
);
15954 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15955 bss_section
= lbss_section
;
15957 s_comm_internal (0, elf_common_parse
);
15959 elf_com_section_ptr
= saved_com_section_ptr
;
15960 bss_section
= saved_bss_section
;
15963 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */