1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 enum { vsz_none
, vsz_set
, vsz_reset
} vsz
; /* vector size control */
135 i386_cpu_flags enable
; /* cpu feature enable flags */
136 i386_cpu_flags disable
; /* cpu feature disable flags */
140 static void update_code_flag (int, int);
141 static void s_insn (int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
151 static void pe_directive_secidx (int);
153 static void signed_cons (int);
154 static char *output_invalid (int c
);
155 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
157 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
159 static int i386_att_operand (char *);
160 static int i386_intel_operand (char *, int);
161 static int i386_intel_simplify (expressionS
*);
162 static int i386_intel_parse_name (const char *, expressionS
*);
163 static const reg_entry
*parse_register (const char *, char **);
164 static const char *parse_insn (const char *, char *, bool);
165 static char *parse_operands (char *, const char *);
166 static void swap_operands (void);
167 static void swap_2_operands (unsigned int, unsigned int);
168 static enum i386_flag_code
i386_addressing_mode (void);
169 static void optimize_imm (void);
170 static bool optimize_disp (const insn_template
*t
);
171 static const insn_template
*match_template (char);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const reg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
190 /* GNU_PROPERTY_X86_ISA_1_USED. */
191 static unsigned int x86_isa_1_used
;
192 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
193 static unsigned int x86_feature_2_used
;
194 /* Generate x86 used ISA and feature properties. */
195 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
198 static const char *default_arch
= DEFAULT_ARCH
;
200 /* parse_register() returns this when a register alias cannot be used. */
201 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
202 { Dw2Inval
, Dw2Inval
} };
204 static const reg_entry
*reg_eax
;
205 static const reg_entry
*reg_ds
;
206 static const reg_entry
*reg_es
;
207 static const reg_entry
*reg_ss
;
208 static const reg_entry
*reg_st0
;
209 static const reg_entry
*reg_k0
;
214 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
215 unsigned char bytes
[4];
217 /* Destination or source register specifier. */
218 const reg_entry
*register_specifier
;
221 /* 'md_assemble ()' gathers together information and puts it into a
228 const reg_entry
*regs
;
233 no_error
, /* Must be first. */
234 operand_size_mismatch
,
235 operand_type_mismatch
,
236 register_type_mismatch
,
237 number_of_operands_mismatch
,
238 invalid_instruction_suffix
,
240 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 invalid_dest_and_src_register_set
,
250 unsupported_vector_index_register
,
251 unsupported_broadcast
,
254 mask_not_on_destination
,
257 invalid_register_operand
,
263 /* TM holds the template for the insn were currently assembling. */
266 /* SUFFIX holds the instruction size suffix for byte, word, dword
267 or qword, if given. */
270 /* OPCODE_LENGTH holds the number of base opcode bytes. */
271 unsigned char opcode_length
;
273 /* OPERANDS gives the number of given operands. */
274 unsigned int operands
;
276 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
277 of given register, displacement, memory operands and immediate
279 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
281 /* TYPES [i] is the type (see above #defines) which tells us how to
282 use OP[i] for the corresponding operand. */
283 i386_operand_type types
[MAX_OPERANDS
];
285 /* Displacement expression, immediate expression, or register for each
287 union i386_op op
[MAX_OPERANDS
];
289 /* Flags for operands. */
290 unsigned int flags
[MAX_OPERANDS
];
291 #define Operand_PCrel 1
292 #define Operand_Mem 2
293 #define Operand_Signed 4 /* .insn only */
295 /* Relocation type for operand */
296 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
298 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
299 the base index byte below. */
300 const reg_entry
*base_reg
;
301 const reg_entry
*index_reg
;
302 unsigned int log2_scale_factor
;
304 /* SEG gives the seg_entries of this insn. They are zero unless
305 explicit segment overrides are given. */
306 const reg_entry
*seg
[2];
308 /* PREFIX holds all the given prefix opcodes (usually null).
309 PREFIXES is the number of prefix opcodes. */
310 unsigned int prefixes
;
311 unsigned char prefix
[MAX_PREFIXES
];
313 /* .insn allows for reserved opcode spaces. */
314 unsigned char insn_opcode_space
;
316 /* .insn also allows (requires) specifying immediate size. */
317 unsigned char imm_bits
[MAX_OPERANDS
];
319 /* Register is in low 3 bits of opcode. */
322 /* The operand to a branch insn indicates an absolute branch. */
325 /* The operand to a branch insn indicates a far branch. */
328 /* There is a memory operand of (%dx) which should be only used
329 with input/output instructions. */
330 bool input_output_operand
;
332 /* Extended states. */
340 xstate_ymm
= 1 << 2 | xstate_xmm
,
342 xstate_zmm
= 1 << 3 | xstate_ymm
,
345 /* Use MASK state. */
349 /* Has GOTPC or TLS relocation. */
350 bool has_gotpc_tls_reloc
;
352 /* RM and SIB are the modrm byte and the sib byte where the
353 addressing modes of this insn are encoded. */
360 /* Masking attributes.
362 The struct describes masking, applied to OPERAND in the instruction.
363 REG is a pointer to the corresponding mask register. ZEROING tells
364 whether merging or zeroing mask is used. */
365 struct Mask_Operation
367 const reg_entry
*reg
;
368 unsigned int zeroing
;
369 /* The operand where this operation is associated. */
370 unsigned int operand
;
373 /* Rounding control and SAE attributes. */
385 /* In Intel syntax the operand modifier form is supposed to be used, but
386 we continue to accept the immediate forms as well. */
390 /* Broadcasting attributes.
392 The struct describes broadcasting, applied to OPERAND. TYPE is
393 expresses the broadcast factor. */
394 struct Broadcast_Operation
396 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
399 /* Index of broadcasted operand. */
400 unsigned int operand
;
402 /* Number of bytes to broadcast. */
406 /* Compressed disp8*N attribute. */
407 unsigned int memshift
;
409 /* Prefer load or store in encoding. */
412 dir_encoding_default
= 0,
418 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
421 disp_encoding_default
= 0,
427 /* Prefer the REX byte in encoding. */
430 /* Disable instruction size optimization. */
433 /* How to encode vector instructions. */
436 vex_encoding_default
= 0,
440 vex_encoding_evex512
,
445 const char *rep_prefix
;
448 const char *hle_prefix
;
450 /* Have BND prefix. */
451 const char *bnd_prefix
;
453 /* Have NOTRACK prefix. */
454 const char *notrack_prefix
;
457 enum i386_error error
;
460 typedef struct _i386_insn i386_insn
;
462 /* Link RC type with corresponding string, that'll be looked for in
471 static const struct RC_name RC_NamesTable
[] =
473 { rne
, STRING_COMMA_LEN ("rn-sae") },
474 { rd
, STRING_COMMA_LEN ("rd-sae") },
475 { ru
, STRING_COMMA_LEN ("ru-sae") },
476 { rz
, STRING_COMMA_LEN ("rz-sae") },
477 { saeonly
, STRING_COMMA_LEN ("sae") },
480 /* To be indexed by segment register number. */
481 static const unsigned char i386_seg_prefixes
[] = {
490 /* List of chars besides those in app.c:symbol_chars that can start an
491 operand. Used to prevent the scrubber eating vital white-space. */
492 const char extra_symbol_chars
[] = "*%-([{}"
501 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
502 && !defined (TE_GNU) \
503 && !defined (TE_LINUX) \
504 && !defined (TE_Haiku) \
505 && !defined (TE_FreeBSD) \
506 && !defined (TE_DragonFly) \
507 && !defined (TE_NetBSD))
508 /* This array holds the chars that always start a comment. If the
509 pre-processor is disabled, these aren't very useful. The option
510 --divide will remove '/' from this list. */
511 const char *i386_comment_chars
= "#/";
512 #define SVR4_COMMENT_CHARS 1
513 #define PREFIX_SEPARATOR '\\'
516 const char *i386_comment_chars
= "#";
517 #define PREFIX_SEPARATOR '/'
520 /* This array holds the chars that only start a comment at the beginning of
521 a line. If the line seems to have the form '# 123 filename'
522 .line and .file directives will appear in the pre-processed output.
523 Note that input_file.c hand checks for '#' at the beginning of the
524 first line of the input file. This is because the compiler outputs
525 #NO_APP at the beginning of its output.
526 Also note that comments started like this one will always work if
527 '/' isn't otherwise defined. */
528 const char line_comment_chars
[] = "#/";
530 const char line_separator_chars
[] = ";";
532 /* Chars that can be used to separate mant from exp in floating point
534 const char EXP_CHARS
[] = "eE";
536 /* Chars that mean this number is a floating point constant
539 const char FLT_CHARS
[] = "fFdDxXhHbB";
541 /* Tables for lexical analysis. */
542 static char mnemonic_chars
[256];
543 static char register_chars
[256];
544 static char operand_chars
[256];
546 /* Lexical macros. */
547 #define is_operand_char(x) (operand_chars[(unsigned char) x])
548 #define is_register_char(x) (register_chars[(unsigned char) x])
549 #define is_space_char(x) ((x) == ' ')
551 /* All non-digit non-letter characters that may occur in an operand and
552 which aren't already in extra_symbol_chars[]. */
553 static const char operand_special_chars
[] = "$+,)._~/<>|&^!=:@]";
555 /* md_assemble() always leaves the strings it's passed unaltered. To
556 effect this we maintain a stack of saved characters that we've smashed
557 with '\0's (indicating end of strings for various sub-fields of the
558 assembler instruction). */
559 static char save_stack
[32];
560 static char *save_stack_p
;
561 #define END_STRING_AND_SAVE(s) \
562 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
563 #define RESTORE_END_STRING(s) \
564 do { *(s) = *--save_stack_p; } while (0)
566 /* The instruction we're assembling. */
569 /* Possible templates for current insn. */
570 static const templates
*current_templates
;
572 /* Per instruction expressionS buffers: max displacements & immediates. */
573 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
574 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
576 /* Current operand we are working on. */
577 static int this_operand
= -1;
579 /* Are we processing a .insn directive? */
580 #define dot_insn() (i.tm.mnem_off == MN__insn)
582 enum i386_flag_code i386_flag_code
;
583 #define flag_code i386_flag_code /* Permit to continue using original name. */
584 static unsigned int object_64bit
;
585 static unsigned int disallow_64bit_reloc
;
586 static int use_rela_relocations
= 0;
587 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
588 static const char *tls_get_addr
;
590 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
591 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
592 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
594 /* The ELF ABI to use. */
602 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
605 #if defined (TE_PE) || defined (TE_PEP)
606 /* Use big object file format. */
607 static int use_big_obj
= 0;
610 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
611 /* 1 if generating code for a shared library. */
612 static int shared
= 0;
614 unsigned int x86_sframe_cfa_sp_reg
;
615 /* The other CFA base register for SFrame stack trace info. */
616 unsigned int x86_sframe_cfa_fp_reg
;
617 unsigned int x86_sframe_cfa_ra_reg
;
621 /* 1 for intel syntax,
623 static int intel_syntax
= 0;
625 static enum x86_64_isa
627 amd64
= 1, /* AMD64 ISA. */
628 intel64
/* Intel64 ISA. */
631 /* 1 for intel mnemonic,
632 0 if att mnemonic. */
633 static int intel_mnemonic
= !SYSV386_COMPAT
;
635 /* 1 if pseudo registers are permitted. */
636 static int allow_pseudo_reg
= 0;
638 /* 1 if register prefix % not required. */
639 static int allow_naked_reg
= 0;
641 /* 1 if the assembler should add BND prefix for all control-transferring
642 instructions supporting it, even if this prefix wasn't specified
644 static int add_bnd_prefix
= 0;
646 /* 1 if pseudo index register, eiz/riz, is allowed . */
647 static int allow_index_reg
= 0;
649 /* 1 if the assembler should ignore LOCK prefix, even if it was
650 specified explicitly. */
651 static int omit_lock_prefix
= 0;
653 /* 1 if the assembler should encode lfence, mfence, and sfence as
654 "lock addl $0, (%{re}sp)". */
655 static int avoid_fence
= 0;
657 /* 1 if lfence should be inserted after every load. */
658 static int lfence_after_load
= 0;
660 /* Non-zero if lfence should be inserted before indirect branch. */
661 static enum lfence_before_indirect_branch_kind
663 lfence_branch_none
= 0,
664 lfence_branch_register
,
665 lfence_branch_memory
,
668 lfence_before_indirect_branch
;
670 /* Non-zero if lfence should be inserted before ret. */
671 static enum lfence_before_ret_kind
673 lfence_before_ret_none
= 0,
674 lfence_before_ret_not
,
675 lfence_before_ret_or
,
676 lfence_before_ret_shl
680 /* Types of previous instruction is .byte or prefix. */
695 /* 1 if the assembler should generate relax relocations. */
697 static int generate_relax_relocations
698 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
700 static enum check_kind
706 sse_check
, operand_check
= check_warning
;
708 /* Non-zero if branches should be aligned within power of 2 boundary. */
709 static int align_branch_power
= 0;
711 /* Types of branches to align. */
712 enum align_branch_kind
714 align_branch_none
= 0,
715 align_branch_jcc
= 1,
716 align_branch_fused
= 2,
717 align_branch_jmp
= 3,
718 align_branch_call
= 4,
719 align_branch_indirect
= 5,
723 /* Type bits of branches to align. */
724 enum align_branch_bit
726 align_branch_jcc_bit
= 1 << align_branch_jcc
,
727 align_branch_fused_bit
= 1 << align_branch_fused
,
728 align_branch_jmp_bit
= 1 << align_branch_jmp
,
729 align_branch_call_bit
= 1 << align_branch_call
,
730 align_branch_indirect_bit
= 1 << align_branch_indirect
,
731 align_branch_ret_bit
= 1 << align_branch_ret
734 static unsigned int align_branch
= (align_branch_jcc_bit
735 | align_branch_fused_bit
736 | align_branch_jmp_bit
);
738 /* Types of condition jump used by macro-fusion. */
741 mf_jcc_jo
= 0, /* base opcode 0x70 */
742 mf_jcc_jc
, /* base opcode 0x72 */
743 mf_jcc_je
, /* base opcode 0x74 */
744 mf_jcc_jna
, /* base opcode 0x76 */
745 mf_jcc_js
, /* base opcode 0x78 */
746 mf_jcc_jp
, /* base opcode 0x7a */
747 mf_jcc_jl
, /* base opcode 0x7c */
748 mf_jcc_jle
, /* base opcode 0x7e */
751 /* Types of compare flag-modifying insntructions used by macro-fusion. */
754 mf_cmp_test_and
, /* test/cmp */
755 mf_cmp_alu_cmp
, /* add/sub/cmp */
756 mf_cmp_incdec
/* inc/dec */
759 /* The maximum padding size for fused jcc. CMP like instruction can
760 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
762 #define MAX_FUSED_JCC_PADDING_SIZE 20
764 /* The maximum number of prefixes added for an instruction. */
765 static unsigned int align_branch_prefix_size
= 5;
768 1. Clear the REX_W bit with register operand if possible.
769 2. Above plus use 128bit vector instruction to clear the full vector
772 static int optimize
= 0;
775 1. Clear the REX_W bit with register operand if possible.
776 2. Above plus use 128bit vector instruction to clear the full vector
778 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
781 static int optimize_for_space
= 0;
783 /* Register prefix used for error message. */
784 static const char *register_prefix
= "%";
786 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
787 leave, push, and pop instructions so that gcc has the same stack
788 frame as in 32 bit mode. */
789 static char stackop_size
= '\0';
791 /* Non-zero to optimize code alignment. */
792 int optimize_align_code
= 1;
794 /* Non-zero to quieten some warnings. */
795 static int quiet_warnings
= 0;
797 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
798 static bool pre_386_16bit_warned
;
801 static const char *cpu_arch_name
= NULL
;
802 static char *cpu_sub_arch_name
= NULL
;
804 /* CPU feature flags. */
805 i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
807 /* If we have selected a cpu we are generating instructions for. */
808 static int cpu_arch_tune_set
= 0;
810 /* Cpu we are generating instructions for. */
811 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
813 /* CPU instruction set architecture used. */
814 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
816 /* CPU feature flags of instruction set architecture used. */
817 i386_cpu_flags cpu_arch_isa_flags
;
819 /* If set, conditional jumps are not automatically promoted to handle
820 larger than a byte offset. */
821 static bool no_cond_jump_promotion
= false;
823 /* This will be set from an expression parser hook if there's any
824 applicable operator involved in an expression. */
827 expr_operator_present
,
831 /* Encode SSE instructions with VEX prefix. */
832 static unsigned int sse2avx
;
834 /* Encode aligned vector move as unaligned vector move. */
835 static unsigned int use_unaligned_vector_move
;
837 /* Maximum permitted vector size. */
838 #define VSZ_DEFAULT VSZ512
839 static unsigned int vector_size
= VSZ_DEFAULT
;
841 /* Encode scalar AVX instructions with specific vector length. */
848 /* Encode VEX WIG instructions with specific vex.w. */
855 /* Encode scalar EVEX LIG instructions with specific vector length. */
863 /* Encode EVEX WIG instructions with specific evex.w. */
870 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
871 static enum rc_type evexrcig
= rne
;
873 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
874 static symbolS
*GOT_symbol
;
876 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
877 unsigned int x86_dwarf2_return_column
;
879 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
880 int x86_cie_data_alignment
;
882 /* Interface to relax_segment.
883 There are 3 major relax states for 386 jump insns because the
884 different types of jumps add different sizes to frags when we're
885 figuring out what sort of jump to choose to reach a given label.
887 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
888 branches which are handled by md_estimate_size_before_relax() and
889 i386_generic_table_relax_frag(). */
892 #define UNCOND_JUMP 0
894 #define COND_JUMP86 2
895 #define BRANCH_PADDING 3
896 #define BRANCH_PREFIX 4
897 #define FUSED_JCC_PADDING 5
902 #define SMALL16 (SMALL | CODE16)
904 #define BIG16 (BIG | CODE16)
908 #define INLINE __inline__
914 #define ENCODE_RELAX_STATE(type, size) \
915 ((relax_substateT) (((type) << 2) | (size)))
916 #define TYPE_FROM_RELAX_STATE(s) \
918 #define DISP_SIZE_FROM_RELAX_STATE(s) \
919 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
921 /* This table is used by relax_frag to promote short jumps to long
922 ones where necessary. SMALL (short) jumps may be promoted to BIG
923 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
924 don't allow a short jump in a 32 bit code segment to be promoted to
925 a 16 bit offset jump because it's slower (requires data size
926 prefix), and doesn't work, unless the destination is in the bottom
927 64k of the code segment (The top 16 bits of eip are zeroed). */
929 const relax_typeS md_relax_table
[] =
932 1) most positive reach of this state,
933 2) most negative reach of this state,
934 3) how many bytes this mode will have in the variable part of the frag
935 4) which index into the table to try if we can't fit into this one. */
937 /* UNCOND_JUMP states. */
938 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
939 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
940 /* dword jmp adds 4 bytes to frag:
941 0 extra opcode bytes, 4 displacement bytes. */
943 /* word jmp adds 2 byte2 to frag:
944 0 extra opcode bytes, 2 displacement bytes. */
947 /* COND_JUMP states. */
948 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
949 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
950 /* dword conditionals adds 5 bytes to frag:
951 1 extra opcode byte, 4 displacement bytes. */
953 /* word conditionals add 3 bytes to frag:
954 1 extra opcode byte, 2 displacement bytes. */
957 /* COND_JUMP86 states. */
958 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
959 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
960 /* dword conditionals adds 5 bytes to frag:
961 1 extra opcode byte, 4 displacement bytes. */
963 /* word conditionals add 4 bytes to frag:
964 1 displacement byte and a 3 byte long branch insn. */
968 #define ARCH(n, t, f, s) \
969 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
971 #define SUBARCH(n, e, d, s) \
972 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
973 CPU_ ## d ## _FLAGS }
974 #define VECARCH(n, e, d, v) \
975 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
976 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
978 static const arch_entry cpu_arch
[] =
980 /* Do not replace the first two entries - i386_target_format() and
981 set_cpu_arch() rely on them being there in this order. */
982 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
983 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
984 ARCH (i8086
, UNKNOWN
, NONE
, false),
985 ARCH (i186
, UNKNOWN
, 186, false),
986 ARCH (i286
, UNKNOWN
, 286, false),
987 ARCH (i386
, I386
, 386, false),
988 ARCH (i486
, I486
, 486, false),
989 ARCH (i586
, PENTIUM
, 586, false),
990 ARCH (pentium
, PENTIUM
, 586, false),
991 ARCH (i686
, I686
, 686, false),
992 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
993 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
994 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
995 ARCH (pentium4
, PENTIUM4
, P4
, false),
996 ARCH (prescott
, NOCONA
, CORE
, false),
997 ARCH (nocona
, NOCONA
, NOCONA
, false),
998 ARCH (yonah
, CORE
, CORE
, true),
999 ARCH (core
, CORE
, CORE
, false),
1000 ARCH (merom
, CORE2
, CORE2
, true),
1001 ARCH (core2
, CORE2
, CORE2
, false),
1002 ARCH (corei7
, COREI7
, COREI7
, false),
1003 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1004 ARCH (k6
, K6
, K6
, false),
1005 ARCH (k6_2
, K6
, K6_2
, false),
1006 ARCH (athlon
, ATHLON
, ATHLON
, false),
1007 ARCH (sledgehammer
, K8
, K8
, true),
1008 ARCH (opteron
, K8
, K8
, false),
1009 ARCH (k8
, K8
, K8
, false),
1010 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1011 ARCH (bdver1
, BD
, BDVER1
, false),
1012 ARCH (bdver2
, BD
, BDVER2
, false),
1013 ARCH (bdver3
, BD
, BDVER3
, false),
1014 ARCH (bdver4
, BD
, BDVER4
, false),
1015 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1016 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1017 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1018 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1019 ARCH (btver1
, BT
, BTVER1
, false),
1020 ARCH (btver2
, BT
, BTVER2
, false),
1022 SUBARCH (8087, 8087, ANY_8087
, false),
1023 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1024 SUBARCH (287, 287, ANY_287
, false),
1025 SUBARCH (387, 387, ANY_387
, false),
1026 SUBARCH (687, 687, ANY_687
, false),
1027 SUBARCH (cmov
, CMOV
, CMOV
, false),
1028 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1029 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1030 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1031 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1032 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1033 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1034 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1035 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1036 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1037 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1038 VECARCH (avx
, AVX
, ANY_AVX
, reset
),
1039 VECARCH (avx2
, AVX2
, ANY_AVX2
, reset
),
1040 VECARCH (avx512f
, AVX512F
, ANY_AVX512F
, reset
),
1041 VECARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, reset
),
1042 VECARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, reset
),
1043 VECARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, reset
),
1044 VECARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, reset
),
1045 VECARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, reset
),
1046 VECARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, reset
),
1047 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1048 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1049 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1050 SUBARCH (smx
, SMX
, SMX
, false),
1051 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1052 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1053 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1054 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1055 SUBARCH (aes
, AES
, ANY_AES
, false),
1056 SUBARCH (pclmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, false),
1057 SUBARCH (clmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, true),
1058 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1059 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1060 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1061 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1062 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1063 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1064 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1065 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1066 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1067 SUBARCH (cx16
, CX16
, CX16
, false),
1068 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1069 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1070 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1071 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1072 SUBARCH (hle
, HLE
, HLE
, false),
1073 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1074 SUBARCH (tsx
, TSX
, TSX
, false),
1075 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1076 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1077 SUBARCH (nop
, NOP
, NOP
, false),
1078 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1079 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1080 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1081 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1082 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1083 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1084 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1085 SUBARCH (abm
, ABM
, ABM
, false),
1086 SUBARCH (bmi
, BMI
, BMI
, false),
1087 SUBARCH (tbm
, TBM
, TBM
, false),
1088 SUBARCH (adx
, ADX
, ADX
, false),
1089 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1090 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1091 SUBARCH (smap
, SMAP
, SMAP
, false),
1092 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1093 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1094 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1095 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1096 SUBARCH (se1
, SE1
, SE1
, false),
1097 SUBARCH (clwb
, CLWB
, CLWB
, false),
1098 VECARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, reset
),
1099 VECARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, reset
),
1100 VECARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, reset
),
1101 VECARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, reset
),
1102 VECARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, reset
),
1103 VECARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, reset
),
1104 VECARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, reset
),
1105 VECARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, reset
),
1106 VECARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, reset
),
1107 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1108 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1109 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1110 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1111 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1112 SUBARCH (ibt
, IBT
, IBT
, false),
1113 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1114 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1115 VECARCH (vaes
, VAES
, ANY_VAES
, reset
),
1116 VECARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, reset
),
1117 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1118 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1119 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1120 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1121 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1122 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1123 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1124 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1125 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1126 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1127 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1128 VECARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, reset
),
1129 VECARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1130 ANY_AVX512_VP2INTERSECT
, reset
),
1131 SUBARCH (tdx
, TDX
, TDX
, false),
1132 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1133 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1134 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1135 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1136 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1137 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1138 SUBARCH (kl
, KL
, ANY_KL
, false),
1139 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1140 SUBARCH (uintr
, UINTR
, UINTR
, false),
1141 SUBARCH (hreset
, HRESET
, HRESET
, false),
1142 VECARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, reset
),
1143 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1144 VECARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, reset
),
1145 VECARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, reset
),
1146 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1147 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1148 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1149 VECARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, reset
),
1150 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1151 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1152 SUBARCH (fred
, FRED
, ANY_FRED
, false),
1153 SUBARCH (lkgs
, LKGS
, ANY_LKGS
, false),
1154 VECARCH (avx_vnni_int16
, AVX_VNNI_INT16
, ANY_AVX_VNNI_INT16
, reset
),
1155 VECARCH (sha512
, SHA512
, ANY_SHA512
, reset
),
1156 VECARCH (sm3
, SM3
, ANY_SM3
, reset
),
1157 VECARCH (sm4
, SM4
, ANY_SM4
, reset
),
1158 SUBARCH (pbndkb
, PBNDKB
, PBNDKB
, false),
1159 VECARCH (avx10
.1
, AVX10_1
, ANY_AVX512F
, set
),
1160 SUBARCH (user_msr
, USER_MSR
, USER_MSR
, false),
1167 /* Like s_lcomm_internal in gas/read.c but the alignment string
1168 is allowed to be optional. */
1171 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1178 && *input_line_pointer
== ',')
1180 align
= parse_align (needs_align
- 1);
1182 if (align
== (addressT
) -1)
1197 bss_alloc (symbolP
, size
, align
);
1202 pe_lcomm (int needs_align
)
1204 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1208 const pseudo_typeS md_pseudo_table
[] =
1210 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1211 {"align", s_align_bytes
, 0},
1213 {"align", s_align_ptwo
, 0},
1215 {"arch", set_cpu_arch
, 0},
1219 {"lcomm", pe_lcomm
, 1},
1221 {"ffloat", float_cons
, 'f'},
1222 {"dfloat", float_cons
, 'd'},
1223 {"tfloat", float_cons
, 'x'},
1224 {"hfloat", float_cons
, 'h'},
1225 {"bfloat16", float_cons
, 'b'},
1227 {"slong", signed_cons
, 4},
1228 {"insn", s_insn
, 0},
1229 {"noopt", s_ignore
, 0},
1230 {"optim", s_ignore
, 0},
1231 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1232 {"code16", set_code_flag
, CODE_16BIT
},
1233 {"code32", set_code_flag
, CODE_32BIT
},
1235 {"code64", set_code_flag
, CODE_64BIT
},
1237 {"intel_syntax", set_intel_syntax
, 1},
1238 {"att_syntax", set_intel_syntax
, 0},
1239 {"intel_mnemonic", set_intel_mnemonic
, 1},
1240 {"att_mnemonic", set_intel_mnemonic
, 0},
1241 {"allow_index_reg", set_allow_index_reg
, 1},
1242 {"disallow_index_reg", set_allow_index_reg
, 0},
1243 {"sse_check", set_check
, 0},
1244 {"operand_check", set_check
, 1},
1245 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1246 {"largecomm", handle_large_common
, 0},
1248 {"file", dwarf2_directive_file
, 0},
1249 {"loc", dwarf2_directive_loc
, 0},
1250 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1253 {"secrel32", pe_directive_secrel
, 0},
1254 {"secidx", pe_directive_secidx
, 0},
1259 /* For interface with expression (). */
1260 extern char *input_line_pointer
;
1262 /* Hash table for instruction mnemonic lookup. */
1263 static htab_t op_hash
;
1265 /* Hash table for register lookup. */
1266 static htab_t reg_hash
;
1268 /* Various efficient no-op patterns for aligning code labels.
1269 Note: Don't try to assemble the instructions in the comments.
1270 0L and 0w are not legal. */
1271 static const unsigned char f32_1
[] =
1273 static const unsigned char f32_2
[] =
1274 {0x66,0x90}; /* xchg %ax,%ax */
1275 static const unsigned char f32_3
[] =
1276 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1277 #define f32_4 (f32_5 + 1) /* leal 0(%esi,%eiz),%esi */
1278 static const unsigned char f32_5
[] =
1279 {0x2e,0x8d,0x74,0x26,0x00}; /* leal %cs:0(%esi,%eiz),%esi */
1280 static const unsigned char f32_6
[] =
1281 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1282 #define f32_7 (f32_8 + 1) /* leal 0L(%esi,%eiz),%esi */
1283 static const unsigned char f32_8
[] =
1284 {0x2e,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal %cs:0L(%esi,%eiz),%esi */
1285 static const unsigned char f64_3
[] =
1286 {0x48,0x89,0xf6}; /* mov %rsi,%rsi */
1287 static const unsigned char f64_4
[] =
1288 {0x48,0x8d,0x76,0x00}; /* lea 0(%rsi),%rsi */
1289 #define f64_5 (f64_6 + 1) /* lea 0(%rsi,%riz),%rsi */
1290 static const unsigned char f64_6
[] =
1291 {0x2e,0x48,0x8d,0x74,0x26,0x00}; /* lea %cs:0(%rsi,%riz),%rsi */
1292 static const unsigned char f64_7
[] =
1293 {0x48,0x8d,0xb6,0x00,0x00,0x00,0x00}; /* lea 0L(%rsi),%rsi */
1294 #define f64_8 (f64_9 + 1) /* lea 0L(%rsi,%riz),%rsi */
1295 static const unsigned char f64_9
[] =
1296 {0x2e,0x48,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* lea %cs:0L(%rsi,%riz),%rsi */
1297 #define f16_2 (f64_3 + 1) /* mov %si,%si */
1298 static const unsigned char f16_3
[] =
1299 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1300 #define f16_4 (f16_5 + 1) /* lea 0W(%si),%si */
1301 static const unsigned char f16_5
[] =
1302 {0x2e,0x8d,0xb4,0x00,0x00}; /* lea %cs:0W(%si),%si */
1303 static const unsigned char jump_disp8
[] =
1304 {0xeb}; /* jmp disp8 */
1305 static const unsigned char jump32_disp32
[] =
1306 {0xe9}; /* jmp disp32 */
1307 static const unsigned char jump16_disp32
[] =
1308 {0x66,0xe9}; /* jmp disp32 */
1309 /* 32-bit NOPs patterns. */
1310 static const unsigned char *const f32_patt
[] = {
1311 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
1313 /* 64-bit NOPs patterns. */
1314 static const unsigned char *const f64_patt
[] = {
1315 f32_1
, f32_2
, f64_3
, f64_4
, f64_5
, f64_6
, f64_7
, f64_8
, f64_9
1317 /* 16-bit NOPs patterns. */
1318 static const unsigned char *const f16_patt
[] = {
1319 f32_1
, f16_2
, f16_3
, f16_4
, f16_5
1321 /* nopl (%[re]ax) */
1322 static const unsigned char alt_3
[] =
1324 /* nopl 0(%[re]ax) */
1325 static const unsigned char alt_4
[] =
1326 {0x0f,0x1f,0x40,0x00};
1327 /* nopl 0(%[re]ax,%[re]ax,1) */
1328 #define alt_5 (alt_6 + 1)
1329 /* nopw 0(%[re]ax,%[re]ax,1) */
1330 static const unsigned char alt_6
[] =
1331 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1332 /* nopl 0L(%[re]ax) */
1333 static const unsigned char alt_7
[] =
1334 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1335 /* nopl 0L(%[re]ax,%[re]ax,1) */
1336 #define alt_8 (alt_9 + 1)
1337 /* nopw 0L(%[re]ax,%[re]ax,1) */
1338 static const unsigned char alt_9
[] =
1339 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1340 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1341 #define alt_10 (alt_11 + 1)
1342 /* data16 nopw %cs:0L(%eax,%eax,1) */
1343 static const unsigned char alt_11
[] =
1344 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1345 /* 32-bit and 64-bit NOPs patterns. */
1346 static const unsigned char *const alt_patt
[] = {
1347 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1348 alt_9
, alt_10
, alt_11
1351 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1352 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1355 i386_output_nops (char *where
, const unsigned char *const *patt
,
1356 int count
, int max_single_nop_size
)
1359 /* Place the longer NOP first. */
1362 const unsigned char *nops
;
1364 if (max_single_nop_size
< 1)
1366 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1367 max_single_nop_size
);
1371 nops
= patt
[max_single_nop_size
- 1];
1372 last
= count
% max_single_nop_size
;
1375 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1376 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1380 nops
= patt
[last
- 1];
1381 memcpy (where
+ offset
, nops
, last
);
1386 fits_in_imm7 (offsetT num
)
1388 return (num
& 0x7f) == num
;
1392 fits_in_imm31 (offsetT num
)
1394 return (num
& 0x7fffffff) == num
;
1397 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1398 single NOP instruction LIMIT. */
1401 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1403 const unsigned char *const *patt
= NULL
;
1404 int max_single_nop_size
;
1405 /* Maximum number of NOPs before switching to jump over NOPs. */
1406 int max_number_of_nops
;
1408 switch (fragP
->fr_type
)
1413 case rs_machine_dependent
:
1414 /* Allow NOP padding for jumps and calls. */
1415 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1416 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1423 /* We need to decide which NOP sequence to use for 32bit and
1424 64bit. When -mtune= is used:
1426 1. For PROCESSOR_I?86, PROCESSOR_PENTIUM, PROCESSOR_IAMCU, and
1427 PROCESSOR_GENERIC32, f32_patt will be used.
1428 2. For the rest, alt_patt will be used.
1430 When -mtune= isn't used, alt_patt will be used if
1431 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt/f64_patt will
1434 When -march= or .arch is used, we can't use anything beyond
1435 cpu_arch_isa_flags. */
1437 if (fragP
->tc_frag_data
.code
== CODE_16BIT
)
1440 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1441 /* Limit number of NOPs to 2 in 16-bit mode. */
1442 max_number_of_nops
= 2;
1446 patt
= fragP
->tc_frag_data
.code
== CODE_64BIT
? f64_patt
: f32_patt
;
1447 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1449 /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless
1450 explicitly disabled. */
1451 switch (fragP
->tc_frag_data
.tune
)
1453 case PROCESSOR_UNKNOWN
:
1454 /* We use cpu_arch_isa_flags to check if we SHOULD
1455 optimize with nops. */
1456 if (fragP
->tc_frag_data
.isanop
)
1460 case PROCESSOR_PENTIUMPRO
:
1461 case PROCESSOR_PENTIUM4
:
1462 case PROCESSOR_NOCONA
:
1463 case PROCESSOR_CORE
:
1464 case PROCESSOR_CORE2
:
1465 case PROCESSOR_COREI7
:
1466 case PROCESSOR_GENERIC64
:
1468 case PROCESSOR_ATHLON
:
1470 case PROCESSOR_AMDFAM10
:
1472 case PROCESSOR_ZNVER
:
1474 if (fragP
->tc_frag_data
.cpunop
)
1478 case PROCESSOR_I386
:
1479 case PROCESSOR_I486
:
1480 case PROCESSOR_PENTIUM
:
1481 case PROCESSOR_I686
:
1482 case PROCESSOR_IAMCU
:
1483 case PROCESSOR_GENERIC32
:
1485 case PROCESSOR_NONE
:
1491 switch (fragP
->tc_frag_data
.tune
)
1493 case PROCESSOR_UNKNOWN
:
1494 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1495 PROCESSOR_UNKNOWN. */
1500 /* We use cpu_arch_isa_flags to check if we CAN optimize
1502 if (fragP
->tc_frag_data
.isanop
)
1506 case PROCESSOR_NONE
:
1511 if (patt
!= alt_patt
)
1513 max_single_nop_size
= patt
== f32_patt
? ARRAY_SIZE (f32_patt
)
1514 : ARRAY_SIZE (f64_patt
);
1515 /* Limit number of NOPs to 2 for older processors. */
1516 max_number_of_nops
= 2;
1520 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1521 /* Limit number of NOPs to 7 for newer processors. */
1522 max_number_of_nops
= 7;
1527 limit
= max_single_nop_size
;
1529 if (fragP
->fr_type
== rs_fill_nop
)
1531 /* Output NOPs for .nop directive. */
1532 if (limit
> max_single_nop_size
)
1534 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1535 _("invalid single nop size: %d "
1536 "(expect within [0, %d])"),
1537 limit
, max_single_nop_size
);
1541 else if (fragP
->fr_type
!= rs_machine_dependent
)
1542 fragP
->fr_var
= count
;
1544 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1546 /* Generate jump over NOPs. */
1547 offsetT disp
= count
- 2;
1548 if (fits_in_imm7 (disp
))
1550 /* Use "jmp disp8" if possible. */
1552 where
[0] = jump_disp8
[0];
1558 unsigned int size_of_jump
;
1560 if (flag_code
== CODE_16BIT
)
1562 where
[0] = jump16_disp32
[0];
1563 where
[1] = jump16_disp32
[1];
1568 where
[0] = jump32_disp32
[0];
1572 count
-= size_of_jump
+ 4;
1573 if (!fits_in_imm31 (count
))
1575 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1576 _("jump over nop padding out of range"));
1580 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1581 where
+= size_of_jump
+ 4;
1585 /* Generate multiple NOPs. */
1586 i386_output_nops (where
, patt
, count
, limit
);
1590 operand_type_all_zero (const union i386_operand_type
*x
)
1592 switch (ARRAY_SIZE(x
->array
))
1603 return !x
->array
[0];
1610 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1612 switch (ARRAY_SIZE(x
->array
))
1628 x
->bitfield
.class = ClassNone
;
1629 x
->bitfield
.instance
= InstanceNone
;
1633 operand_type_equal (const union i386_operand_type
*x
,
1634 const union i386_operand_type
*y
)
1636 switch (ARRAY_SIZE(x
->array
))
1639 if (x
->array
[2] != y
->array
[2])
1643 if (x
->array
[1] != y
->array
[1])
1647 return x
->array
[0] == y
->array
[0];
1655 is_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1659 case Cpu287
: return t
->cpu
.bitfield
.cpu287
;
1660 case Cpu387
: return t
->cpu
.bitfield
.cpu387
;
1661 case Cpu3dnow
: return t
->cpu
.bitfield
.cpu3dnow
;
1662 case Cpu3dnowA
: return t
->cpu
.bitfield
.cpu3dnowa
;
1663 case CpuAVX
: return t
->cpu
.bitfield
.cpuavx
;
1664 case CpuHLE
: return t
->cpu
.bitfield
.cpuhle
;
1665 case CpuAVX512F
: return t
->cpu
.bitfield
.cpuavx512f
;
1666 case CpuAVX512VL
: return t
->cpu
.bitfield
.cpuavx512vl
;
1667 case Cpu64
: return t
->cpu
.bitfield
.cpu64
;
1668 case CpuNo64
: return t
->cpu
.bitfield
.cpuno64
;
1670 gas_assert (cpu
< CpuAttrEnums
);
1672 return t
->cpu
.bitfield
.isa
== cpu
+ 1u;
1675 static i386_cpu_flags
cpu_flags_from_attr (i386_cpu_attr a
)
1677 const unsigned int bps
= sizeof (a
.array
[0]) * CHAR_BIT
;
1678 i386_cpu_flags f
= { .array
[0] = 0 };
1680 switch (ARRAY_SIZE(a
.array
))
1683 f
.array
[CpuAttrEnums
/ bps
]
1684 |= (a
.array
[0] >> CpuIsaBits
) << (CpuAttrEnums
% bps
);
1685 if (CpuAttrEnums
% bps
> CpuIsaBits
)
1686 f
.array
[CpuAttrEnums
/ bps
+ 1]
1687 = (a
.array
[0] >> CpuIsaBits
) >> (bps
- CpuAttrEnums
% bps
);
1694 f
.array
[(a
.bitfield
.isa
- 1) / bps
] |= 1u << ((a
.bitfield
.isa
- 1) % bps
);
1700 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1702 switch (ARRAY_SIZE(x
->array
))
1721 return !x
->array
[0];
1728 cpu_flags_equal (const union i386_cpu_flags
*x
,
1729 const union i386_cpu_flags
*y
)
1731 switch (ARRAY_SIZE(x
->array
))
1734 if (x
->array
[4] != y
->array
[4])
1738 if (x
->array
[3] != y
->array
[3])
1742 if (x
->array
[2] != y
->array
[2])
1746 if (x
->array
[1] != y
->array
[1])
1750 return x
->array
[0] == y
->array
[0];
1758 cpu_flags_check_cpu64 (const insn_template
*t
)
1760 return flag_code
== CODE_64BIT
1761 ? !t
->cpu
.bitfield
.cpuno64
1762 : !t
->cpu
.bitfield
.cpu64
;
1765 static INLINE i386_cpu_flags
1766 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1768 switch (ARRAY_SIZE (x
.array
))
1771 x
.array
[4] &= y
.array
[4];
1774 x
.array
[3] &= y
.array
[3];
1777 x
.array
[2] &= y
.array
[2];
1780 x
.array
[1] &= y
.array
[1];
1783 x
.array
[0] &= y
.array
[0];
1791 static INLINE i386_cpu_flags
1792 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1794 switch (ARRAY_SIZE (x
.array
))
1797 x
.array
[4] |= y
.array
[4];
1800 x
.array
[3] |= y
.array
[3];
1803 x
.array
[2] |= y
.array
[2];
1806 x
.array
[1] |= y
.array
[1];
1809 x
.array
[0] |= y
.array
[0];
1817 static INLINE i386_cpu_flags
1818 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1820 switch (ARRAY_SIZE (x
.array
))
1823 x
.array
[4] &= ~y
.array
[4];
1826 x
.array
[3] &= ~y
.array
[3];
1829 x
.array
[2] &= ~y
.array
[2];
1832 x
.array
[1] &= ~y
.array
[1];
1835 x
.array
[0] &= ~y
.array
[0];
1843 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1845 static INLINE
bool need_evex_encoding (void)
1847 return i
.vec_encoding
== vex_encoding_evex
1848 || i
.vec_encoding
== vex_encoding_evex512
1852 #define CPU_FLAGS_ARCH_MATCH 0x1
1853 #define CPU_FLAGS_64BIT_MATCH 0x2
1855 #define CPU_FLAGS_PERFECT_MATCH \
1856 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1858 /* Return CPU flags match bits. */
1861 cpu_flags_match (const insn_template
*t
)
1863 i386_cpu_flags x
= cpu_flags_from_attr (t
->cpu
);
1864 int match
= cpu_flags_check_cpu64 (t
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1866 x
.bitfield
.cpu64
= 0;
1867 x
.bitfield
.cpuno64
= 0;
1869 if (cpu_flags_all_zero (&x
))
1871 /* This instruction is available on all archs. */
1872 match
|= CPU_FLAGS_ARCH_MATCH
;
1876 /* This instruction is available only on some archs. */
1877 i386_cpu_flags cpu
= cpu_arch_flags
;
1879 /* Dual VEX/EVEX templates may need stripping of one of the flags. */
1880 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
1882 /* Dual AVX/AVX512F templates need to retain AVX512F only if we already
1883 know that EVEX encoding will be needed. */
1884 if ((x
.bitfield
.cpuavx
|| x
.bitfield
.cpuavx2
)
1885 && x
.bitfield
.cpuavx512f
)
1887 if (need_evex_encoding ())
1889 x
.bitfield
.cpuavx
= 0;
1890 x
.bitfield
.cpuavx2
= 0;
1892 /* need_evex_encoding() isn't reliable before operands were
1894 else if (i
.operands
)
1896 x
.bitfield
.cpuavx512f
= 0;
1897 x
.bitfield
.cpuavx512vl
= 0;
1898 if (x
.bitfield
.cpufma
&& !cpu
.bitfield
.cpufma
)
1899 x
.bitfield
.cpuavx
= 0;
1904 /* AVX512VL is no standalone feature - match it and then strip it. */
1905 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1907 x
.bitfield
.cpuavx512vl
= 0;
1909 /* AVX and AVX2 present at the same time express an operand size
1910 dependency - strip AVX2 for the purposes here. The operand size
1911 dependent check occurs in check_vecOperands(). */
1912 if (x
.bitfield
.cpuavx
&& x
.bitfield
.cpuavx2
)
1913 x
.bitfield
.cpuavx2
= 0;
1915 cpu
= cpu_flags_and (x
, cpu
);
1916 if (!cpu_flags_all_zero (&cpu
))
1918 if (t
->cpu
.bitfield
.cpuavx
&& t
->cpu
.bitfield
.cpuavx512f
)
1920 if ((need_evex_encoding ()
1921 ? cpu
.bitfield
.cpuavx512f
1922 : cpu
.bitfield
.cpuavx
)
1923 && (!x
.bitfield
.cpufma
|| cpu
.bitfield
.cpufma
1924 || cpu_arch_flags
.bitfield
.cpuavx512f
)
1925 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1926 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1927 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1928 match
|= CPU_FLAGS_ARCH_MATCH
;
1930 else if (x
.bitfield
.cpuavx
)
1932 /* We need to check a few extra flags with AVX. */
1933 if (cpu
.bitfield
.cpuavx
1934 && (!t
->opcode_modifier
.sse2avx
1935 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1936 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1937 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1938 && (!x
.bitfield
.cpupclmulqdq
|| cpu
.bitfield
.cpupclmulqdq
))
1939 match
|= CPU_FLAGS_ARCH_MATCH
;
1941 else if (x
.bitfield
.cpuavx2
&& cpu
.bitfield
.cpuavx2
)
1942 match
|= CPU_FLAGS_ARCH_MATCH
;
1943 else if (x
.bitfield
.cpuavx512f
)
1945 /* We need to check a few extra flags with AVX512F. */
1946 if (cpu
.bitfield
.cpuavx512f
1947 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
))
1948 match
|= CPU_FLAGS_ARCH_MATCH
;
1951 match
|= CPU_FLAGS_ARCH_MATCH
;
1957 static INLINE i386_operand_type
1958 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1960 if (x
.bitfield
.class != y
.bitfield
.class)
1961 x
.bitfield
.class = ClassNone
;
1962 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1963 x
.bitfield
.instance
= InstanceNone
;
1965 switch (ARRAY_SIZE (x
.array
))
1968 x
.array
[2] &= y
.array
[2];
1971 x
.array
[1] &= y
.array
[1];
1974 x
.array
[0] &= y
.array
[0];
1982 static INLINE i386_operand_type
1983 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1985 gas_assert (y
.bitfield
.class == ClassNone
);
1986 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1988 switch (ARRAY_SIZE (x
.array
))
1991 x
.array
[2] &= ~y
.array
[2];
1994 x
.array
[1] &= ~y
.array
[1];
1997 x
.array
[0] &= ~y
.array
[0];
2005 static INLINE i386_operand_type
2006 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2008 gas_assert (x
.bitfield
.class == ClassNone
||
2009 y
.bitfield
.class == ClassNone
||
2010 x
.bitfield
.class == y
.bitfield
.class);
2011 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2012 y
.bitfield
.instance
== InstanceNone
||
2013 x
.bitfield
.instance
== y
.bitfield
.instance
);
2015 switch (ARRAY_SIZE (x
.array
))
2018 x
.array
[2] |= y
.array
[2];
2021 x
.array
[1] |= y
.array
[1];
2024 x
.array
[0] |= y
.array
[0];
2032 static INLINE i386_operand_type
2033 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2035 gas_assert (y
.bitfield
.class == ClassNone
);
2036 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2038 switch (ARRAY_SIZE (x
.array
))
2041 x
.array
[2] ^= y
.array
[2];
2044 x
.array
[1] ^= y
.array
[1];
2047 x
.array
[0] ^= y
.array
[0];
2055 static const i386_operand_type anydisp
= {
2056 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
2068 operand_type_check (i386_operand_type t
, enum operand_type c
)
2073 return t
.bitfield
.class == Reg
;
2076 return (t
.bitfield
.imm8
2080 || t
.bitfield
.imm32s
2081 || t
.bitfield
.imm64
);
2084 return (t
.bitfield
.disp8
2085 || t
.bitfield
.disp16
2086 || t
.bitfield
.disp32
2087 || t
.bitfield
.disp64
);
2090 return (t
.bitfield
.disp8
2091 || t
.bitfield
.disp16
2092 || t
.bitfield
.disp32
2093 || t
.bitfield
.disp64
2094 || t
.bitfield
.baseindex
);
2103 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2104 between operand GIVEN and opeand WANTED for instruction template T. */
2107 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2110 return !((i
.types
[given
].bitfield
.byte
2111 && !t
->operand_types
[wanted
].bitfield
.byte
)
2112 || (i
.types
[given
].bitfield
.word
2113 && !t
->operand_types
[wanted
].bitfield
.word
)
2114 || (i
.types
[given
].bitfield
.dword
2115 && !t
->operand_types
[wanted
].bitfield
.dword
)
2116 || (i
.types
[given
].bitfield
.qword
2117 && (!t
->operand_types
[wanted
].bitfield
.qword
2118 /* Don't allow 64-bit (memory) operands outside of 64-bit
2119 mode, when they're used where a 64-bit GPR could also
2120 be used. Checking is needed for Intel Syntax only. */
2122 && flag_code
!= CODE_64BIT
2123 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2124 || t
->operand_types
[wanted
].bitfield
.class == Accum
2125 || t
->opcode_modifier
.isstring
))))
2126 || (i
.types
[given
].bitfield
.tbyte
2127 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2130 /* Return 1 if there is no conflict in SIMD register between operand
2131 GIVEN and opeand WANTED for instruction template T. */
2134 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2137 return !((i
.types
[given
].bitfield
.xmmword
2138 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2139 || (i
.types
[given
].bitfield
.ymmword
2140 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2141 || (i
.types
[given
].bitfield
.zmmword
2142 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2143 || (i
.types
[given
].bitfield
.tmmword
2144 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2147 /* Return 1 if there is no conflict in any size between operand GIVEN
2148 and opeand WANTED for instruction template T. */
2151 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2154 return (match_operand_size (t
, wanted
, given
)
2155 && !((i
.types
[given
].bitfield
.unspecified
2156 && !i
.broadcast
.type
2157 && !i
.broadcast
.bytes
2158 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2159 || (i
.types
[given
].bitfield
.fword
2160 && !t
->operand_types
[wanted
].bitfield
.fword
)
2161 /* For scalar opcode templates to allow register and memory
2162 operands at the same time, some special casing is needed
2163 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2164 down-conversion vpmov*. */
2165 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2166 && t
->operand_types
[wanted
].bitfield
.byte
2167 + t
->operand_types
[wanted
].bitfield
.word
2168 + t
->operand_types
[wanted
].bitfield
.dword
2169 + t
->operand_types
[wanted
].bitfield
.qword
2170 > !!t
->opcode_modifier
.broadcast
)
2171 ? (i
.types
[given
].bitfield
.xmmword
2172 || i
.types
[given
].bitfield
.ymmword
2173 || i
.types
[given
].bitfield
.zmmword
)
2174 : !match_simd_size(t
, wanted
, given
))));
2177 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2178 operands for instruction template T, and it has MATCH_REVERSE set if there
2179 is no size conflict on any operands for the template with operands reversed
2180 (and the template allows for reversing in the first place). */
2182 #define MATCH_STRAIGHT 1
2183 #define MATCH_REVERSE 2
2185 static INLINE
unsigned int
2186 operand_size_match (const insn_template
*t
)
2188 unsigned int j
, match
= MATCH_STRAIGHT
;
2190 /* Don't check non-absolute jump instructions. */
2191 if (t
->opcode_modifier
.jump
2192 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2195 /* Check memory and accumulator operand size. */
2196 for (j
= 0; j
< i
.operands
; j
++)
2198 if (i
.types
[j
].bitfield
.class != Reg
2199 && i
.types
[j
].bitfield
.class != RegSIMD
2200 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2203 if (t
->operand_types
[j
].bitfield
.class == Reg
2204 && !match_operand_size (t
, j
, j
))
2210 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2211 && !match_simd_size (t
, j
, j
))
2217 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2218 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2224 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2231 if (!t
->opcode_modifier
.d
)
2234 /* Check reverse. */
2235 gas_assert (i
.operands
>= 2);
2237 for (j
= 0; j
< i
.operands
; j
++)
2239 unsigned int given
= i
.operands
- j
- 1;
2241 /* For FMA4 and XOP insns VEX.W controls just the first two
2242 register operands. */
2243 if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
2244 given
= j
< 2 ? 1 - j
: j
;
2246 if (t
->operand_types
[j
].bitfield
.class == Reg
2247 && !match_operand_size (t
, j
, given
))
2250 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2251 && !match_simd_size (t
, j
, given
))
2254 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2255 && (!match_operand_size (t
, j
, given
)
2256 || !match_simd_size (t
, j
, given
)))
2259 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2263 return match
| MATCH_REVERSE
;
2267 operand_type_match (i386_operand_type overlap
,
2268 i386_operand_type given
)
2270 i386_operand_type temp
= overlap
;
2272 temp
.bitfield
.unspecified
= 0;
2273 temp
.bitfield
.byte
= 0;
2274 temp
.bitfield
.word
= 0;
2275 temp
.bitfield
.dword
= 0;
2276 temp
.bitfield
.fword
= 0;
2277 temp
.bitfield
.qword
= 0;
2278 temp
.bitfield
.tbyte
= 0;
2279 temp
.bitfield
.xmmword
= 0;
2280 temp
.bitfield
.ymmword
= 0;
2281 temp
.bitfield
.zmmword
= 0;
2282 temp
.bitfield
.tmmword
= 0;
2283 if (operand_type_all_zero (&temp
))
2286 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2290 i
.error
= operand_type_mismatch
;
2294 /* If given types g0 and g1 are registers they must be of the same type
2295 unless the expected operand type register overlap is null.
2296 Intel syntax sized memory operands are also checked here. */
2299 operand_type_register_match (i386_operand_type g0
,
2300 i386_operand_type t0
,
2301 i386_operand_type g1
,
2302 i386_operand_type t1
)
2304 if (g0
.bitfield
.class != Reg
2305 && g0
.bitfield
.class != RegSIMD
2306 && (g0
.bitfield
.unspecified
2307 || !operand_type_check (g0
, anymem
)))
2310 if (g1
.bitfield
.class != Reg
2311 && g1
.bitfield
.class != RegSIMD
2312 && (g1
.bitfield
.unspecified
2313 || !operand_type_check (g1
, anymem
)))
2316 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2317 && g0
.bitfield
.word
== g1
.bitfield
.word
2318 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2319 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2320 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2321 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2322 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2325 /* If expectations overlap in no more than a single size, all is fine. */
2326 g0
= operand_type_and (t0
, t1
);
2327 if (g0
.bitfield
.byte
2331 + g0
.bitfield
.xmmword
2332 + g0
.bitfield
.ymmword
2333 + g0
.bitfield
.zmmword
<= 1)
2336 i
.error
= register_type_mismatch
;
2341 static INLINE
unsigned int
2342 register_number (const reg_entry
*r
)
2344 unsigned int nr
= r
->reg_num
;
2346 if (r
->reg_flags
& RegRex
)
2349 if (r
->reg_flags
& RegVRex
)
2355 static INLINE
unsigned int
2356 mode_from_disp_size (i386_operand_type t
)
2358 if (t
.bitfield
.disp8
)
2360 else if (t
.bitfield
.disp16
2361 || t
.bitfield
.disp32
)
2368 fits_in_signed_byte (addressT num
)
2370 return num
+ 0x80 <= 0xff;
2374 fits_in_unsigned_byte (addressT num
)
2380 fits_in_unsigned_word (addressT num
)
2382 return num
<= 0xffff;
2386 fits_in_signed_word (addressT num
)
2388 return num
+ 0x8000 <= 0xffff;
2392 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2397 return num
+ 0x80000000 <= 0xffffffff;
2399 } /* fits_in_signed_long() */
2402 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2407 return num
<= 0xffffffff;
2409 } /* fits_in_unsigned_long() */
2411 static INLINE valueT
extend_to_32bit_address (addressT num
)
2414 if (fits_in_unsigned_long(num
))
2415 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2417 if (!fits_in_signed_long (num
))
2418 return num
& 0xffffffff;
2425 fits_in_disp8 (offsetT num
)
2427 int shift
= i
.memshift
;
2433 mask
= (1 << shift
) - 1;
2435 /* Return 0 if NUM isn't properly aligned. */
2439 /* Check if NUM will fit in 8bit after shift. */
2440 return fits_in_signed_byte (num
>> shift
);
2444 fits_in_imm4 (offsetT num
)
2446 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2447 return (num
& (i
.vec_encoding
!= vex_encoding_evex
? 0xf : 7)) == num
;
2450 static i386_operand_type
2451 smallest_imm_type (offsetT num
)
2453 i386_operand_type t
;
2455 operand_type_set (&t
, 0);
2456 t
.bitfield
.imm64
= 1;
2458 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2460 /* This code is disabled on the 486 because all the Imm1 forms
2461 in the opcode table are slower on the i486. They're the
2462 versions with the implicitly specified single-position
2463 displacement, which has another syntax if you really want to
2465 t
.bitfield
.imm1
= 1;
2466 t
.bitfield
.imm8
= 1;
2467 t
.bitfield
.imm8s
= 1;
2468 t
.bitfield
.imm16
= 1;
2469 t
.bitfield
.imm32
= 1;
2470 t
.bitfield
.imm32s
= 1;
2472 else if (fits_in_signed_byte (num
))
2474 if (fits_in_unsigned_byte (num
))
2475 t
.bitfield
.imm8
= 1;
2476 t
.bitfield
.imm8s
= 1;
2477 t
.bitfield
.imm16
= 1;
2478 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2479 t
.bitfield
.imm32
= 1;
2480 t
.bitfield
.imm32s
= 1;
2482 else if (fits_in_unsigned_byte (num
))
2484 t
.bitfield
.imm8
= 1;
2485 t
.bitfield
.imm16
= 1;
2486 t
.bitfield
.imm32
= 1;
2487 t
.bitfield
.imm32s
= 1;
2489 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2491 t
.bitfield
.imm16
= 1;
2492 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2493 t
.bitfield
.imm32
= 1;
2494 t
.bitfield
.imm32s
= 1;
2496 else if (fits_in_signed_long (num
))
2498 if (flag_code
!= CODE_64BIT
|| fits_in_unsigned_long (num
))
2499 t
.bitfield
.imm32
= 1;
2500 t
.bitfield
.imm32s
= 1;
2502 else if (fits_in_unsigned_long (num
))
2503 t
.bitfield
.imm32
= 1;
2509 offset_in_range (offsetT val
, int size
)
2515 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2516 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2518 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2520 case sizeof (val
): return val
;
2524 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2525 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2526 (uint64_t) val
, (uint64_t) (val
& mask
));
2531 static INLINE
const char *insn_name (const insn_template
*t
)
2533 return &i386_mnemonics
[t
->mnem_off
];
2546 a. PREFIX_EXIST if attempting to add a prefix where one from the
2547 same class already exists.
2548 b. PREFIX_LOCK if lock prefix is added.
2549 c. PREFIX_REP if rep/repne prefix is added.
2550 d. PREFIX_DS if ds prefix is added.
2551 e. PREFIX_OTHER if other prefix is added.
2554 static enum PREFIX_GROUP
2555 add_prefix (unsigned int prefix
)
2557 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2560 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2561 && flag_code
== CODE_64BIT
)
2563 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2564 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2565 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2566 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2577 case DS_PREFIX_OPCODE
:
2580 case CS_PREFIX_OPCODE
:
2581 case ES_PREFIX_OPCODE
:
2582 case FS_PREFIX_OPCODE
:
2583 case GS_PREFIX_OPCODE
:
2584 case SS_PREFIX_OPCODE
:
2588 case REPNE_PREFIX_OPCODE
:
2589 case REPE_PREFIX_OPCODE
:
2594 case LOCK_PREFIX_OPCODE
:
2603 case ADDR_PREFIX_OPCODE
:
2607 case DATA_PREFIX_OPCODE
:
2611 if (i
.prefix
[q
] != 0)
2619 i
.prefix
[q
] |= prefix
;
2622 as_bad (_("same type of prefix used twice"));
2628 update_code_flag (int value
, int check
)
2630 PRINTF_LIKE ((*as_error
)) = check
? as_fatal
: as_bad
;
2632 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpu64
)
2634 as_error (_("64bit mode not supported on `%s'."),
2635 cpu_arch_name
? cpu_arch_name
: default_arch
);
2639 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2641 as_error (_("32bit mode not supported on `%s'."),
2642 cpu_arch_name
? cpu_arch_name
: default_arch
);
2646 flag_code
= (enum flag_code
) value
;
2648 stackop_size
= '\0';
2652 set_code_flag (int value
)
2654 update_code_flag (value
, 0);
2658 set_16bit_gcc_code_flag (int new_code_flag
)
2660 flag_code
= (enum flag_code
) new_code_flag
;
2661 if (flag_code
!= CODE_16BIT
)
2663 stackop_size
= LONG_MNEM_SUFFIX
;
2667 set_intel_syntax (int syntax_flag
)
2669 /* Find out if register prefixing is specified. */
2670 int ask_naked_reg
= 0;
2673 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2676 int e
= get_symbol_name (&string
);
2678 if (strcmp (string
, "prefix") == 0)
2680 else if (strcmp (string
, "noprefix") == 0)
2683 as_bad (_("bad argument to syntax directive."));
2684 (void) restore_line_pointer (e
);
2686 demand_empty_rest_of_line ();
2688 intel_syntax
= syntax_flag
;
2690 if (ask_naked_reg
== 0)
2691 allow_naked_reg
= (intel_syntax
2692 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2694 allow_naked_reg
= (ask_naked_reg
< 0);
2696 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2698 register_prefix
= allow_naked_reg
? "" : "%";
2702 set_intel_mnemonic (int mnemonic_flag
)
2704 intel_mnemonic
= mnemonic_flag
;
2708 set_allow_index_reg (int flag
)
2710 allow_index_reg
= flag
;
2714 set_check (int what
)
2716 enum check_kind
*kind
;
2721 kind
= &operand_check
;
2732 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2735 int e
= get_symbol_name (&string
);
2737 if (strcmp (string
, "none") == 0)
2739 else if (strcmp (string
, "warning") == 0)
2740 *kind
= check_warning
;
2741 else if (strcmp (string
, "error") == 0)
2742 *kind
= check_error
;
2744 as_bad (_("bad argument to %s_check directive."), str
);
2745 (void) restore_line_pointer (e
);
2748 as_bad (_("missing argument for %s_check directive"), str
);
2750 demand_empty_rest_of_line ();
2754 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2755 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2757 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2758 static const char *arch
;
2760 /* Intel MCU is only supported on ELF. */
2766 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2767 use default_arch. */
2768 arch
= cpu_arch_name
;
2770 arch
= default_arch
;
2773 /* If we are targeting Intel MCU, we must enable it. */
2774 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2775 == new_flag
.bitfield
.cpuiamcu
)
2778 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2783 extend_cpu_sub_arch_name (const char *pfx
, const char *name
)
2785 if (cpu_sub_arch_name
)
2786 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2787 pfx
, name
, (const char *) NULL
);
2789 cpu_sub_arch_name
= concat (pfx
, name
, (const char *) NULL
);
2792 static void isa_enable (unsigned int idx
)
2794 i386_cpu_flags flags
= cpu_flags_or (cpu_arch_flags
, cpu_arch
[idx
].enable
);
2796 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2798 extend_cpu_sub_arch_name (".", cpu_arch
[idx
].name
);
2799 cpu_arch_flags
= flags
;
2802 cpu_arch_isa_flags
= cpu_flags_or (cpu_arch_isa_flags
, cpu_arch
[idx
].enable
);
2805 static void isa_disable (unsigned int idx
)
2807 i386_cpu_flags flags
2808 = cpu_flags_and_not (cpu_arch_flags
, cpu_arch
[idx
].disable
);
2810 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2812 extend_cpu_sub_arch_name (".no", cpu_arch
[idx
].name
);
2813 cpu_arch_flags
= flags
;
2817 = cpu_flags_and_not (cpu_arch_isa_flags
, cpu_arch
[idx
].disable
);
2821 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2823 typedef struct arch_stack_entry
2825 const struct arch_stack_entry
*prev
;
2828 i386_cpu_flags flags
;
2829 i386_cpu_flags isa_flags
;
2830 enum processor_type isa
;
2831 enum flag_code flag_code
;
2832 unsigned int vector_size
;
2834 bool no_cond_jump_promotion
;
2836 static const arch_stack_entry
*arch_stack_top
;
2844 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
2846 as_bad (_("missing cpu architecture"));
2847 input_line_pointer
++;
2851 e
= get_symbol_name (&s
);
2854 if (strcmp (string
, "push") == 0)
2856 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2858 top
->name
= cpu_arch_name
;
2859 if (cpu_sub_arch_name
)
2860 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2862 top
->sub_name
= NULL
;
2863 top
->flags
= cpu_arch_flags
;
2864 top
->isa
= cpu_arch_isa
;
2865 top
->isa_flags
= cpu_arch_isa_flags
;
2866 top
->flag_code
= flag_code
;
2867 top
->vector_size
= vector_size
;
2868 top
->stackop_size
= stackop_size
;
2869 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2871 top
->prev
= arch_stack_top
;
2872 arch_stack_top
= top
;
2874 (void) restore_line_pointer (e
);
2875 demand_empty_rest_of_line ();
2879 if (strcmp (string
, "pop") == 0)
2881 const arch_stack_entry
*top
= arch_stack_top
;
2884 as_bad (_(".arch stack is empty"));
2885 else if (top
->flag_code
!= flag_code
2886 || top
->stackop_size
!= stackop_size
)
2888 static const unsigned int bits
[] = {
2894 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2895 bits
[top
->flag_code
],
2896 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2900 arch_stack_top
= top
->prev
;
2902 cpu_arch_name
= top
->name
;
2903 free (cpu_sub_arch_name
);
2904 cpu_sub_arch_name
= top
->sub_name
;
2905 cpu_arch_flags
= top
->flags
;
2906 cpu_arch_isa
= top
->isa
;
2907 cpu_arch_isa_flags
= top
->isa_flags
;
2908 vector_size
= top
->vector_size
;
2909 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2914 (void) restore_line_pointer (e
);
2915 demand_empty_rest_of_line ();
2919 if (strcmp (string
, "default") == 0)
2921 if (strcmp (default_arch
, "iamcu") == 0)
2922 string
= default_arch
;
2925 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2927 cpu_arch_name
= NULL
;
2928 free (cpu_sub_arch_name
);
2929 cpu_sub_arch_name
= NULL
;
2930 cpu_arch_flags
= cpu_unknown_flags
;
2931 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2932 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2933 if (!cpu_arch_tune_set
)
2934 cpu_arch_tune
= PROCESSOR_UNKNOWN
;
2936 vector_size
= VSZ_DEFAULT
;
2938 j
= ARRAY_SIZE (cpu_arch
) + 1;
2942 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2944 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2945 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2949 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2951 if (flag_code
== CODE_64BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpu64
)
2953 as_bad (_("64bit mode not supported on `%s'."),
2955 (void) restore_line_pointer (e
);
2956 ignore_rest_of_line ();
2960 if (flag_code
== CODE_32BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpui386
)
2962 as_bad (_("32bit mode not supported on `%s'."),
2964 (void) restore_line_pointer (e
);
2965 ignore_rest_of_line ();
2969 cpu_arch_name
= cpu_arch
[j
].name
;
2970 free (cpu_sub_arch_name
);
2971 cpu_sub_arch_name
= NULL
;
2972 cpu_arch_flags
= cpu_arch
[j
].enable
;
2973 cpu_arch_isa
= cpu_arch
[j
].type
;
2974 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2975 if (!cpu_arch_tune_set
)
2976 cpu_arch_tune
= cpu_arch_isa
;
2978 vector_size
= VSZ_DEFAULT
;
2980 pre_386_16bit_warned
= false;
2984 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
2989 (void) restore_line_pointer (e
);
2991 switch (cpu_arch
[j
].vsz
)
2997 #ifdef SVR4_COMMENT_CHARS
2998 if (*input_line_pointer
== ':' || *input_line_pointer
== '/')
3000 if (*input_line_pointer
== '/')
3003 ++input_line_pointer
;
3004 switch (get_absolute_expression ())
3006 case 512: vector_size
= VSZ512
; break;
3007 case 256: vector_size
= VSZ256
; break;
3008 case 128: vector_size
= VSZ128
; break;
3010 as_bad (_("Unrecognized vector size specifier"));
3011 ignore_rest_of_line ();
3018 vector_size
= VSZ_DEFAULT
;
3022 demand_empty_rest_of_line ();
3027 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
3029 /* Disable an ISA extension. */
3030 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
3031 if (cpu_arch
[j
].type
== PROCESSOR_NONE
3032 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
3036 if (cpu_arch
[j
].vsz
== vsz_set
)
3037 vector_size
= VSZ_DEFAULT
;
3039 (void) restore_line_pointer (e
);
3040 demand_empty_rest_of_line ();
3045 if (j
== ARRAY_SIZE (cpu_arch
))
3046 as_bad (_("no such architecture: `%s'"), string
);
3048 *input_line_pointer
= e
;
3050 no_cond_jump_promotion
= 0;
3051 if (*input_line_pointer
== ','
3052 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
3054 ++input_line_pointer
;
3055 e
= get_symbol_name (&s
);
3058 if (strcmp (string
, "nojumps") == 0)
3059 no_cond_jump_promotion
= 1;
3060 else if (strcmp (string
, "jumps") == 0)
3063 as_bad (_("no such architecture modifier: `%s'"), string
);
3065 (void) restore_line_pointer (e
);
3068 demand_empty_rest_of_line ();
3071 enum bfd_architecture
3074 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3076 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3077 || flag_code
== CODE_64BIT
)
3078 as_fatal (_("Intel MCU is 32bit ELF only"));
3079 return bfd_arch_iamcu
;
3082 return bfd_arch_i386
;
3088 if (startswith (default_arch
, "x86_64"))
3090 if (default_arch
[6] == '\0')
3091 return bfd_mach_x86_64
;
3093 return bfd_mach_x64_32
;
3095 else if (!strcmp (default_arch
, "i386")
3096 || !strcmp (default_arch
, "iamcu"))
3098 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3100 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3101 as_fatal (_("Intel MCU is 32bit ELF only"));
3102 return bfd_mach_i386_iamcu
;
3105 return bfd_mach_i386_i386
;
3108 as_fatal (_("unknown architecture"));
3111 #include "opcodes/i386-tbl.h"
3116 /* Support pseudo prefixes like {disp32}. */
3117 lex_type
['{'] = LEX_BEGIN_NAME
;
3119 /* Initialize op_hash hash table. */
3120 op_hash
= str_htab_create ();
3123 const insn_template
*const *sets
= i386_op_sets
;
3124 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
3126 /* Type checks to compensate for the conversion through void * which
3127 occurs during hash table insertion / lookup. */
3128 (void) sizeof (sets
== ¤t_templates
->start
);
3129 (void) sizeof (end
== ¤t_templates
->end
);
3130 for (; sets
< end
; ++sets
)
3131 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3132 as_fatal (_("duplicate %s"), insn_name (*sets
));
3135 /* Initialize reg_hash hash table. */
3136 reg_hash
= str_htab_create ();
3138 const reg_entry
*regtab
;
3139 unsigned int regtab_size
= i386_regtab_size
;
3141 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3143 switch (regtab
->reg_type
.bitfield
.class)
3146 if (regtab
->reg_type
.bitfield
.dword
)
3148 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3151 else if (regtab
->reg_type
.bitfield
.tbyte
)
3153 /* There's no point inserting st(<N>) in the hash table, as
3154 parentheses aren't included in register_chars[] anyway. */
3155 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3162 switch (regtab
->reg_num
)
3164 case 0: reg_es
= regtab
; break;
3165 case 2: reg_ss
= regtab
; break;
3166 case 3: reg_ds
= regtab
; break;
3171 if (!regtab
->reg_num
)
3176 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3177 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3181 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3186 for (c
= 0; c
< 256; c
++)
3188 if (ISDIGIT (c
) || ISLOWER (c
))
3190 mnemonic_chars
[c
] = c
;
3191 register_chars
[c
] = c
;
3192 operand_chars
[c
] = c
;
3194 else if (ISUPPER (c
))
3196 mnemonic_chars
[c
] = TOLOWER (c
);
3197 register_chars
[c
] = mnemonic_chars
[c
];
3198 operand_chars
[c
] = c
;
3200 #ifdef SVR4_COMMENT_CHARS
3201 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3202 operand_chars
[c
] = c
;
3206 operand_chars
[c
] = c
;
3209 mnemonic_chars
['_'] = '_';
3210 mnemonic_chars
['-'] = '-';
3211 mnemonic_chars
['.'] = '.';
3213 for (p
= extra_symbol_chars
; *p
!= '\0'; p
++)
3214 operand_chars
[(unsigned char) *p
] = *p
;
3215 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3216 operand_chars
[(unsigned char) *p
] = *p
;
3219 if (flag_code
== CODE_64BIT
)
3221 #if defined (OBJ_COFF) && defined (TE_PE)
3222 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3225 x86_dwarf2_return_column
= 16;
3227 x86_cie_data_alignment
= -8;
3228 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3229 x86_sframe_cfa_sp_reg
= 7;
3230 x86_sframe_cfa_fp_reg
= 6;
3235 x86_dwarf2_return_column
= 8;
3236 x86_cie_data_alignment
= -4;
3239 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3240 can be turned into BRANCH_PREFIX frag. */
3241 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3246 i386_print_statistics (FILE *file
)
3248 htab_print_statistics (file
, "i386 opcode", op_hash
);
3249 htab_print_statistics (file
, "i386 register", reg_hash
);
3255 htab_delete (op_hash
);
3256 htab_delete (reg_hash
);
3261 /* Debugging routines for md_assemble. */
3262 static void pte (insn_template
*);
3263 static void pt (i386_operand_type
);
3264 static void pe (expressionS
*);
3265 static void ps (symbolS
*);
3268 pi (const char *line
, i386_insn
*x
)
3272 fprintf (stdout
, "%s: template ", line
);
3274 fprintf (stdout
, " address: base %s index %s scale %x\n",
3275 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3276 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3277 x
->log2_scale_factor
);
3278 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3279 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3280 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3281 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3282 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3283 (x
->rex
& REX_W
) != 0,
3284 (x
->rex
& REX_R
) != 0,
3285 (x
->rex
& REX_X
) != 0,
3286 (x
->rex
& REX_B
) != 0);
3287 for (j
= 0; j
< x
->operands
; j
++)
3289 fprintf (stdout
, " #%d: ", j
+ 1);
3291 fprintf (stdout
, "\n");
3292 if (x
->types
[j
].bitfield
.class == Reg
3293 || x
->types
[j
].bitfield
.class == RegMMX
3294 || x
->types
[j
].bitfield
.class == RegSIMD
3295 || x
->types
[j
].bitfield
.class == RegMask
3296 || x
->types
[j
].bitfield
.class == SReg
3297 || x
->types
[j
].bitfield
.class == RegCR
3298 || x
->types
[j
].bitfield
.class == RegDR
3299 || x
->types
[j
].bitfield
.class == RegTR
3300 || x
->types
[j
].bitfield
.class == RegBND
)
3301 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3302 if (operand_type_check (x
->types
[j
], imm
))
3304 if (operand_type_check (x
->types
[j
], disp
))
3305 pe (x
->op
[j
].disps
);
3310 pte (insn_template
*t
)
3312 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3313 static const char *const opc_spc
[] = {
3314 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3315 "XOP08", "XOP09", "XOP0A",
3319 fprintf (stdout
, " %d operands ", t
->operands
);
3320 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3321 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3322 if (opc_spc
[t
->opcode_space
])
3323 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3324 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3325 if (t
->extension_opcode
!= None
)
3326 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3327 if (t
->opcode_modifier
.d
)
3328 fprintf (stdout
, "D");
3329 if (t
->opcode_modifier
.w
)
3330 fprintf (stdout
, "W");
3331 fprintf (stdout
, "\n");
3332 for (j
= 0; j
< t
->operands
; j
++)
3334 fprintf (stdout
, " #%d type ", j
+ 1);
3335 pt (t
->operand_types
[j
]);
3336 fprintf (stdout
, "\n");
3343 fprintf (stdout
, " operation %d\n", e
->X_op
);
3344 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3345 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3346 if (e
->X_add_symbol
)
3348 fprintf (stdout
, " add_symbol ");
3349 ps (e
->X_add_symbol
);
3350 fprintf (stdout
, "\n");
3354 fprintf (stdout
, " op_symbol ");
3355 ps (e
->X_op_symbol
);
3356 fprintf (stdout
, "\n");
3363 fprintf (stdout
, "%s type %s%s",
3365 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3366 segment_name (S_GET_SEGMENT (s
)));
3369 static struct type_name
3371 i386_operand_type mask
;
3374 const type_names
[] =
3376 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3377 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3378 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3379 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3380 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3381 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3382 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3383 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3384 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3385 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3386 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3387 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3388 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3389 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3390 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3391 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3392 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3393 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3394 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3395 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3396 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3397 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3398 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3399 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3400 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3401 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3402 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3403 { { .bitfield
= { .class = SReg
} }, "SReg" },
3404 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3405 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3406 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3407 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3408 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3409 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3413 pt (i386_operand_type t
)
3416 i386_operand_type a
;
3418 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3420 a
= operand_type_and (t
, type_names
[j
].mask
);
3421 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3422 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3427 #endif /* DEBUG386 */
3429 static bfd_reloc_code_real_type
3430 reloc (unsigned int size
,
3433 bfd_reloc_code_real_type other
)
3435 if (other
!= NO_RELOC
)
3437 reloc_howto_type
*rel
;
3442 case BFD_RELOC_X86_64_GOT32
:
3443 return BFD_RELOC_X86_64_GOT64
;
3445 case BFD_RELOC_X86_64_GOTPLT64
:
3446 return BFD_RELOC_X86_64_GOTPLT64
;
3448 case BFD_RELOC_X86_64_PLTOFF64
:
3449 return BFD_RELOC_X86_64_PLTOFF64
;
3451 case BFD_RELOC_X86_64_GOTPC32
:
3452 other
= BFD_RELOC_X86_64_GOTPC64
;
3454 case BFD_RELOC_X86_64_GOTPCREL
:
3455 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3457 case BFD_RELOC_X86_64_TPOFF32
:
3458 other
= BFD_RELOC_X86_64_TPOFF64
;
3460 case BFD_RELOC_X86_64_DTPOFF32
:
3461 other
= BFD_RELOC_X86_64_DTPOFF64
;
3467 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3468 if (other
== BFD_RELOC_SIZE32
)
3471 other
= BFD_RELOC_SIZE64
;
3474 as_bad (_("there are no pc-relative size relocations"));
3480 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3481 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3484 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3486 as_bad (_("unknown relocation (%u)"), other
);
3487 else if (size
!= bfd_get_reloc_size (rel
))
3488 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3489 bfd_get_reloc_size (rel
),
3491 else if (pcrel
&& !rel
->pc_relative
)
3492 as_bad (_("non-pc-relative relocation for pc-relative field"));
3493 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3495 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3497 as_bad (_("relocated field and relocation type differ in signedness"));
3506 as_bad (_("there are no unsigned pc-relative relocations"));
3509 case 1: return BFD_RELOC_8_PCREL
;
3510 case 2: return BFD_RELOC_16_PCREL
;
3511 case 4: return BFD_RELOC_32_PCREL
;
3512 case 8: return BFD_RELOC_64_PCREL
;
3514 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3521 case 4: return BFD_RELOC_X86_64_32S
;
3526 case 1: return BFD_RELOC_8
;
3527 case 2: return BFD_RELOC_16
;
3528 case 4: return BFD_RELOC_32
;
3529 case 8: return BFD_RELOC_64
;
3531 as_bad (_("cannot do %s %u byte relocation"),
3532 sign
> 0 ? "signed" : "unsigned", size
);
3538 /* Here we decide which fixups can be adjusted to make them relative to
3539 the beginning of the section instead of the symbol. Basically we need
3540 to make sure that the dynamic relocations are done correctly, so in
3541 some cases we force the original symbol to be used. */
3544 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3550 /* Don't adjust pc-relative references to merge sections in 64-bit
3552 if (use_rela_relocations
3553 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3557 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3558 and changed later by validate_fix. */
3559 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3560 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3563 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3564 for size relocations. */
3565 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3566 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3567 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3568 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3569 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3570 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3571 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3572 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3573 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3574 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3575 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3576 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3577 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3578 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3579 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3580 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3581 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3582 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3583 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3584 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3585 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3586 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3587 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3588 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3589 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3590 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3591 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3592 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3593 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3594 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3595 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3602 want_disp32 (const insn_template
*t
)
3604 return flag_code
!= CODE_64BIT
3605 || i
.prefix
[ADDR_PREFIX
]
3606 || (t
->mnem_off
== MN_lea
3607 && (!i
.types
[1].bitfield
.qword
3608 || t
->opcode_modifier
.size
== SIZE32
));
3612 intel_float_operand (const char *mnemonic
)
3614 /* Note that the value returned is meaningful only for opcodes with (memory)
3615 operands, hence the code here is free to improperly handle opcodes that
3616 have no operands (for better performance and smaller code). */
3618 if (mnemonic
[0] != 'f')
3619 return 0; /* non-math */
3621 switch (mnemonic
[1])
3623 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3624 the fs segment override prefix not currently handled because no
3625 call path can make opcodes without operands get here */
3627 return 2 /* integer op */;
3629 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3630 return 3; /* fldcw/fldenv */
3633 if (mnemonic
[2] != 'o' /* fnop */)
3634 return 3; /* non-waiting control op */
3637 if (mnemonic
[2] == 's')
3638 return 3; /* frstor/frstpm */
3641 if (mnemonic
[2] == 'a')
3642 return 3; /* fsave */
3643 if (mnemonic
[2] == 't')
3645 switch (mnemonic
[3])
3647 case 'c': /* fstcw */
3648 case 'd': /* fstdw */
3649 case 'e': /* fstenv */
3650 case 's': /* fsts[gw] */
3656 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3657 return 0; /* fxsave/fxrstor are not really math ops */
3665 install_template (const insn_template
*t
)
3671 /* Dual VEX/EVEX templates need stripping one of the possible variants. */
3672 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
3674 if ((is_cpu (t
, CpuAVX
) || is_cpu (t
, CpuAVX2
))
3675 && is_cpu (t
, CpuAVX512F
))
3677 if (need_evex_encoding ())
3679 i
.tm
.opcode_modifier
.vex
= 0;
3680 i
.tm
.cpu
.bitfield
.cpuavx
= 0;
3681 if (is_cpu (&i
.tm
, CpuAVX2
))
3682 i
.tm
.cpu
.bitfield
.isa
= 0;
3686 i
.tm
.opcode_modifier
.evex
= 0;
3687 i
.tm
.cpu
.bitfield
.cpuavx512f
= 0;
3692 /* Note that for pseudo prefixes this produces a length of 1. But for them
3693 the length isn't interesting at all. */
3694 for (l
= 1; l
< 4; ++l
)
3695 if (!(t
->base_opcode
>> (8 * l
)))
3698 i
.opcode_length
= l
;
3701 /* Build the VEX prefix. */
3704 build_vex_prefix (const insn_template
*t
)
3706 unsigned int register_specifier
;
3707 unsigned int vector_length
;
3710 /* Check register specifier. */
3711 if (i
.vex
.register_specifier
)
3713 register_specifier
=
3714 ~register_number (i
.vex
.register_specifier
) & 0xf;
3715 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3718 register_specifier
= 0xf;
3720 /* Use 2-byte VEX prefix by swapping destination and source operand
3721 if there are more than 1 register operand. */
3722 if (i
.reg_operands
> 1
3723 && i
.vec_encoding
!= vex_encoding_vex3
3724 && i
.dir_encoding
== dir_encoding_default
3725 && i
.operands
== i
.reg_operands
3726 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3727 && i
.tm
.opcode_space
== SPACE_0F
3728 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3733 swap_2_operands (0, i
.operands
- 1);
3735 gas_assert (i
.rm
.mode
== 3);
3739 i
.rm
.regmem
= i
.rm
.reg
;
3742 if (i
.tm
.opcode_modifier
.d
)
3743 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3744 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3745 else /* Use the next insn. */
3746 install_template (&t
[1]);
3749 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3750 are no memory operands and at least 3 register ones. */
3751 if (i
.reg_operands
>= 3
3752 && i
.vec_encoding
!= vex_encoding_vex3
3753 && i
.reg_operands
== i
.operands
- i
.imm_operands
3754 && i
.tm
.opcode_modifier
.vex
3755 && i
.tm
.opcode_modifier
.commutative
3756 && (i
.tm
.opcode_modifier
.sse2avx
3757 || (optimize
> 1 && !i
.no_optimize
))
3759 && i
.vex
.register_specifier
3760 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3762 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3764 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3765 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3766 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3767 &i
.types
[i
.operands
- 3]));
3768 gas_assert (i
.rm
.mode
== 3);
3770 swap_2_operands (xchg
, xchg
+ 1);
3773 xchg
= i
.rm
.regmem
| 8;
3774 i
.rm
.regmem
= ~register_specifier
& 0xf;
3775 gas_assert (!(i
.rm
.regmem
& 8));
3776 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3777 register_specifier
= ~xchg
& 0xf;
3780 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3781 vector_length
= avxscalar
;
3782 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3784 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3790 /* Determine vector length from the last multi-length vector
3793 for (op
= t
->operands
; op
--;)
3794 if (t
->operand_types
[op
].bitfield
.xmmword
3795 && t
->operand_types
[op
].bitfield
.ymmword
3796 && i
.types
[op
].bitfield
.ymmword
)
3803 /* Check the REX.W bit and VEXW. */
3804 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3805 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3806 else if (i
.tm
.opcode_modifier
.vexw
)
3807 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3809 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3811 /* Use 2-byte VEX prefix if possible. */
3813 && i
.vec_encoding
!= vex_encoding_vex3
3814 && i
.tm
.opcode_space
== SPACE_0F
3815 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3817 /* 2-byte VEX prefix. */
3821 i
.vex
.bytes
[0] = 0xc5;
3823 /* Check the REX.R bit. */
3824 r
= (i
.rex
& REX_R
) ? 0 : 1;
3825 i
.vex
.bytes
[1] = (r
<< 7
3826 | register_specifier
<< 3
3827 | vector_length
<< 2
3828 | i
.tm
.opcode_modifier
.opcodeprefix
);
3832 /* 3-byte VEX prefix. */
3835 switch (i
.tm
.opcode_space
)
3841 i
.vex
.bytes
[0] = 0xc4;
3846 i
.vex
.bytes
[0] = 0x8f;
3852 /* The high 3 bits of the second VEX byte are 1's compliment
3853 of RXB bits from REX. */
3854 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3855 | (!dot_insn () ? i
.tm
.opcode_space
3856 : i
.insn_opcode_space
);
3858 i
.vex
.bytes
[2] = (w
<< 7
3859 | register_specifier
<< 3
3860 | vector_length
<< 2
3861 | i
.tm
.opcode_modifier
.opcodeprefix
);
3866 is_evex_encoding (const insn_template
*t
)
3868 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3869 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3870 || t
->opcode_modifier
.sae
;
3874 is_any_vex_encoding (const insn_template
*t
)
3876 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3880 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3882 unsigned int op
, bytes
;
3883 const i386_operand_type
*types
;
3885 if (i
.broadcast
.type
)
3886 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3888 gas_assert (intel_syntax
);
3890 for (op
= 0; op
< t
->operands
; ++op
)
3891 if (t
->operand_types
[op
].bitfield
.baseindex
)
3894 gas_assert (op
< t
->operands
);
3896 if (t
->opcode_modifier
.evex
3897 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3898 switch (i
.broadcast
.bytes
)
3901 if (t
->operand_types
[op
].bitfield
.word
)
3905 if (t
->operand_types
[op
].bitfield
.dword
)
3909 if (t
->operand_types
[op
].bitfield
.qword
)
3913 if (t
->operand_types
[op
].bitfield
.xmmword
)
3915 if (t
->operand_types
[op
].bitfield
.ymmword
)
3917 if (t
->operand_types
[op
].bitfield
.zmmword
)
3924 gas_assert (op
+ 1 < t
->operands
);
3926 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3927 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3928 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3930 types
= &i
.types
[op
+ 1];
3933 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3934 types
= &t
->operand_types
[op
];
3936 if (types
->bitfield
.zmmword
)
3938 else if (types
->bitfield
.ymmword
)
3944 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3945 insn_name (t
), bytes
* 8);
3950 /* Build the EVEX prefix. */
3953 build_evex_prefix (void)
3955 unsigned int register_specifier
, w
;
3956 rex_byte vrex_used
= 0;
3958 /* Check register specifier. */
3959 if (i
.vex
.register_specifier
)
3961 gas_assert ((i
.vrex
& REX_X
) == 0);
3963 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3964 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3965 register_specifier
+= 8;
3966 /* The upper 16 registers are encoded in the fourth byte of the
3968 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3969 i
.vex
.bytes
[3] = 0x8;
3970 register_specifier
= ~register_specifier
& 0xf;
3974 register_specifier
= 0xf;
3976 /* Encode upper 16 vector index register in the fourth byte of
3978 if (!(i
.vrex
& REX_X
))
3979 i
.vex
.bytes
[3] = 0x8;
3984 /* 4 byte EVEX prefix. */
3986 i
.vex
.bytes
[0] = 0x62;
3988 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3990 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
3991 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
3992 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3993 | (!dot_insn () ? i
.tm
.opcode_space
3994 : i
.insn_opcode_space
);
3996 /* The fifth bit of the second EVEX byte is 1's compliment of the
3997 REX_R bit in VREX. */
3998 if (!(i
.vrex
& REX_R
))
3999 i
.vex
.bytes
[1] |= 0x10;
4003 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
4005 /* When all operands are registers, the REX_X bit in REX is not
4006 used. We reuse it to encode the upper 16 registers, which is
4007 indicated by the REX_B bit in VREX. The REX_X bit is encoded
4008 as 1's compliment. */
4009 if ((i
.vrex
& REX_B
))
4012 i
.vex
.bytes
[1] &= ~0x40;
4016 /* EVEX instructions shouldn't need the REX prefix. */
4017 i
.vrex
&= ~vrex_used
;
4018 gas_assert (i
.vrex
== 0);
4020 /* Check the REX.W bit and VEXW. */
4021 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
4022 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
4023 else if (i
.tm
.opcode_modifier
.vexw
)
4024 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
4026 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
4028 /* The third byte of the EVEX prefix. */
4029 i
.vex
.bytes
[2] = ((w
<< 7)
4030 | (register_specifier
<< 3)
4031 | 4 /* Encode the U bit. */
4032 | i
.tm
.opcode_modifier
.opcodeprefix
);
4034 /* The fourth byte of the EVEX prefix. */
4035 /* The zeroing-masking bit. */
4036 if (i
.mask
.reg
&& i
.mask
.zeroing
)
4037 i
.vex
.bytes
[3] |= 0x80;
4039 /* Don't always set the broadcast bit if there is no RC. */
4040 if (i
.rounding
.type
== rc_none
)
4042 /* Encode the vector length. */
4043 unsigned int vec_length
;
4045 if (!i
.tm
.opcode_modifier
.evex
4046 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
4050 /* Determine vector length from the last multi-length vector
4052 for (op
= i
.operands
; op
--;)
4053 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
4054 + i
.tm
.operand_types
[op
].bitfield
.ymmword
4055 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
4057 if (i
.types
[op
].bitfield
.zmmword
)
4059 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4062 else if (i
.types
[op
].bitfield
.ymmword
)
4064 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4067 else if (i
.types
[op
].bitfield
.xmmword
)
4069 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4072 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
4073 && op
== i
.broadcast
.operand
)
4075 switch (get_broadcast_bytes (&i
.tm
, true))
4078 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4081 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4084 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4093 if (op
>= MAX_OPERANDS
)
4097 switch (i
.tm
.opcode_modifier
.evex
)
4099 case EVEXLIG
: /* LL' is ignored */
4100 vec_length
= evexlig
<< 5;
4103 vec_length
= 0 << 5;
4106 vec_length
= 1 << 5;
4109 vec_length
= 2 << 5;
4114 vec_length
= 3 << 5;
4122 i
.vex
.bytes
[3] |= vec_length
;
4123 /* Encode the broadcast bit. */
4124 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
4125 i
.vex
.bytes
[3] |= 0x10;
4127 else if (i
.rounding
.type
!= saeonly
)
4128 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4130 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4133 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4137 process_immext (void)
4141 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4142 which is coded in the same place as an 8-bit immediate field
4143 would be. Here we fake an 8-bit immediate operand from the
4144 opcode suffix stored in tm.extension_opcode.
4146 AVX instructions also use this encoding, for some of
4147 3 argument instructions. */
4149 gas_assert (i
.imm_operands
<= 1
4151 || (is_any_vex_encoding (&i
.tm
)
4152 && i
.operands
<= 4)));
4154 exp
= &im_expressions
[i
.imm_operands
++];
4155 i
.op
[i
.operands
].imms
= exp
;
4156 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4158 exp
->X_op
= O_constant
;
4159 exp
->X_add_number
= i
.tm
.extension_opcode
;
4160 i
.tm
.extension_opcode
= None
;
4167 switch (i
.tm
.opcode_modifier
.prefixok
)
4175 as_bad (_("invalid instruction `%s' after `%s'"),
4176 insn_name (&i
.tm
), i
.hle_prefix
);
4179 if (i
.prefix
[LOCK_PREFIX
])
4181 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4185 case PrefixHLERelease
:
4186 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4188 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4192 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4194 as_bad (_("memory destination needed for instruction `%s'"
4195 " after `xrelease'"), insn_name (&i
.tm
));
4202 /* Encode aligned vector move as unaligned vector move. */
4205 encode_with_unaligned_vector_move (void)
4207 switch (i
.tm
.base_opcode
)
4209 case 0x28: /* Load instructions. */
4210 case 0x29: /* Store instructions. */
4211 /* movaps/movapd/vmovaps/vmovapd. */
4212 if (i
.tm
.opcode_space
== SPACE_0F
4213 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4214 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4216 case 0x6f: /* Load instructions. */
4217 case 0x7f: /* Store instructions. */
4218 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4219 if (i
.tm
.opcode_space
== SPACE_0F
4220 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4221 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4228 /* Try the shortest encoding by shortening operand size. */
4231 optimize_encoding (void)
4235 if (i
.tm
.mnem_off
== MN_lea
)
4238 lea symbol, %rN -> mov $symbol, %rN
4239 lea (%rM), %rN -> mov %rM, %rN
4240 lea (,%rM,1), %rN -> mov %rM, %rN
4242 and in 32-bit mode for 16-bit addressing
4244 lea (%rM), %rN -> movzx %rM, %rN
4246 and in 64-bit mode zap 32-bit addressing in favor of using a
4247 32-bit (or less) destination.
4249 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4251 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4252 i
.tm
.opcode_modifier
.size
= SIZE32
;
4253 i
.prefix
[ADDR_PREFIX
] = 0;
4256 if (!i
.index_reg
&& !i
.base_reg
)
4259 lea symbol, %rN -> mov $symbol, %rN
4261 if (flag_code
== CODE_64BIT
)
4263 /* Don't transform a relocation to a 16-bit one. */
4265 && i
.op
[0].disps
->X_op
!= O_constant
4266 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4269 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4270 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4272 i
.tm
.base_opcode
= 0xb8;
4273 i
.tm
.opcode_modifier
.modrm
= 0;
4274 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4275 i
.types
[0].bitfield
.imm32
= 1;
4278 i
.tm
.opcode_modifier
.size
= SIZE16
;
4279 i
.types
[0].bitfield
.imm16
= 1;
4284 /* Subject to further optimization below. */
4285 i
.tm
.base_opcode
= 0xc7;
4286 i
.tm
.extension_opcode
= 0;
4287 i
.types
[0].bitfield
.imm32s
= 1;
4288 i
.types
[0].bitfield
.baseindex
= 0;
4291 /* Outside of 64-bit mode address and operand sizes have to match if
4292 a relocation is involved, as otherwise we wouldn't (currently) or
4293 even couldn't express the relocation correctly. */
4294 else if (i
.op
[0].disps
4295 && i
.op
[0].disps
->X_op
!= O_constant
4296 && ((!i
.prefix
[ADDR_PREFIX
])
4297 != (flag_code
== CODE_32BIT
4298 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4299 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4301 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4302 destination is going to grow encoding size. */
4303 else if (flag_code
== CODE_16BIT
4304 && (optimize
<= 1 || optimize_for_space
)
4305 && !i
.prefix
[ADDR_PREFIX
]
4306 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4310 i
.tm
.base_opcode
= 0xb8;
4311 i
.tm
.opcode_modifier
.modrm
= 0;
4312 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4313 i
.types
[0].bitfield
.imm32
= 1;
4315 i
.types
[0].bitfield
.imm16
= 1;
4318 && i
.op
[0].disps
->X_op
== O_constant
4319 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4320 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4322 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4323 i
.op
[0].disps
->X_add_number
&= 0xffff;
4326 i
.tm
.operand_types
[0] = i
.types
[0];
4330 i
.op
[0].imms
= &im_expressions
[0];
4331 i
.op
[0].imms
->X_op
= O_absent
;
4334 else if (i
.op
[0].disps
4335 && (i
.op
[0].disps
->X_op
!= O_constant
4336 || i
.op
[0].disps
->X_add_number
))
4341 lea (%rM), %rN -> mov %rM, %rN
4342 lea (,%rM,1), %rN -> mov %rM, %rN
4343 lea (%rM), %rN -> movzx %rM, %rN
4345 const reg_entry
*addr_reg
;
4347 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4348 addr_reg
= i
.base_reg
;
4349 else if (!i
.base_reg
4350 && i
.index_reg
->reg_num
!= RegIZ
4351 && !i
.log2_scale_factor
)
4352 addr_reg
= i
.index_reg
;
4356 if (addr_reg
->reg_type
.bitfield
.word
4357 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4359 if (flag_code
!= CODE_32BIT
)
4361 i
.tm
.opcode_space
= SPACE_0F
;
4362 i
.tm
.base_opcode
= 0xb7;
4365 i
.tm
.base_opcode
= 0x8b;
4367 if (addr_reg
->reg_type
.bitfield
.dword
4368 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4369 i
.tm
.opcode_modifier
.size
= SIZE32
;
4371 i
.op
[0].regs
= addr_reg
;
4376 i
.disp_operands
= 0;
4377 i
.prefix
[ADDR_PREFIX
] = 0;
4378 i
.prefix
[SEG_PREFIX
] = 0;
4382 if (optimize_for_space
4383 && i
.tm
.mnem_off
== MN_test
4384 && i
.reg_operands
== 1
4385 && i
.imm_operands
== 1
4386 && !i
.types
[1].bitfield
.byte
4387 && i
.op
[0].imms
->X_op
== O_constant
4388 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4391 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4393 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4394 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4396 i
.types
[1].bitfield
.byte
= 1;
4397 /* Ignore the suffix. */
4399 /* Convert to byte registers. */
4400 if (i
.types
[1].bitfield
.word
)
4402 else if (i
.types
[1].bitfield
.dword
)
4406 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4411 else if (flag_code
== CODE_64BIT
4412 && i
.tm
.opcode_space
== SPACE_BASE
4413 && ((i
.types
[1].bitfield
.qword
4414 && i
.reg_operands
== 1
4415 && i
.imm_operands
== 1
4416 && i
.op
[0].imms
->X_op
== O_constant
4417 && ((i
.tm
.base_opcode
== 0xb8
4418 && i
.tm
.extension_opcode
== None
4419 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4420 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4421 && (i
.tm
.base_opcode
== 0x24
4422 || (i
.tm
.base_opcode
== 0x80
4423 && i
.tm
.extension_opcode
== 0x4)
4424 || i
.tm
.mnem_off
== MN_test
4425 || ((i
.tm
.base_opcode
| 1) == 0xc7
4426 && i
.tm
.extension_opcode
== 0x0)))
4427 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4428 && i
.tm
.base_opcode
== 0x83
4429 && i
.tm
.extension_opcode
== 0x4)))
4430 || (i
.types
[0].bitfield
.qword
4431 && ((i
.reg_operands
== 2
4432 && i
.op
[0].regs
== i
.op
[1].regs
4433 && (i
.tm
.mnem_off
== MN_xor
4434 || i
.tm
.mnem_off
== MN_sub
))
4435 || i
.tm
.mnem_off
== MN_clr
))))
4438 andq $imm31, %r64 -> andl $imm31, %r32
4439 andq $imm7, %r64 -> andl $imm7, %r32
4440 testq $imm31, %r64 -> testl $imm31, %r32
4441 xorq %r64, %r64 -> xorl %r32, %r32
4442 subq %r64, %r64 -> subl %r32, %r32
4443 movq $imm31, %r64 -> movl $imm31, %r32
4444 movq $imm32, %r64 -> movl $imm32, %r32
4446 i
.tm
.opcode_modifier
.size
= SIZE32
;
4449 i
.types
[0].bitfield
.imm32
= 1;
4450 i
.types
[0].bitfield
.imm32s
= 0;
4451 i
.types
[0].bitfield
.imm64
= 0;
4455 i
.types
[0].bitfield
.dword
= 1;
4456 i
.types
[0].bitfield
.qword
= 0;
4458 i
.types
[1].bitfield
.dword
= 1;
4459 i
.types
[1].bitfield
.qword
= 0;
4460 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4463 movq $imm31, %r64 -> movl $imm31, %r32
4464 movq $imm32, %r64 -> movl $imm32, %r32
4466 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4467 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4468 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4469 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4472 movq $imm31, %r64 -> movl $imm31, %r32
4474 i
.tm
.base_opcode
= 0xb8;
4475 i
.tm
.extension_opcode
= None
;
4476 i
.tm
.opcode_modifier
.w
= 0;
4477 i
.tm
.opcode_modifier
.modrm
= 0;
4481 else if (optimize
> 1
4482 && !optimize_for_space
4483 && i
.reg_operands
== 2
4484 && i
.op
[0].regs
== i
.op
[1].regs
4485 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4486 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4489 andb %rN, %rN -> testb %rN, %rN
4490 andw %rN, %rN -> testw %rN, %rN
4491 andq %rN, %rN -> testq %rN, %rN
4492 orb %rN, %rN -> testb %rN, %rN
4493 orw %rN, %rN -> testw %rN, %rN
4494 orq %rN, %rN -> testq %rN, %rN
4496 and outside of 64-bit mode
4498 andl %rN, %rN -> testl %rN, %rN
4499 orl %rN, %rN -> testl %rN, %rN
4501 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4503 else if (i
.tm
.base_opcode
== 0xba
4504 && i
.tm
.opcode_space
== SPACE_0F
4505 && i
.reg_operands
== 1
4506 && i
.op
[0].imms
->X_op
== O_constant
4507 && i
.op
[0].imms
->X_add_number
>= 0)
4510 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4511 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4512 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4514 With <BT> one of bts, btr, and bts also:
4515 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4516 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4521 if (i
.tm
.extension_opcode
!= 4)
4523 if (i
.types
[1].bitfield
.qword
4524 && i
.op
[0].imms
->X_add_number
< 32
4525 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4526 i
.tm
.opcode_modifier
.size
= SIZE32
;
4529 if (i
.types
[1].bitfield
.word
4530 && i
.op
[0].imms
->X_add_number
< 16)
4531 i
.tm
.opcode_modifier
.size
= SIZE32
;
4534 if (i
.op
[0].imms
->X_add_number
< 16)
4535 i
.tm
.opcode_modifier
.size
= SIZE16
;
4539 else if (i
.reg_operands
== 3
4540 && i
.op
[0].regs
== i
.op
[1].regs
4541 && !i
.types
[2].bitfield
.xmmword
4542 && (i
.tm
.opcode_modifier
.vex
4543 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4544 && is_evex_encoding (&i
.tm
)
4545 && (i
.vec_encoding
!= vex_encoding_evex
4546 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4547 || is_cpu (&i
.tm
, CpuAVX512VL
)
4548 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4549 && i
.types
[2].bitfield
.ymmword
))))
4550 && i
.tm
.opcode_space
== SPACE_0F
4551 && ((i
.tm
.base_opcode
| 2) == 0x57
4552 || i
.tm
.base_opcode
== 0xdf
4553 || i
.tm
.base_opcode
== 0xef
4554 || (i
.tm
.base_opcode
| 3) == 0xfb
4555 || i
.tm
.base_opcode
== 0x42
4556 || i
.tm
.base_opcode
== 0x47))
4559 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4561 EVEX VOP %zmmM, %zmmM, %zmmN
4562 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4563 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4564 EVEX VOP %ymmM, %ymmM, %ymmN
4565 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4566 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4567 VEX VOP %ymmM, %ymmM, %ymmN
4568 -> VEX VOP %xmmM, %xmmM, %xmmN
4569 VOP, one of vpandn and vpxor:
4570 VEX VOP %ymmM, %ymmM, %ymmN
4571 -> VEX VOP %xmmM, %xmmM, %xmmN
4572 VOP, one of vpandnd and vpandnq:
4573 EVEX VOP %zmmM, %zmmM, %zmmN
4574 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4575 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4576 EVEX VOP %ymmM, %ymmM, %ymmN
4577 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4578 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4579 VOP, one of vpxord and vpxorq:
4580 EVEX VOP %zmmM, %zmmM, %zmmN
4581 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4582 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4583 EVEX VOP %ymmM, %ymmM, %ymmN
4584 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4585 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4586 VOP, one of kxord and kxorq:
4587 VEX VOP %kM, %kM, %kN
4588 -> VEX kxorw %kM, %kM, %kN
4589 VOP, one of kandnd and kandnq:
4590 VEX VOP %kM, %kM, %kN
4591 -> VEX kandnw %kM, %kM, %kN
4593 if (is_evex_encoding (&i
.tm
))
4595 if (i
.vec_encoding
!= vex_encoding_evex
)
4597 i
.tm
.opcode_modifier
.vex
= VEX128
;
4598 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4599 i
.tm
.opcode_modifier
.evex
= 0;
4600 i
.vec_encoding
= vex_encoding_vex
;
4603 else if (optimize
> 1)
4604 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4608 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4610 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4611 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4614 i
.tm
.opcode_modifier
.vex
= VEX128
;
4616 if (i
.tm
.opcode_modifier
.vex
)
4617 for (j
= 0; j
< 3; j
++)
4619 i
.types
[j
].bitfield
.xmmword
= 1;
4620 i
.types
[j
].bitfield
.ymmword
= 0;
4623 else if (i
.vec_encoding
!= vex_encoding_evex
4624 && !i
.types
[0].bitfield
.zmmword
4625 && !i
.types
[1].bitfield
.zmmword
4627 && !i
.broadcast
.type
4628 && !i
.broadcast
.bytes
4629 && is_evex_encoding (&i
.tm
)
4630 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4631 || (i
.tm
.base_opcode
& ~4) == 0xdb
4632 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4633 && i
.tm
.extension_opcode
== None
)
4636 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4637 vmovdqu32 and vmovdqu64:
4638 EVEX VOP %xmmM, %xmmN
4639 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4640 EVEX VOP %ymmM, %ymmN
4641 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4643 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4645 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4647 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4649 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4650 VOP, one of vpand, vpandn, vpor, vpxor:
4651 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4652 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4653 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4654 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4655 EVEX VOP{d,q} mem, %xmmM, %xmmN
4656 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4657 EVEX VOP{d,q} mem, %ymmM, %ymmN
4658 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4660 for (j
= 0; j
< i
.operands
; j
++)
4661 if (operand_type_check (i
.types
[j
], disp
)
4662 && i
.op
[j
].disps
->X_op
== O_constant
)
4664 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4665 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4666 bytes, we choose EVEX Disp8 over VEX Disp32. */
4667 int evex_disp8
, vex_disp8
;
4668 unsigned int memshift
= i
.memshift
;
4669 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4671 evex_disp8
= fits_in_disp8 (n
);
4673 vex_disp8
= fits_in_disp8 (n
);
4674 if (evex_disp8
!= vex_disp8
)
4676 i
.memshift
= memshift
;
4680 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4683 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4684 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4685 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4686 i
.tm
.opcode_modifier
.vex
4687 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4688 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4689 /* VPAND, VPOR, and VPXOR are commutative. */
4690 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4691 i
.tm
.opcode_modifier
.commutative
= 1;
4692 i
.tm
.opcode_modifier
.evex
= 0;
4693 i
.tm
.opcode_modifier
.masking
= 0;
4694 i
.tm
.opcode_modifier
.broadcast
= 0;
4695 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4698 i
.types
[j
].bitfield
.disp8
4699 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4701 else if (optimize_for_space
4702 && i
.tm
.base_opcode
== 0x29
4703 && i
.tm
.opcode_space
== SPACE_0F38
4704 && i
.operands
== i
.reg_operands
4705 && i
.op
[0].regs
== i
.op
[1].regs
4706 && (!i
.tm
.opcode_modifier
.vex
4707 || !(i
.op
[0].regs
->reg_flags
& RegRex
))
4708 && !is_evex_encoding (&i
.tm
))
4711 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4712 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4713 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4715 i
.tm
.opcode_space
= SPACE_0F
;
4716 i
.tm
.base_opcode
= 0x76;
4718 else if (((i
.tm
.base_opcode
>= 0x64
4719 && i
.tm
.base_opcode
<= 0x66
4720 && i
.tm
.opcode_space
== SPACE_0F
)
4721 || (i
.tm
.base_opcode
== 0x37
4722 && i
.tm
.opcode_space
== SPACE_0F38
))
4723 && i
.operands
== i
.reg_operands
4724 && i
.op
[0].regs
== i
.op
[1].regs
4725 && !is_evex_encoding (&i
.tm
))
4728 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4729 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4730 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4731 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4732 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4733 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4735 i
.tm
.opcode_space
= SPACE_0F
;
4736 i
.tm
.base_opcode
= 0xef;
4737 if (i
.tm
.opcode_modifier
.vex
&& (i
.op
[0].regs
->reg_flags
& RegRex
))
4739 if (i
.operands
== 2)
4741 gas_assert (i
.tm
.opcode_modifier
.sse2avx
);
4747 i
.op
[2].regs
= i
.op
[0].regs
;
4748 i
.types
[2] = i
.types
[0];
4749 i
.flags
[2] = i
.flags
[0];
4750 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4752 i
.tm
.opcode_modifier
.sse2avx
= 0;
4754 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
+ 8;
4755 i
.op
[1].regs
= i
.op
[0].regs
;
4758 else if (optimize_for_space
4759 && i
.tm
.base_opcode
== 0x59
4760 && i
.tm
.opcode_space
== SPACE_0F38
4761 && i
.operands
== i
.reg_operands
4762 && i
.tm
.opcode_modifier
.vex
4763 && !(i
.op
[0].regs
->reg_flags
& RegRex
)
4764 && i
.op
[0].regs
->reg_type
.bitfield
.xmmword
4765 && i
.vec_encoding
!= vex_encoding_vex3
)
4768 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
4770 i
.tm
.opcode_space
= SPACE_0F
;
4771 i
.tm
.base_opcode
= 0x6c;
4772 i
.tm
.opcode_modifier
.vexvvvv
= 1;
4778 i
.op
[2].regs
= i
.op
[0].regs
;
4779 i
.types
[2] = i
.types
[0];
4780 i
.flags
[2] = i
.flags
[0];
4781 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4783 swap_2_operands (1, 2);
4787 /* Return non-zero for load instruction. */
4793 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4794 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4798 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4799 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4800 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4804 if (i
.tm
.mnem_off
== MN_pop
)
4808 if (i
.tm
.opcode_space
== SPACE_BASE
)
4811 if (i
.tm
.base_opcode
== 0x9d
4812 || i
.tm
.base_opcode
== 0x61)
4815 /* movs, cmps, lods, scas. */
4816 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4820 if (base_opcode
== 0x6f
4821 || i
.tm
.base_opcode
== 0xd7)
4823 /* NB: For AMD-specific insns with implicit memory operands,
4824 they're intentionally not covered. */
4827 /* No memory operand. */
4828 if (!i
.mem_operands
)
4833 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4836 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4838 /* test, not, neg, mul, imul, div, idiv. */
4839 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4843 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4846 /* add, or, adc, sbb, and, sub, xor, cmp. */
4847 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4850 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4851 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4852 && i
.tm
.extension_opcode
!= 6)
4855 /* Check for x87 instructions. */
4856 if ((base_opcode
| 6) == 0xdf)
4858 /* Skip fst, fstp, fstenv, fstcw. */
4859 if (i
.tm
.base_opcode
== 0xd9
4860 && (i
.tm
.extension_opcode
== 2
4861 || i
.tm
.extension_opcode
== 3
4862 || i
.tm
.extension_opcode
== 6
4863 || i
.tm
.extension_opcode
== 7))
4866 /* Skip fisttp, fist, fistp, fstp. */
4867 if (i
.tm
.base_opcode
== 0xdb
4868 && (i
.tm
.extension_opcode
== 1
4869 || i
.tm
.extension_opcode
== 2
4870 || i
.tm
.extension_opcode
== 3
4871 || i
.tm
.extension_opcode
== 7))
4874 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4875 if (i
.tm
.base_opcode
== 0xdd
4876 && (i
.tm
.extension_opcode
== 1
4877 || i
.tm
.extension_opcode
== 2
4878 || i
.tm
.extension_opcode
== 3
4879 || i
.tm
.extension_opcode
== 6
4880 || i
.tm
.extension_opcode
== 7))
4883 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4884 if (i
.tm
.base_opcode
== 0xdf
4885 && (i
.tm
.extension_opcode
== 1
4886 || i
.tm
.extension_opcode
== 2
4887 || i
.tm
.extension_opcode
== 3
4888 || i
.tm
.extension_opcode
== 6
4889 || i
.tm
.extension_opcode
== 7))
4895 else if (i
.tm
.opcode_space
== SPACE_0F
)
4897 /* bt, bts, btr, btc. */
4898 if (i
.tm
.base_opcode
== 0xba
4899 && (i
.tm
.extension_opcode
| 3) == 7)
4902 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4903 if (i
.tm
.base_opcode
== 0xc7
4904 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4905 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4906 || i
.tm
.extension_opcode
== 6))
4909 /* fxrstor, ldmxcsr, xrstor. */
4910 if (i
.tm
.base_opcode
== 0xae
4911 && (i
.tm
.extension_opcode
== 1
4912 || i
.tm
.extension_opcode
== 2
4913 || i
.tm
.extension_opcode
== 5))
4916 /* lgdt, lidt, lmsw. */
4917 if (i
.tm
.base_opcode
== 0x01
4918 && (i
.tm
.extension_opcode
== 2
4919 || i
.tm
.extension_opcode
== 3
4920 || i
.tm
.extension_opcode
== 6))
4924 dest
= i
.operands
- 1;
4926 /* Check fake imm8 operand and 3 source operands. */
4927 if ((i
.tm
.opcode_modifier
.immext
4928 || i
.reg_operands
+ i
.mem_operands
== 4)
4929 && i
.types
[dest
].bitfield
.imm8
)
4932 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4933 if (i
.tm
.opcode_space
== SPACE_BASE
4934 && ((base_opcode
| 0x38) == 0x39
4935 || (base_opcode
| 2) == 0x87))
4938 if (i
.tm
.mnem_off
== MN_xadd
)
4941 /* Check for load instruction. */
4942 return (i
.types
[dest
].bitfield
.class != ClassNone
4943 || i
.types
[dest
].bitfield
.instance
== Accum
);
4946 /* Output lfence, 0xfaee8, after instruction. */
4949 insert_lfence_after (void)
4951 if (lfence_after_load
&& load_insn_p ())
4953 /* There are also two REP string instructions that require
4954 special treatment. Specifically, the compare string (CMPS)
4955 and scan string (SCAS) instructions set EFLAGS in a manner
4956 that depends on the data being compared/scanned. When used
4957 with a REP prefix, the number of iterations may therefore
4958 vary depending on this data. If the data is a program secret
4959 chosen by the adversary using an LVI method,
4960 then this data-dependent behavior may leak some aspect
4962 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4963 && i
.prefix
[REP_PREFIX
])
4965 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4968 char *p
= frag_more (3);
4975 /* Output lfence, 0xfaee8, before instruction. */
4978 insert_lfence_before (void)
4982 if (i
.tm
.opcode_space
!= SPACE_BASE
)
4985 if (i
.tm
.base_opcode
== 0xff
4986 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4988 /* Insert lfence before indirect branch if needed. */
4990 if (lfence_before_indirect_branch
== lfence_branch_none
)
4993 if (i
.operands
!= 1)
4996 if (i
.reg_operands
== 1)
4998 /* Indirect branch via register. Don't insert lfence with
4999 -mlfence-after-load=yes. */
5000 if (lfence_after_load
5001 || lfence_before_indirect_branch
== lfence_branch_memory
)
5004 else if (i
.mem_operands
== 1
5005 && lfence_before_indirect_branch
!= lfence_branch_register
)
5007 as_warn (_("indirect `%s` with memory operand should be avoided"),
5014 if (last_insn
.kind
!= last_insn_other
5015 && last_insn
.seg
== now_seg
)
5017 as_warn_where (last_insn
.file
, last_insn
.line
,
5018 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
5019 last_insn
.name
, insn_name (&i
.tm
));
5030 /* Output or/not/shl and lfence before near ret. */
5031 if (lfence_before_ret
!= lfence_before_ret_none
5032 && (i
.tm
.base_opcode
| 1) == 0xc3)
5034 if (last_insn
.kind
!= last_insn_other
5035 && last_insn
.seg
== now_seg
)
5037 as_warn_where (last_insn
.file
, last_insn
.line
,
5038 _("`%s` skips -mlfence-before-ret on `%s`"),
5039 last_insn
.name
, insn_name (&i
.tm
));
5043 /* Near ret ingore operand size override under CPU64. */
5044 char prefix
= flag_code
== CODE_64BIT
5046 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
5048 if (lfence_before_ret
== lfence_before_ret_not
)
5050 /* not: 0xf71424, may add prefix
5051 for operand size override or 64-bit code. */
5052 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
5066 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
5069 if (lfence_before_ret
== lfence_before_ret_or
)
5071 /* or: 0x830c2400, may add prefix
5072 for operand size override or 64-bit code. */
5078 /* shl: 0xc1242400, may add prefix
5079 for operand size override or 64-bit code. */
5094 /* Shared helper for md_assemble() and s_insn(). */
5095 static void init_globals (void)
5099 memset (&i
, '\0', sizeof (i
));
5100 i
.rounding
.type
= rc_none
;
5101 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5102 i
.reloc
[j
] = NO_RELOC
;
5103 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
5104 memset (im_expressions
, '\0', sizeof (im_expressions
));
5105 save_stack_p
= save_stack
;
5108 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5109 parsing pass. Instead of introducing a rarely use new insn attribute this
5110 utilizes a common pattern between affected templates. It is deemed
5111 acceptable that this will lead to unnecessary pass 2 preparations in a
5112 limited set of cases. */
5113 static INLINE
bool may_need_pass2 (const insn_template
*t
)
5115 return t
->opcode_modifier
.sse2avx
5116 /* Note that all SSE2AVX templates have at least one operand. */
5117 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
5118 : (t
->opcode_space
== SPACE_0F
5119 && (t
->base_opcode
| 1) == 0xbf)
5120 || (t
->opcode_space
== SPACE_BASE
5121 && t
->base_opcode
== 0x63);
5124 /* This is the guts of the machine-dependent assembler. LINE points to a
5125 machine dependent instruction. This function is supposed to emit
5126 the frags/bytes it assembles to. */
5129 md_assemble (char *line
)
5132 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
5133 const char *end
, *pass1_mnem
= NULL
;
5134 enum i386_error pass1_err
= 0;
5135 const insn_template
*t
;
5137 /* Initialize globals. */
5138 current_templates
= NULL
;
5142 /* First parse an instruction mnemonic & call i386_operand for the operands.
5143 We assume that the scrubber has arranged it so that line[0] is the valid
5144 start of a (possibly prefixed) mnemonic. */
5146 end
= parse_insn (line
, mnemonic
, false);
5149 if (pass1_mnem
!= NULL
)
5151 if (i
.error
!= no_error
)
5153 gas_assert (current_templates
!= NULL
);
5154 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
5156 /* No point in trying a 2nd pass - it'll only find the same suffix
5158 mnem_suffix
= i
.suffix
;
5163 t
= current_templates
->start
;
5164 if (may_need_pass2 (t
))
5166 /* Make a copy of the full line in case we need to retry. */
5167 copy
= xstrdup (line
);
5170 mnem_suffix
= i
.suffix
;
5172 line
= parse_operands (line
, mnemonic
);
5180 /* Now we've parsed the mnemonic into a set of templates, and have the
5181 operands at hand. */
5183 /* All Intel opcodes have reversed operands except for "bound", "enter",
5184 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
5185 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
5186 intersegment "jmp" and "call" instructions with 2 immediate operands so
5187 that the immediate segment precedes the offset consistently in Intel and
5191 && (t
->mnem_off
!= MN_bound
)
5192 && !startswith (mnemonic
, "invlpg")
5193 && !startswith (mnemonic
, "monitor")
5194 && !startswith (mnemonic
, "mwait")
5195 && (t
->mnem_off
!= MN_pvalidate
)
5196 && !startswith (mnemonic
, "rmp")
5197 && (t
->mnem_off
!= MN_tpause
)
5198 && (t
->mnem_off
!= MN_umwait
)
5199 && !(i
.operands
== 2
5200 && operand_type_check (i
.types
[0], imm
)
5201 && operand_type_check (i
.types
[1], imm
)))
5204 /* The order of the immediates should be reversed
5205 for 2 immediates extrq and insertq instructions */
5206 if (i
.imm_operands
== 2
5207 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
5208 swap_2_operands (0, 1);
5212 /* For USER_MSR instructions, imm32 stands for the name of an model specific
5213 register (MSR). That's an unsigned quantity, whereas all other insns with
5214 32-bit immediate and 64-bit operand size use sign-extended
5215 immediates (imm32s). Therefore these insns are special-cased, bypassing
5216 the normal handling of immediates here. */
5217 if (is_cpu(current_templates
->start
, CpuUSER_MSR
))
5219 for (j
= 0; j
< i
.operands
; j
++)
5221 if (operand_type_check(i
.types
[j
], imm
))
5222 i
.types
[j
] = smallest_imm_type (i
.op
[j
].imms
->X_add_number
);
5229 if (i
.disp_operands
&& !optimize_disp (t
))
5232 /* Next, we find a template that matches the given insn,
5233 making sure the overlap of the given operands types is consistent
5234 with the template operand types. */
5236 if (!(t
= match_template (mnem_suffix
)))
5238 const char *err_msg
;
5240 if (copy
&& !mnem_suffix
)
5245 pass1_err
= i
.error
;
5246 pass1_mnem
= insn_name (current_templates
->start
);
5250 /* If a non-/only-64bit template (group) was found in pass 1, and if
5251 _some_ template (group) was found in pass 2, squash pass 1's
5253 if (pass1_err
== unsupported_64bit
)
5259 switch (pass1_mnem
? pass1_err
: i
.error
)
5263 case operand_size_mismatch
:
5264 err_msg
= _("operand size mismatch");
5266 case operand_type_mismatch
:
5267 err_msg
= _("operand type mismatch");
5269 case register_type_mismatch
:
5270 err_msg
= _("register type mismatch");
5272 case number_of_operands_mismatch
:
5273 err_msg
= _("number of operands mismatch");
5275 case invalid_instruction_suffix
:
5276 err_msg
= _("invalid instruction suffix");
5279 err_msg
= _("constant doesn't fit in 4 bits");
5281 case unsupported_with_intel_mnemonic
:
5282 err_msg
= _("unsupported with Intel mnemonic");
5284 case unsupported_syntax
:
5285 err_msg
= _("unsupported syntax");
5288 as_bad (_("unsupported instruction `%s'"),
5289 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5291 case unsupported_on_arch
:
5292 as_bad (_("`%s' is not supported on `%s%s'"),
5293 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5294 cpu_arch_name
? cpu_arch_name
: default_arch
,
5295 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5297 case unsupported_64bit
:
5298 if (ISLOWER (mnem_suffix
))
5300 if (flag_code
== CODE_64BIT
)
5301 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5302 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5305 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5306 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5311 if (flag_code
== CODE_64BIT
)
5312 as_bad (_("`%s' is not supported in 64-bit mode"),
5313 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5315 as_bad (_("`%s' is only supported in 64-bit mode"),
5316 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5319 case invalid_sib_address
:
5320 err_msg
= _("invalid SIB address");
5322 case invalid_vsib_address
:
5323 err_msg
= _("invalid VSIB address");
5325 case invalid_vector_register_set
:
5326 err_msg
= _("mask, index, and destination registers must be distinct");
5328 case invalid_tmm_register_set
:
5329 err_msg
= _("all tmm registers must be distinct");
5331 case invalid_dest_and_src_register_set
:
5332 err_msg
= _("destination and source registers must be distinct");
5334 case unsupported_vector_index_register
:
5335 err_msg
= _("unsupported vector index register");
5337 case unsupported_broadcast
:
5338 err_msg
= _("unsupported broadcast");
5340 case broadcast_needed
:
5341 err_msg
= _("broadcast is needed for operand of such type");
5343 case unsupported_masking
:
5344 err_msg
= _("unsupported masking");
5346 case mask_not_on_destination
:
5347 err_msg
= _("mask not on destination operand");
5349 case no_default_mask
:
5350 err_msg
= _("default mask isn't allowed");
5352 case unsupported_rc_sae
:
5353 err_msg
= _("unsupported static rounding/sae");
5355 case invalid_register_operand
:
5356 err_msg
= _("invalid register operand");
5358 case internal_error
:
5359 err_msg
= _("internal error");
5362 as_bad (_("%s for `%s'"), err_msg
,
5363 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5369 if (sse_check
!= check_none
5370 /* The opcode space check isn't strictly needed; it's there only to
5371 bypass the logic below when easily possible. */
5372 && t
->opcode_space
>= SPACE_0F
5373 && t
->opcode_space
<= SPACE_0F3A
5374 && !is_cpu (&i
.tm
, CpuSSE4a
)
5375 && !is_any_vex_encoding (t
))
5379 for (j
= 0; j
< t
->operands
; ++j
)
5381 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5383 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5387 if (j
>= t
->operands
&& simd
)
5388 (sse_check
== check_warning
5390 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5393 if (i
.tm
.opcode_modifier
.fwait
)
5394 if (!add_prefix (FWAIT_OPCODE
))
5397 /* Check if REP prefix is OK. */
5398 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5400 as_bad (_("invalid instruction `%s' after `%s'"),
5401 insn_name (&i
.tm
), i
.rep_prefix
);
5405 /* Check for lock without a lockable instruction. Destination operand
5406 must be memory unless it is xchg (0x86). */
5407 if (i
.prefix
[LOCK_PREFIX
])
5409 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5410 || i
.mem_operands
== 0
5411 || (i
.tm
.base_opcode
!= 0x86
5412 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5414 as_bad (_("expecting lockable instruction after `lock'"));
5418 /* Zap the redundant prefix from XCHG when optimizing. */
5419 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5420 i
.prefix
[LOCK_PREFIX
] = 0;
5423 if (is_any_vex_encoding (&i
.tm
)
5424 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5425 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5427 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5428 if (i
.prefix
[DATA_PREFIX
])
5430 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5434 /* Don't allow e.g. KMOV in TLS code sequences. */
5435 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5438 case BFD_RELOC_386_TLS_GOTIE
:
5439 case BFD_RELOC_386_TLS_LE_32
:
5440 case BFD_RELOC_X86_64_GOTTPOFF
:
5441 case BFD_RELOC_X86_64_TLSLD
:
5442 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5449 /* Check if HLE prefix is OK. */
5450 if (i
.hle_prefix
&& !check_hle ())
5453 /* Check BND prefix. */
5454 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5455 as_bad (_("expecting valid branch instruction after `bnd'"));
5457 /* Check NOTRACK prefix. */
5458 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5459 as_bad (_("expecting indirect branch instruction after `notrack'"));
5461 if (is_cpu (&i
.tm
, CpuMPX
))
5463 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5464 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5465 else if (flag_code
!= CODE_16BIT
5466 ? i
.prefix
[ADDR_PREFIX
]
5467 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5468 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5471 /* Insert BND prefix. */
5472 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5474 if (!i
.prefix
[BND_PREFIX
])
5475 add_prefix (BND_PREFIX_OPCODE
);
5476 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5478 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5479 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5483 /* Check string instruction segment overrides. */
5484 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5486 gas_assert (i
.mem_operands
);
5487 if (!check_string ())
5489 i
.disp_operands
= 0;
5492 /* The memory operand of (%dx) should be only used with input/output
5493 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5494 if (i
.input_output_operand
5495 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5496 || i
.tm
.opcode_space
!= SPACE_BASE
))
5498 as_bad (_("input/output port address isn't allowed with `%s'"),
5503 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5504 optimize_encoding ();
5506 /* Past optimization there's no need to distinguish vex_encoding_evex and
5507 vex_encoding_evex512 anymore. */
5508 if (i
.vec_encoding
== vex_encoding_evex512
)
5509 i
.vec_encoding
= vex_encoding_evex
;
5511 if (use_unaligned_vector_move
)
5512 encode_with_unaligned_vector_move ();
5514 if (!process_suffix ())
5517 /* Check if IP-relative addressing requirements can be satisfied. */
5518 if (is_cpu (&i
.tm
, CpuPREFETCHI
)
5519 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5520 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5522 /* Update operand types and check extended states. */
5523 for (j
= 0; j
< i
.operands
; j
++)
5525 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5526 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5531 i
.xstate
|= xstate_mmx
;
5534 i
.xstate
|= xstate_mask
;
5537 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5538 i
.xstate
|= xstate_tmm
;
5539 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
5540 && !i
.tm
.opcode_modifier
.vex
5541 && vector_size
>= VSZ512
)
5542 i
.xstate
|= xstate_zmm
;
5543 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
5544 && vector_size
>= VSZ256
)
5545 i
.xstate
|= xstate_ymm
;
5546 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5547 i
.xstate
|= xstate_xmm
;
5552 /* Make still unresolved immediate matches conform to size of immediate
5553 given in i.suffix. */
5554 if (!finalize_imm ())
5557 if (i
.types
[0].bitfield
.imm1
)
5558 i
.imm_operands
= 0; /* kludge for shift insns. */
5560 /* For insns with operands there are more diddles to do to the opcode. */
5563 if (!process_operands ())
5566 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5568 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5569 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5572 if (is_any_vex_encoding (&i
.tm
))
5574 if (!cpu_arch_flags
.bitfield
.cpui286
)
5576 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5581 /* Check for explicit REX prefix. */
5582 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5584 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5588 if (i
.tm
.opcode_modifier
.vex
)
5589 build_vex_prefix (t
);
5591 build_evex_prefix ();
5593 /* The individual REX.RXBW bits got consumed. */
5594 i
.rex
&= REX_OPCODE
;
5597 /* Handle conversion of 'int $3' --> special int3 insn. */
5598 if (i
.tm
.mnem_off
== MN_int
5599 && i
.op
[0].imms
->X_add_number
== 3)
5601 i
.tm
.base_opcode
= INT3_OPCODE
;
5605 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5606 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5607 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5608 && i
.op
[0].disps
->X_op
== O_constant
)
5610 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5611 the absolute address given by the constant. Since ix86 jumps and
5612 calls are pc relative, we need to generate a reloc. */
5613 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5614 i
.op
[0].disps
->X_op
= O_symbol
;
5617 /* For 8 bit registers we need an empty rex prefix. Also if the
5618 instruction already has a prefix, we need to convert old
5619 registers to new ones. */
5621 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5622 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5623 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5624 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5625 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5626 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5631 i
.rex
|= REX_OPCODE
;
5632 for (x
= 0; x
< 2; x
++)
5634 /* Look for 8 bit operand that uses old registers. */
5635 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5636 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5638 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5639 /* In case it is "hi" register, give up. */
5640 if (i
.op
[x
].regs
->reg_num
> 3)
5641 as_bad (_("can't encode register '%s%s' in an "
5642 "instruction requiring REX prefix."),
5643 register_prefix
, i
.op
[x
].regs
->reg_name
);
5645 /* Otherwise it is equivalent to the extended register.
5646 Since the encoding doesn't change this is merely
5647 cosmetic cleanup for debug output. */
5649 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5654 if (i
.rex
== 0 && i
.rex_encoding
)
5656 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5657 that uses legacy register. If it is "hi" register, don't add
5658 the REX_OPCODE byte. */
5660 for (x
= 0; x
< 2; x
++)
5661 if (i
.types
[x
].bitfield
.class == Reg
5662 && i
.types
[x
].bitfield
.byte
5663 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5664 && i
.op
[x
].regs
->reg_num
> 3)
5666 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5667 i
.rex_encoding
= false;
5676 add_prefix (REX_OPCODE
| i
.rex
);
5678 insert_lfence_before ();
5680 /* We are ready to output the insn. */
5683 insert_lfence_after ();
5685 last_insn
.seg
= now_seg
;
5687 if (i
.tm
.opcode_modifier
.isprefix
)
5689 last_insn
.kind
= last_insn_prefix
;
5690 last_insn
.name
= insn_name (&i
.tm
);
5691 last_insn
.file
= as_where (&last_insn
.line
);
5694 last_insn
.kind
= last_insn_other
;
5697 /* The Q suffix is generally valid only in 64-bit mode, with very few
5698 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5699 and fisttp only one of their two templates is matched below: That's
5700 sufficient since other relevant attributes are the same between both
5701 respective templates. */
5702 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5704 return flag_code
== CODE_64BIT
5705 || (t
->opcode_space
== SPACE_BASE
5706 && t
->base_opcode
== 0xdf
5707 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5708 || t
->mnem_off
== MN_cmpxchg8b
;
5712 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5714 const char *l
= line
, *token_start
= l
;
5716 bool pass1
= !current_templates
;
5718 const insn_template
*t
;
5724 /* Pseudo-prefixes start with an opening figure brace. */
5725 if ((*mnem_p
= *l
) == '{')
5730 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5735 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5738 as_bad (_("no such instruction: `%s'"), token_start
);
5743 /* Pseudo-prefixes end with a closing figure brace. */
5744 if (*mnemonic
== '{' && *l
== '}')
5747 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5751 /* Point l at the closing brace if there's no other separator. */
5752 if (*l
!= END_OF_INSN
&& !is_space_char (*l
)
5753 && *l
!= PREFIX_SEPARATOR
)
5756 else if (!is_space_char (*l
)
5757 && *l
!= END_OF_INSN
5759 || (*l
!= PREFIX_SEPARATOR
&& *l
!= ',')))
5763 as_bad (_("invalid character %s in mnemonic"),
5764 output_invalid (*l
));
5767 if (token_start
== l
)
5769 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5770 as_bad (_("expecting prefix; got nothing"));
5772 as_bad (_("expecting mnemonic; got nothing"));
5776 /* Look up instruction (or prefix) via hash table. */
5777 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5779 if (*l
!= END_OF_INSN
5780 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5781 && current_templates
5782 && current_templates
->start
->opcode_modifier
.isprefix
)
5784 if (!cpu_flags_check_cpu64 (current_templates
->start
))
5786 as_bad ((flag_code
!= CODE_64BIT
5787 ? _("`%s' is only supported in 64-bit mode")
5788 : _("`%s' is not supported in 64-bit mode")),
5789 insn_name (current_templates
->start
));
5792 /* If we are in 16-bit mode, do not allow addr16 or data16.
5793 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5794 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5795 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5796 && flag_code
!= CODE_64BIT
5797 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5798 ^ (flag_code
== CODE_16BIT
)))
5800 as_bad (_("redundant %s prefix"),
5801 insn_name (current_templates
->start
));
5805 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5807 /* Handle pseudo prefixes. */
5808 switch (current_templates
->start
->extension_opcode
)
5812 i
.disp_encoding
= disp_encoding_8bit
;
5816 i
.disp_encoding
= disp_encoding_16bit
;
5820 i
.disp_encoding
= disp_encoding_32bit
;
5824 i
.dir_encoding
= dir_encoding_load
;
5828 i
.dir_encoding
= dir_encoding_store
;
5832 i
.vec_encoding
= vex_encoding_vex
;
5836 i
.vec_encoding
= vex_encoding_vex3
;
5840 i
.vec_encoding
= vex_encoding_evex
;
5844 i
.rex_encoding
= true;
5846 case Prefix_NoOptimize
:
5848 i
.no_optimize
= true;
5856 /* Add prefix, checking for repeated prefixes. */
5857 switch (add_prefix (current_templates
->start
->base_opcode
))
5862 if (is_cpu (current_templates
->start
, CpuIBT
))
5863 i
.notrack_prefix
= insn_name (current_templates
->start
);
5866 if (is_cpu (current_templates
->start
, CpuHLE
))
5867 i
.hle_prefix
= insn_name (current_templates
->start
);
5868 else if (is_cpu (current_templates
->start
, CpuMPX
))
5869 i
.bnd_prefix
= insn_name (current_templates
->start
);
5871 i
.rep_prefix
= insn_name (current_templates
->start
);
5877 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5887 if (!current_templates
)
5889 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5890 Check if we should swap operand or force 32bit displacement in
5892 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5893 i
.dir_encoding
= dir_encoding_swap
;
5894 else if (mnem_p
- 3 == dot_p
5897 i
.disp_encoding
= disp_encoding_8bit
;
5898 else if (mnem_p
- 4 == dot_p
5902 i
.disp_encoding
= disp_encoding_32bit
;
5907 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5910 if (!current_templates
|| !pass1
)
5912 current_templates
= NULL
;
5915 if (mnem_p
> mnemonic
)
5917 /* See if we can get a match by trimming off a suffix. */
5920 case WORD_MNEM_SUFFIX
:
5921 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5922 i
.suffix
= SHORT_MNEM_SUFFIX
;
5925 case BYTE_MNEM_SUFFIX
:
5926 case QWORD_MNEM_SUFFIX
:
5927 i
.suffix
= mnem_p
[-1];
5930 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5932 case SHORT_MNEM_SUFFIX
:
5933 case LONG_MNEM_SUFFIX
:
5936 i
.suffix
= mnem_p
[-1];
5939 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5947 if (intel_float_operand (mnemonic
) == 1)
5948 i
.suffix
= SHORT_MNEM_SUFFIX
;
5950 i
.suffix
= LONG_MNEM_SUFFIX
;
5953 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5955 /* For compatibility reasons accept MOVSD and CMPSD without
5956 operands even in AT&T mode. */
5957 else if (*l
== END_OF_INSN
5958 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5962 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5963 if (current_templates
!= NULL
5965 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5966 && current_templates
->start
->opcode_space
5968 && mnem_p
[-2] == 's')
5970 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5971 mnemonic
, mnemonic
);
5972 i
.suffix
= LONG_MNEM_SUFFIX
;
5976 current_templates
= NULL
;
5984 if (!current_templates
)
5987 as_bad (_("no such instruction: `%s'"), token_start
);
5992 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5993 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5995 /* Check for a branch hint. We allow ",pt" and ",pn" for
5996 predict taken and predict not taken respectively.
5997 I'm not sure that branch hints actually do anything on loop
5998 and jcxz insns (JumpByte) for current Pentium4 chips. They
5999 may work in the future and it doesn't hurt to accept them
6001 if (l
[0] == ',' && l
[1] == 'p')
6005 if (!add_prefix (DS_PREFIX_OPCODE
))
6009 else if (l
[2] == 'n')
6011 if (!add_prefix (CS_PREFIX_OPCODE
))
6017 /* Any other comma loses. */
6020 as_bad (_("invalid character %s in mnemonic"),
6021 output_invalid (*l
));
6025 /* Check if instruction is supported on specified architecture. */
6027 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
6029 supported
|= cpu_flags_match (t
);
6031 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
6032 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
6034 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
6040 if (supported
& CPU_FLAGS_64BIT_MATCH
)
6041 i
.error
= unsupported_on_arch
;
6043 i
.error
= unsupported_64bit
;
6050 parse_operands (char *l
, const char *mnemonic
)
6054 /* 1 if operand is pending after ','. */
6055 unsigned int expecting_operand
= 0;
6057 while (*l
!= END_OF_INSN
)
6059 /* Non-zero if operand parens not balanced. */
6060 unsigned int paren_not_balanced
= 0;
6061 /* True if inside double quotes. */
6062 bool in_quotes
= false;
6064 /* Skip optional white space before operand. */
6065 if (is_space_char (*l
))
6067 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
6069 as_bad (_("invalid character %s before operand %d"),
6070 output_invalid (*l
),
6074 token_start
= l
; /* After white space. */
6075 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
6077 if (*l
== END_OF_INSN
)
6081 as_bad (_("unbalanced double quotes in operand %d."),
6085 if (paren_not_balanced
)
6087 know (!intel_syntax
);
6088 as_bad (_("unbalanced parenthesis in operand %d."),
6093 break; /* we are done */
6095 else if (*l
== '\\' && l
[1] == '"')
6098 in_quotes
= !in_quotes
;
6099 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
6101 as_bad (_("invalid character %s in operand %d"),
6102 output_invalid (*l
),
6106 if (!intel_syntax
&& !in_quotes
)
6109 ++paren_not_balanced
;
6111 --paren_not_balanced
;
6115 if (l
!= token_start
)
6116 { /* Yes, we've read in another operand. */
6117 unsigned int operand_ok
;
6118 this_operand
= i
.operands
++;
6119 if (i
.operands
> MAX_OPERANDS
)
6121 as_bad (_("spurious operands; (%d operands/instruction max)"),
6125 i
.types
[this_operand
].bitfield
.unspecified
= 1;
6126 /* Now parse operand adding info to 'i' as we go along. */
6127 END_STRING_AND_SAVE (l
);
6129 if (i
.mem_operands
> 1)
6131 as_bad (_("too many memory references for `%s'"),
6138 i386_intel_operand (token_start
,
6139 intel_float_operand (mnemonic
));
6141 operand_ok
= i386_att_operand (token_start
);
6143 RESTORE_END_STRING (l
);
6149 if (expecting_operand
)
6151 expecting_operand_after_comma
:
6152 as_bad (_("expecting operand after ','; got nothing"));
6157 as_bad (_("expecting operand before ','; got nothing"));
6162 /* Now *l must be either ',' or END_OF_INSN. */
6165 if (*++l
== END_OF_INSN
)
6167 /* Just skip it, if it's \n complain. */
6168 goto expecting_operand_after_comma
;
6170 expecting_operand
= 1;
6177 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
6179 union i386_op temp_op
;
6180 i386_operand_type temp_type
;
6181 unsigned int temp_flags
;
6182 enum bfd_reloc_code_real temp_reloc
;
6184 temp_type
= i
.types
[xchg2
];
6185 i
.types
[xchg2
] = i
.types
[xchg1
];
6186 i
.types
[xchg1
] = temp_type
;
6188 temp_flags
= i
.flags
[xchg2
];
6189 i
.flags
[xchg2
] = i
.flags
[xchg1
];
6190 i
.flags
[xchg1
] = temp_flags
;
6192 temp_op
= i
.op
[xchg2
];
6193 i
.op
[xchg2
] = i
.op
[xchg1
];
6194 i
.op
[xchg1
] = temp_op
;
6196 temp_reloc
= i
.reloc
[xchg2
];
6197 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
6198 i
.reloc
[xchg1
] = temp_reloc
;
6200 temp_flags
= i
.imm_bits
[xchg2
];
6201 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
6202 i
.imm_bits
[xchg1
] = temp_flags
;
6206 if (i
.mask
.operand
== xchg1
)
6207 i
.mask
.operand
= xchg2
;
6208 else if (i
.mask
.operand
== xchg2
)
6209 i
.mask
.operand
= xchg1
;
6211 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6213 if (i
.broadcast
.operand
== xchg1
)
6214 i
.broadcast
.operand
= xchg2
;
6215 else if (i
.broadcast
.operand
== xchg2
)
6216 i
.broadcast
.operand
= xchg1
;
6221 swap_operands (void)
6227 swap_2_operands (1, i
.operands
- 2);
6231 swap_2_operands (0, i
.operands
- 1);
6237 if (i
.mem_operands
== 2)
6239 const reg_entry
*temp_seg
;
6240 temp_seg
= i
.seg
[0];
6241 i
.seg
[0] = i
.seg
[1];
6242 i
.seg
[1] = temp_seg
;
6246 /* Try to ensure constant immediates are represented in the smallest
6251 char guess_suffix
= 0;
6255 guess_suffix
= i
.suffix
;
6256 else if (i
.reg_operands
)
6258 /* Figure out a suffix from the last register operand specified.
6259 We can't do this properly yet, i.e. excluding special register
6260 instances, but the following works for instructions with
6261 immediates. In any case, we can't set i.suffix yet. */
6262 for (op
= i
.operands
; --op
>= 0;)
6263 if (i
.types
[op
].bitfield
.class != Reg
)
6265 else if (i
.types
[op
].bitfield
.byte
)
6267 guess_suffix
= BYTE_MNEM_SUFFIX
;
6270 else if (i
.types
[op
].bitfield
.word
)
6272 guess_suffix
= WORD_MNEM_SUFFIX
;
6275 else if (i
.types
[op
].bitfield
.dword
)
6277 guess_suffix
= LONG_MNEM_SUFFIX
;
6280 else if (i
.types
[op
].bitfield
.qword
)
6282 guess_suffix
= QWORD_MNEM_SUFFIX
;
6286 else if ((flag_code
== CODE_16BIT
)
6287 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
6288 guess_suffix
= WORD_MNEM_SUFFIX
;
6289 else if (flag_code
!= CODE_64BIT
6290 || (!(i
.prefix
[REX_PREFIX
] & REX_W
)
6291 /* A more generic (but also more involved) way of dealing
6292 with the special case(s) would be to go look for
6293 DefaultSize attributes on any of the templates. */
6294 && current_templates
->start
->mnem_off
!= MN_push
))
6295 guess_suffix
= LONG_MNEM_SUFFIX
;
6297 for (op
= i
.operands
; --op
>= 0;)
6298 if (operand_type_check (i
.types
[op
], imm
))
6300 switch (i
.op
[op
].imms
->X_op
)
6303 /* If a suffix is given, this operand may be shortened. */
6304 switch (guess_suffix
)
6306 case LONG_MNEM_SUFFIX
:
6307 i
.types
[op
].bitfield
.imm32
= 1;
6308 i
.types
[op
].bitfield
.imm64
= 1;
6310 case WORD_MNEM_SUFFIX
:
6311 i
.types
[op
].bitfield
.imm16
= 1;
6312 i
.types
[op
].bitfield
.imm32
= 1;
6313 i
.types
[op
].bitfield
.imm32s
= 1;
6314 i
.types
[op
].bitfield
.imm64
= 1;
6316 case BYTE_MNEM_SUFFIX
:
6317 i
.types
[op
].bitfield
.imm8
= 1;
6318 i
.types
[op
].bitfield
.imm8s
= 1;
6319 i
.types
[op
].bitfield
.imm16
= 1;
6320 i
.types
[op
].bitfield
.imm32
= 1;
6321 i
.types
[op
].bitfield
.imm32s
= 1;
6322 i
.types
[op
].bitfield
.imm64
= 1;
6326 /* If this operand is at most 16 bits, convert it
6327 to a signed 16 bit number before trying to see
6328 whether it will fit in an even smaller size.
6329 This allows a 16-bit operand such as $0xffe0 to
6330 be recognised as within Imm8S range. */
6331 if ((i
.types
[op
].bitfield
.imm16
)
6332 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6334 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6335 ^ 0x8000) - 0x8000);
6338 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6339 if ((i
.types
[op
].bitfield
.imm32
)
6340 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6342 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6343 ^ ((offsetT
) 1 << 31))
6344 - ((offsetT
) 1 << 31));
6348 = operand_type_or (i
.types
[op
],
6349 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6351 /* We must avoid matching of Imm32 templates when 64bit
6352 only immediate is available. */
6353 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6354 i
.types
[op
].bitfield
.imm32
= 0;
6361 /* Symbols and expressions. */
6363 /* Convert symbolic operand to proper sizes for matching, but don't
6364 prevent matching a set of insns that only supports sizes other
6365 than those matching the insn suffix. */
6367 i386_operand_type mask
, allowed
;
6368 const insn_template
*t
= current_templates
->start
;
6370 operand_type_set (&mask
, 0);
6371 switch (guess_suffix
)
6373 case QWORD_MNEM_SUFFIX
:
6374 mask
.bitfield
.imm64
= 1;
6375 mask
.bitfield
.imm32s
= 1;
6377 case LONG_MNEM_SUFFIX
:
6378 mask
.bitfield
.imm32
= 1;
6380 case WORD_MNEM_SUFFIX
:
6381 mask
.bitfield
.imm16
= 1;
6383 case BYTE_MNEM_SUFFIX
:
6384 mask
.bitfield
.imm8
= 1;
6390 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6391 while (++t
< current_templates
->end
)
6393 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6394 allowed
= operand_type_and (allowed
, mask
);
6397 if (!operand_type_all_zero (&allowed
))
6398 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6405 /* Try to use the smallest displacement type too. */
6407 optimize_disp (const insn_template
*t
)
6411 if (!want_disp32 (t
)
6412 && (!t
->opcode_modifier
.jump
6413 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6415 for (op
= 0; op
< i
.operands
; ++op
)
6417 const expressionS
*exp
= i
.op
[op
].disps
;
6419 if (!operand_type_check (i
.types
[op
], disp
))
6422 if (exp
->X_op
!= O_constant
)
6425 /* Since displacement is signed extended to 64bit, don't allow
6426 disp32 if it is out of range. */
6427 if (fits_in_signed_long (exp
->X_add_number
))
6430 i
.types
[op
].bitfield
.disp32
= 0;
6431 if (i
.types
[op
].bitfield
.baseindex
)
6433 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6434 (uint64_t) exp
->X_add_number
);
6440 /* Don't optimize displacement for movabs since it only takes 64bit
6442 if (i
.disp_encoding
> disp_encoding_8bit
6443 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6446 for (op
= i
.operands
; op
-- > 0;)
6447 if (operand_type_check (i
.types
[op
], disp
))
6449 if (i
.op
[op
].disps
->X_op
== O_constant
)
6451 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6453 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6455 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6456 i
.op
[op
].disps
= NULL
;
6461 if (i
.types
[op
].bitfield
.disp16
6462 && fits_in_unsigned_word (op_disp
))
6464 /* If this operand is at most 16 bits, convert
6465 to a signed 16 bit number and don't use 64bit
6467 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6468 i
.types
[op
].bitfield
.disp64
= 0;
6472 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6473 if ((flag_code
!= CODE_64BIT
6474 ? i
.types
[op
].bitfield
.disp32
6476 && (!t
->opcode_modifier
.jump
6477 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6478 && fits_in_unsigned_long (op_disp
))
6480 /* If this operand is at most 32 bits, convert
6481 to a signed 32 bit number and don't use 64bit
6483 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6484 i
.types
[op
].bitfield
.disp64
= 0;
6485 i
.types
[op
].bitfield
.disp32
= 1;
6488 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6490 i
.types
[op
].bitfield
.disp64
= 0;
6491 i
.types
[op
].bitfield
.disp32
= 1;
6494 if ((i
.types
[op
].bitfield
.disp32
6495 || i
.types
[op
].bitfield
.disp16
)
6496 && fits_in_disp8 (op_disp
))
6497 i
.types
[op
].bitfield
.disp8
= 1;
6499 i
.op
[op
].disps
->X_add_number
= op_disp
;
6501 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6502 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6504 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6505 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6506 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6509 /* We only support 64bit displacement on constants. */
6510 i
.types
[op
].bitfield
.disp64
= 0;
6516 /* Return 1 if there is a match in broadcast bytes between operand
6517 GIVEN and instruction template T. */
6520 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6522 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6523 && i
.types
[given
].bitfield
.byte
)
6524 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6525 && i
.types
[given
].bitfield
.word
)
6526 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6527 && i
.types
[given
].bitfield
.dword
)
6528 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6529 && i
.types
[given
].bitfield
.qword
));
6532 /* Check if operands are valid for the instruction. */
6535 check_VecOperands (const insn_template
*t
)
6540 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6541 any one operand are implicity requiring AVX512VL support if the actual
6542 operand size is YMMword or XMMword. Since this function runs after
6543 template matching, there's no need to check for YMMword/XMMword in
6545 cpu
= cpu_flags_and (cpu_flags_from_attr (t
->cpu
), avx512
);
6546 if (!cpu_flags_all_zero (&cpu
)
6547 && !is_cpu (t
, CpuAVX512VL
)
6548 && !cpu_arch_flags
.bitfield
.cpuavx512vl
6549 && (!t
->opcode_modifier
.vex
|| need_evex_encoding ()))
6551 for (op
= 0; op
< t
->operands
; ++op
)
6553 if (t
->operand_types
[op
].bitfield
.zmmword
6554 && (i
.types
[op
].bitfield
.ymmword
6555 || i
.types
[op
].bitfield
.xmmword
))
6557 i
.error
= unsupported
;
6563 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6564 requiring AVX2 support if the actual operand size is YMMword. */
6565 if (is_cpu (t
, CpuAVX
) && is_cpu (t
, CpuAVX2
)
6566 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6568 for (op
= 0; op
< t
->operands
; ++op
)
6570 if (t
->operand_types
[op
].bitfield
.xmmword
6571 && i
.types
[op
].bitfield
.ymmword
)
6573 i
.error
= unsupported
;
6579 /* Without VSIB byte, we can't have a vector register for index. */
6580 if (!t
->opcode_modifier
.sib
6582 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6583 || i
.index_reg
->reg_type
.bitfield
.ymmword
6584 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6586 i
.error
= unsupported_vector_index_register
;
6590 /* Check if default mask is allowed. */
6591 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6592 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6594 i
.error
= no_default_mask
;
6598 /* For VSIB byte, we need a vector register for index, and all vector
6599 registers must be distinct. */
6600 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6603 || !((t
->opcode_modifier
.sib
== VECSIB128
6604 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6605 || (t
->opcode_modifier
.sib
== VECSIB256
6606 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6607 || (t
->opcode_modifier
.sib
== VECSIB512
6608 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6610 i
.error
= invalid_vsib_address
;
6614 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6615 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6617 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6618 gas_assert (i
.types
[0].bitfield
.xmmword
6619 || i
.types
[0].bitfield
.ymmword
);
6620 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6621 gas_assert (i
.types
[2].bitfield
.xmmword
6622 || i
.types
[2].bitfield
.ymmword
);
6623 if (operand_check
== check_none
)
6625 if (register_number (i
.op
[0].regs
)
6626 != register_number (i
.index_reg
)
6627 && register_number (i
.op
[2].regs
)
6628 != register_number (i
.index_reg
)
6629 && register_number (i
.op
[0].regs
)
6630 != register_number (i
.op
[2].regs
))
6632 if (operand_check
== check_error
)
6634 i
.error
= invalid_vector_register_set
;
6637 as_warn (_("mask, index, and destination registers should be distinct"));
6639 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6641 if (i
.types
[1].bitfield
.class == RegSIMD
6642 && (i
.types
[1].bitfield
.xmmword
6643 || i
.types
[1].bitfield
.ymmword
6644 || i
.types
[1].bitfield
.zmmword
)
6645 && (register_number (i
.op
[1].regs
)
6646 == register_number (i
.index_reg
)))
6648 if (operand_check
== check_error
)
6650 i
.error
= invalid_vector_register_set
;
6653 if (operand_check
!= check_none
)
6654 as_warn (_("index and destination registers should be distinct"));
6659 /* For AMX instructions with 3 TMM register operands, all operands
6660 must be distinct. */
6661 if (i
.reg_operands
== 3
6662 && t
->operand_types
[0].bitfield
.tmmword
6663 && (i
.op
[0].regs
== i
.op
[1].regs
6664 || i
.op
[0].regs
== i
.op
[2].regs
6665 || i
.op
[1].regs
== i
.op
[2].regs
))
6667 i
.error
= invalid_tmm_register_set
;
6671 /* For some special instructions require that destination must be distinct
6672 from source registers. */
6673 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6675 unsigned int dest_reg
= i
.operands
- 1;
6677 know (i
.operands
>= 3);
6679 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6680 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6681 || (i
.reg_operands
> 2
6682 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6684 i
.error
= invalid_dest_and_src_register_set
;
6689 /* Check if broadcast is supported by the instruction and is applied
6690 to the memory operand. */
6691 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6693 i386_operand_type type
, overlap
;
6695 /* Check if specified broadcast is supported in this instruction,
6696 and its broadcast bytes match the memory operand. */
6697 op
= i
.broadcast
.operand
;
6698 if (!t
->opcode_modifier
.broadcast
6699 || !(i
.flags
[op
] & Operand_Mem
)
6700 || (!i
.types
[op
].bitfield
.unspecified
6701 && !match_broadcast_size (t
, op
)))
6704 i
.error
= unsupported_broadcast
;
6708 operand_type_set (&type
, 0);
6709 switch (get_broadcast_bytes (t
, false))
6712 type
.bitfield
.word
= 1;
6715 type
.bitfield
.dword
= 1;
6718 type
.bitfield
.qword
= 1;
6721 type
.bitfield
.xmmword
= 1;
6724 if (vector_size
< VSZ256
)
6726 type
.bitfield
.ymmword
= 1;
6729 if (vector_size
< VSZ512
)
6731 type
.bitfield
.zmmword
= 1;
6737 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6738 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6739 && t
->operand_types
[op
].bitfield
.byte
6740 + t
->operand_types
[op
].bitfield
.word
6741 + t
->operand_types
[op
].bitfield
.dword
6742 + t
->operand_types
[op
].bitfield
.qword
> 1)
6744 overlap
.bitfield
.xmmword
= 0;
6745 overlap
.bitfield
.ymmword
= 0;
6746 overlap
.bitfield
.zmmword
= 0;
6748 if (operand_type_all_zero (&overlap
))
6751 if (t
->opcode_modifier
.checkoperandsize
)
6755 type
.bitfield
.baseindex
= 1;
6756 for (j
= 0; j
< i
.operands
; ++j
)
6759 && !operand_type_register_match(i
.types
[j
],
6760 t
->operand_types
[j
],
6762 t
->operand_types
[op
]))
6767 /* If broadcast is supported in this instruction, we need to check if
6768 operand of one-element size isn't specified without broadcast. */
6769 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6771 /* Find memory operand. */
6772 for (op
= 0; op
< i
.operands
; op
++)
6773 if (i
.flags
[op
] & Operand_Mem
)
6775 gas_assert (op
< i
.operands
);
6776 /* Check size of the memory operand. */
6777 if (match_broadcast_size (t
, op
))
6779 i
.error
= broadcast_needed
;
6784 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6786 /* Check if requested masking is supported. */
6789 if (!t
->opcode_modifier
.masking
)
6791 i
.error
= unsupported_masking
;
6795 /* Common rules for masking:
6796 - mask register destinations permit only zeroing-masking, without
6797 that actually being expressed by a {z} operand suffix or EVEX.z,
6798 - memory destinations allow only merging-masking,
6799 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
6802 && (t
->operand_types
[t
->operands
- 1].bitfield
.class == RegMask
6803 || (i
.flags
[t
->operands
- 1] & Operand_Mem
)
6804 || t
->opcode_modifier
.sib
))
6806 i
.error
= unsupported_masking
;
6811 /* Check if masking is applied to dest operand. */
6812 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6814 i
.error
= mask_not_on_destination
;
6819 if (i
.rounding
.type
!= rc_none
)
6821 if (!t
->opcode_modifier
.sae
6822 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6825 i
.error
= unsupported_rc_sae
;
6829 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6831 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6833 for (op
= 0; op
< t
->operands
; ++op
)
6834 if (i
.types
[op
].bitfield
.zmmword
)
6836 if (op
>= t
->operands
)
6838 i
.error
= operand_size_mismatch
;
6844 /* Check the special Imm4 cases; must be the first operand. */
6845 if (is_cpu (t
, CpuXOP
) && t
->operands
== 5)
6847 if (i
.op
[0].imms
->X_op
!= O_constant
6848 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6854 /* Turn off Imm<N> so that update_imm won't complain. */
6855 operand_type_set (&i
.types
[0], 0);
6858 /* Check vector Disp8 operand. */
6859 if (t
->opcode_modifier
.disp8memshift
6860 && (!t
->opcode_modifier
.vex
6861 || need_evex_encoding ())
6862 && i
.disp_encoding
<= disp_encoding_8bit
)
6864 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6865 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6866 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6867 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6870 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6873 for (op
= 0; op
< i
.operands
; op
++)
6874 if (i
.flags
[op
] & Operand_Mem
)
6876 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6877 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6878 else if (t
->operand_types
[op
].bitfield
.xmmword
6879 + t
->operand_types
[op
].bitfield
.ymmword
6880 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6881 type
= &t
->operand_types
[op
];
6882 else if (!i
.types
[op
].bitfield
.unspecified
)
6883 type
= &i
.types
[op
];
6884 else /* Ambiguities get resolved elsewhere. */
6885 fallback
= &t
->operand_types
[op
];
6887 else if (i
.types
[op
].bitfield
.class == RegSIMD
6888 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6890 if (i
.types
[op
].bitfield
.zmmword
)
6892 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6894 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6898 if (!type
&& !i
.memshift
)
6902 if (type
->bitfield
.zmmword
)
6904 else if (type
->bitfield
.ymmword
)
6906 else if (type
->bitfield
.xmmword
)
6910 /* For the check in fits_in_disp8(). */
6911 if (i
.memshift
== 0)
6915 for (op
= 0; op
< i
.operands
; op
++)
6916 if (operand_type_check (i
.types
[op
], disp
)
6917 && i
.op
[op
].disps
->X_op
== O_constant
)
6919 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6921 i
.types
[op
].bitfield
.disp8
= 1;
6924 i
.types
[op
].bitfield
.disp8
= 0;
6933 /* Check if encoding requirements are met by the instruction. */
6936 VEX_check_encoding (const insn_template
*t
)
6938 if (i
.vec_encoding
== vex_encoding_error
)
6940 i
.error
= unsupported
;
6944 /* Vector size restrictions. */
6945 if ((vector_size
< VSZ512
6946 && (t
->opcode_modifier
.evex
== EVEX512
6947 || t
->opcode_modifier
.vsz
>= VSZ512
))
6948 || (vector_size
< VSZ256
6949 && (t
->opcode_modifier
.evex
== EVEX256
6950 || t
->opcode_modifier
.vex
== VEX256
6951 || t
->opcode_modifier
.vsz
>= VSZ256
)))
6953 i
.error
= unsupported
;
6957 if (i
.vec_encoding
== vex_encoding_evex
6958 || i
.vec_encoding
== vex_encoding_evex512
)
6960 /* This instruction must be encoded with EVEX prefix. */
6961 if (!is_evex_encoding (t
))
6963 i
.error
= unsupported
;
6969 if (!t
->opcode_modifier
.vex
)
6971 /* This instruction template doesn't have VEX prefix. */
6972 if (i
.vec_encoding
!= vex_encoding_default
)
6974 i
.error
= unsupported
;
6983 /* Helper function for the progress() macro in match_template(). */
6984 static INLINE
enum i386_error
progress (enum i386_error
new,
6985 enum i386_error last
,
6986 unsigned int line
, unsigned int *line_p
)
6988 if (line
<= *line_p
)
6994 static const insn_template
*
6995 match_template (char mnem_suffix
)
6997 /* Points to template once we've found it. */
6998 const insn_template
*t
;
6999 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
7000 i386_operand_type overlap4
;
7001 unsigned int found_reverse_match
;
7002 i386_operand_type operand_types
[MAX_OPERANDS
];
7003 int addr_prefix_disp
;
7004 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
7005 enum i386_error specific_error
= number_of_operands_mismatch
;
7006 #define progress(err) progress (err, specific_error, __LINE__, &errline)
7008 #if MAX_OPERANDS != 5
7009 # error "MAX_OPERANDS must be 5."
7012 found_reverse_match
= 0;
7013 addr_prefix_disp
= -1;
7015 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
7017 addr_prefix_disp
= -1;
7018 found_reverse_match
= 0;
7020 /* Must have right number of operands. */
7021 if (i
.operands
!= t
->operands
)
7024 /* Check processor support. */
7025 specific_error
= progress (unsupported
);
7026 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
7029 /* Check AT&T mnemonic. */
7030 specific_error
= progress (unsupported_with_intel_mnemonic
);
7031 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
7034 /* Check AT&T/Intel syntax. */
7035 specific_error
= progress (unsupported_syntax
);
7036 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
7037 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
7040 /* Check Intel64/AMD64 ISA. */
7044 /* Default: Don't accept Intel64. */
7045 if (t
->opcode_modifier
.isa64
== INTEL64
)
7049 /* -mamd64: Don't accept Intel64 and Intel64 only. */
7050 if (t
->opcode_modifier
.isa64
>= INTEL64
)
7054 /* -mintel64: Don't accept AMD64. */
7055 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
7060 /* Check the suffix. */
7061 specific_error
= progress (invalid_instruction_suffix
);
7062 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
7063 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
7064 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
7065 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
7066 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
7069 specific_error
= progress (operand_size_mismatch
);
7070 size_match
= operand_size_match (t
);
7074 /* This is intentionally not
7076 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
7078 as the case of a missing * on the operand is accepted (perhaps with
7079 a warning, issued further down). */
7080 specific_error
= progress (operand_type_mismatch
);
7081 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
7084 /* In Intel syntax, normally we can check for memory operand size when
7085 there is no mnemonic suffix. But jmp and call have 2 different
7086 encodings with Dword memory operand size. Skip the "near" one
7087 (permitting a register operand) when "far" was requested. */
7089 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
7090 && t
->operand_types
[0].bitfield
.class == Reg
)
7093 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7094 operand_types
[j
] = t
->operand_types
[j
];
7096 /* In general, don't allow 32-bit operands on pre-386. */
7097 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
7098 : operand_size_mismatch
);
7099 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
7100 if (i
.suffix
== LONG_MNEM_SUFFIX
7101 && !cpu_arch_flags
.bitfield
.cpui386
7103 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
7104 && !intel_float_operand (insn_name (t
)))
7105 : intel_float_operand (insn_name (t
)) != 2)
7106 && (t
->operands
== i
.imm_operands
7107 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
7108 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
7109 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
7110 || (operand_types
[j
].bitfield
.class != RegMMX
7111 && operand_types
[j
].bitfield
.class != RegSIMD
7112 && operand_types
[j
].bitfield
.class != RegMask
))
7113 && !t
->opcode_modifier
.sib
)
7116 /* Do not verify operands when there are none. */
7119 if (VEX_check_encoding (t
))
7121 specific_error
= progress (i
.error
);
7125 /* We've found a match; break out of loop. */
7129 if (!t
->opcode_modifier
.jump
7130 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
7132 /* There should be only one Disp operand. */
7133 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7134 if (operand_type_check (operand_types
[j
], disp
))
7136 if (j
< MAX_OPERANDS
)
7138 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7140 addr_prefix_disp
= j
;
7142 /* Address size prefix will turn Disp64 operand into Disp32 and
7143 Disp32/Disp16 one into Disp16/Disp32 respectively. */
7147 override
= !override
;
7150 if (operand_types
[j
].bitfield
.disp32
7151 && operand_types
[j
].bitfield
.disp16
)
7153 operand_types
[j
].bitfield
.disp16
= override
;
7154 operand_types
[j
].bitfield
.disp32
= !override
;
7156 gas_assert (!operand_types
[j
].bitfield
.disp64
);
7160 if (operand_types
[j
].bitfield
.disp64
)
7162 gas_assert (!operand_types
[j
].bitfield
.disp32
);
7163 operand_types
[j
].bitfield
.disp32
= override
;
7164 operand_types
[j
].bitfield
.disp64
= !override
;
7166 operand_types
[j
].bitfield
.disp16
= 0;
7172 /* We check register size if needed. */
7173 if (t
->opcode_modifier
.checkoperandsize
)
7175 check_register
= (1 << t
->operands
) - 1;
7176 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
7177 check_register
&= ~(1 << i
.broadcast
.operand
);
7182 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
7183 switch (t
->operands
)
7186 if (!operand_type_match (overlap0
, i
.types
[0]))
7189 /* Allow the ModR/M encoding to be requested by using the {load} or
7190 {store} pseudo prefix on an applicable insn. */
7191 if (!t
->opcode_modifier
.modrm
7192 && i
.reg_operands
== 1
7193 && ((i
.dir_encoding
== dir_encoding_load
7194 && t
->mnem_off
!= MN_pop
)
7195 || (i
.dir_encoding
== dir_encoding_store
7196 && t
->mnem_off
!= MN_push
))
7198 && t
->mnem_off
!= MN_bswap
)
7203 /* xchg %eax, %eax is a special case. It is an alias for nop
7204 only in 32bit mode and we can use opcode 0x90. In 64bit
7205 mode, we can't use 0x90 for xchg %eax, %eax since it should
7206 zero-extend %eax to %rax. */
7207 if (t
->base_opcode
== 0x90
7208 && t
->opcode_space
== SPACE_BASE
)
7210 if (flag_code
== CODE_64BIT
7211 && i
.types
[0].bitfield
.instance
== Accum
7212 && i
.types
[0].bitfield
.dword
7213 && i
.types
[1].bitfield
.instance
== Accum
)
7216 /* Allow the ModR/M encoding to be requested by using the
7217 {load} or {store} pseudo prefix. */
7218 if (i
.dir_encoding
== dir_encoding_load
7219 || i
.dir_encoding
== dir_encoding_store
)
7223 if (t
->base_opcode
== MOV_AX_DISP32
7224 && t
->opcode_space
== SPACE_BASE
7225 && t
->mnem_off
!= MN_movabs
)
7227 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
7228 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
7231 /* xrelease mov %eax, <disp> is another special case. It must not
7232 match the accumulator-only encoding of mov. */
7236 /* Allow the ModR/M encoding to be requested by using a suitable
7237 {load} or {store} pseudo prefix. */
7238 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
7239 ? dir_encoding_store
7240 : dir_encoding_load
)
7241 && !i
.types
[0].bitfield
.disp64
7242 && !i
.types
[1].bitfield
.disp64
)
7246 /* Allow the ModR/M encoding to be requested by using the {load} or
7247 {store} pseudo prefix on an applicable insn. */
7248 if (!t
->opcode_modifier
.modrm
7249 && i
.reg_operands
== 1
7250 && i
.imm_operands
== 1
7251 && (i
.dir_encoding
== dir_encoding_load
7252 || i
.dir_encoding
== dir_encoding_store
)
7253 && t
->opcode_space
== SPACE_BASE
)
7255 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
7256 && i
.dir_encoding
== dir_encoding_store
)
7259 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
7260 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
7261 || i
.dir_encoding
== dir_encoding_load
))
7264 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
7265 && i
.dir_encoding
== dir_encoding_load
)
7271 if (!(size_match
& MATCH_STRAIGHT
))
7273 /* Reverse direction of operands if swapping is possible in the first
7274 place (operands need to be symmetric) and
7275 - the load form is requested, and the template is a store form,
7276 - the store form is requested, and the template is a load form,
7277 - the non-default (swapped) form is requested. */
7278 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
7279 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
7280 && !operand_type_all_zero (&overlap1
))
7281 switch (i
.dir_encoding
)
7283 case dir_encoding_load
:
7284 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7285 || t
->opcode_modifier
.regmem
)
7289 case dir_encoding_store
:
7290 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7291 && !t
->opcode_modifier
.regmem
)
7295 case dir_encoding_swap
:
7298 case dir_encoding_default
:
7301 /* If we want store form, we skip the current load. */
7302 if ((i
.dir_encoding
== dir_encoding_store
7303 || i
.dir_encoding
== dir_encoding_swap
)
7304 && i
.mem_operands
== 0
7305 && t
->opcode_modifier
.load
)
7310 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7311 if (!operand_type_match (overlap0
, i
.types
[0])
7312 || !operand_type_match (overlap1
, i
.types
[1])
7313 || ((check_register
& 3) == 3
7314 && !operand_type_register_match (i
.types
[0],
7319 specific_error
= progress (i
.error
);
7321 /* Check if other direction is valid ... */
7322 if (!t
->opcode_modifier
.d
)
7326 if (!(size_match
& MATCH_REVERSE
))
7328 /* Try reversing direction of operands. */
7329 j
= is_cpu (t
, CpuFMA4
)
7330 || is_cpu (t
, CpuXOP
) ? 1 : i
.operands
- 1;
7331 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7332 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7333 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7334 gas_assert (t
->operands
!= 3 || !check_register
);
7335 if (!operand_type_match (overlap0
, i
.types
[0])
7336 || !operand_type_match (overlap1
, i
.types
[j
])
7337 || (t
->operands
== 3
7338 && !operand_type_match (overlap2
, i
.types
[1]))
7340 && !operand_type_register_match (i
.types
[0],
7345 /* Does not match either direction. */
7346 specific_error
= progress (i
.error
);
7349 /* found_reverse_match holds which variant of D
7351 if (!t
->opcode_modifier
.d
)
7352 found_reverse_match
= 0;
7353 else if (operand_types
[0].bitfield
.tbyte
)
7355 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7356 found_reverse_match
= Opcode_FloatD
;
7358 found_reverse_match
= ~0;
7359 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7360 if ((t
->extension_opcode
& 4)
7361 && (intel_syntax
|| intel_mnemonic
))
7362 found_reverse_match
|= Opcode_FloatR
;
7364 else if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
7366 found_reverse_match
= Opcode_VexW
;
7367 goto check_operands_345
;
7369 else if (t
->opcode_space
!= SPACE_BASE
7370 && (t
->opcode_space
!= SPACE_0F
7371 /* MOV to/from CR/DR/TR, as an exception, follow
7372 the base opcode space encoding model. */
7373 || (t
->base_opcode
| 7) != 0x27))
7374 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7375 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7376 else if (!t
->opcode_modifier
.commutative
)
7377 found_reverse_match
= Opcode_D
;
7379 found_reverse_match
= ~0;
7383 /* Found a forward 2 operand match here. */
7385 switch (t
->operands
)
7388 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7389 if (!operand_type_match (overlap4
, i
.types
[4])
7390 || !operand_type_register_match (i
.types
[3],
7395 specific_error
= progress (i
.error
);
7400 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7401 if (!operand_type_match (overlap3
, i
.types
[3])
7402 || ((check_register
& 0xa) == 0xa
7403 && !operand_type_register_match (i
.types
[1],
7407 || ((check_register
& 0xc) == 0xc
7408 && !operand_type_register_match (i
.types
[2],
7413 specific_error
= progress (i
.error
);
7418 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7419 if (!operand_type_match (overlap2
, i
.types
[2])
7420 || ((check_register
& 5) == 5
7421 && !operand_type_register_match (i
.types
[0],
7425 || ((check_register
& 6) == 6
7426 && !operand_type_register_match (i
.types
[1],
7431 specific_error
= progress (i
.error
);
7437 /* Found either forward/reverse 2, 3 or 4 operand match here:
7438 slip through to break. */
7441 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7442 if (VEX_check_encoding (t
))
7444 specific_error
= progress (i
.error
);
7448 /* Check if vector operands are valid. */
7449 if (check_VecOperands (t
))
7451 specific_error
= progress (i
.error
);
7455 /* Check whether to use the shorter VEX encoding for certain insns where
7456 the EVEX enconding comes first in the table. This requires the respective
7457 AVX-* feature to be explicitly enabled. */
7458 if (t
== current_templates
->start
7459 && t
->opcode_modifier
.disp8memshift
7460 && !t
->opcode_modifier
.vex
7461 && !need_evex_encoding ()
7462 && t
+ 1 < current_templates
->end
7463 && t
[1].opcode_modifier
.vex
)
7466 unsigned int memshift
= i
.memshift
;
7469 cpu
= cpu_flags_and (cpu_flags_from_attr (t
[1].cpu
), cpu_arch_isa_flags
);
7470 if (!cpu_flags_all_zero (&cpu
)
7471 && (!i
.types
[0].bitfield
.disp8
7472 || !operand_type_check (i
.types
[0], disp
)
7473 || i
.op
[0].disps
->X_op
!= O_constant
7474 || fits_in_disp8 (i
.op
[0].disps
->X_add_number
)))
7476 specific_error
= progress (internal_error
);
7479 i
.memshift
= memshift
;
7482 /* We've found a match; break out of loop. */
7488 if (t
== current_templates
->end
)
7490 /* We found no match. */
7491 i
.error
= specific_error
;
7495 if (!quiet_warnings
)
7498 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7499 as_warn (_("indirect %s without `*'"), insn_name (t
));
7501 if (t
->opcode_modifier
.isprefix
7502 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7504 /* Warn them that a data or address size prefix doesn't
7505 affect assembly of the next line of code. */
7506 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7510 /* Copy the template we found. */
7511 install_template (t
);
7513 if (addr_prefix_disp
!= -1)
7514 i
.tm
.operand_types
[addr_prefix_disp
]
7515 = operand_types
[addr_prefix_disp
];
7517 switch (found_reverse_match
)
7523 case Opcode_FloatR
| Opcode_FloatD
:
7524 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7525 found_reverse_match
&= Opcode_FloatD
;
7529 /* If we found a reverse match we must alter the opcode direction
7530 bit and clear/flip the regmem modifier one. found_reverse_match
7531 holds bits to change (different for int & float insns). */
7533 i
.tm
.base_opcode
^= found_reverse_match
;
7535 /* Certain SIMD insns have their load forms specified in the opcode
7536 table, and hence we need to _set_ RegMem instead of clearing it.
7537 We need to avoid setting the bit though on insns like KMOVW. */
7538 i
.tm
.opcode_modifier
.regmem
7539 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7540 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7541 && !i
.tm
.opcode_modifier
.regmem
;
7545 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7546 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7550 /* Only the first two register operands need reversing, alongside
7552 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7554 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7555 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7556 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7560 /* This pattern aims to put the unusually placed imm operand to a usual
7561 place. The constraints are currently only adapted to uwrmsr, and may
7562 need further tweaking when new similar instructions become available. */
7563 if (i
.imm_operands
&& i
.imm_operands
< i
.operands
7564 && operand_type_check (operand_types
[i
.operands
- 1], imm
))
7566 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7567 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7568 swap_2_operands(0, i
.operands
- 1);
7577 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7578 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7580 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7582 as_bad (_("`%s' operand %u must use `%ses' segment"),
7584 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7589 /* There's only ever one segment override allowed per instruction.
7590 This instruction possibly has a legal segment override on the
7591 second operand, so copy the segment to where non-string
7592 instructions store it, allowing common code. */
7593 i
.seg
[op
] = i
.seg
[1];
7599 process_suffix (void)
7601 bool is_movx
= false;
7603 /* If matched instruction specifies an explicit instruction mnemonic
7605 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7606 i
.suffix
= WORD_MNEM_SUFFIX
;
7607 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7608 i
.suffix
= LONG_MNEM_SUFFIX
;
7609 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7610 i
.suffix
= QWORD_MNEM_SUFFIX
;
7611 else if (i
.reg_operands
7612 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7613 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7615 unsigned int numop
= i
.operands
;
7618 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7619 && (i
.tm
.base_opcode
| 8) == 0xbe)
7620 || (i
.tm
.opcode_space
== SPACE_BASE
7621 && i
.tm
.base_opcode
== 0x63
7622 && is_cpu (&i
.tm
, Cpu64
));
7624 /* movsx/movzx want only their source operand considered here, for the
7625 ambiguity checking below. The suffix will be replaced afterwards
7626 to represent the destination (register). */
7627 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7630 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7631 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7634 /* If there's no instruction mnemonic suffix we try to invent one
7635 based on GPR operands. */
7638 /* We take i.suffix from the last register operand specified,
7639 Destination register type is more significant than source
7640 register type. crc32 in SSE4.2 prefers source register
7642 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7645 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7646 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7648 if (i
.types
[op
].bitfield
.class != Reg
)
7650 if (i
.types
[op
].bitfield
.byte
)
7651 i
.suffix
= BYTE_MNEM_SUFFIX
;
7652 else if (i
.types
[op
].bitfield
.word
)
7653 i
.suffix
= WORD_MNEM_SUFFIX
;
7654 else if (i
.types
[op
].bitfield
.dword
)
7655 i
.suffix
= LONG_MNEM_SUFFIX
;
7656 else if (i
.types
[op
].bitfield
.qword
)
7657 i
.suffix
= QWORD_MNEM_SUFFIX
;
7663 /* As an exception, movsx/movzx silently default to a byte source
7665 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7666 i
.suffix
= BYTE_MNEM_SUFFIX
;
7668 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7670 if (!check_byte_reg ())
7673 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7675 if (!check_long_reg ())
7678 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7680 if (!check_qword_reg ())
7683 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7685 if (!check_word_reg ())
7688 else if (intel_syntax
7689 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7690 /* Do nothing if the instruction is going to ignore the prefix. */
7695 /* Undo the movsx/movzx change done above. */
7698 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7701 i
.suffix
= stackop_size
;
7702 if (stackop_size
== LONG_MNEM_SUFFIX
)
7704 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7705 .code16gcc directive to support 16-bit mode with
7706 32-bit address. For IRET without a suffix, generate
7707 16-bit IRET (opcode 0xcf) to return from an interrupt
7709 if (i
.tm
.base_opcode
== 0xcf)
7711 i
.suffix
= WORD_MNEM_SUFFIX
;
7712 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7714 /* Warn about changed behavior for segment register push/pop. */
7715 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7716 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7721 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7722 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7723 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7724 || (i
.tm
.opcode_space
== SPACE_0F
7725 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7726 && i
.tm
.extension_opcode
<= 3)))
7731 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7733 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7734 || i
.tm
.opcode_modifier
.no_lsuf
)
7735 i
.suffix
= QWORD_MNEM_SUFFIX
;
7740 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7741 i
.suffix
= LONG_MNEM_SUFFIX
;
7744 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7745 i
.suffix
= WORD_MNEM_SUFFIX
;
7751 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7752 /* Also cover lret/retf/iret in 64-bit mode. */
7753 || (flag_code
== CODE_64BIT
7754 && !i
.tm
.opcode_modifier
.no_lsuf
7755 && !i
.tm
.opcode_modifier
.no_qsuf
))
7756 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7757 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7758 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7759 /* Accept FLDENV et al without suffix. */
7760 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7762 unsigned int suffixes
, evex
= 0;
7764 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7765 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7767 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7769 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7771 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7774 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7775 also suitable for AT&T syntax mode, it was requested that this be
7776 restricted to just Intel syntax. */
7777 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7778 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7782 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7784 if (vector_size
< VSZ512
)
7786 i
.tm
.operand_types
[op
].bitfield
.zmmword
= 0;
7787 if (vector_size
< VSZ256
)
7789 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7790 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7791 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7792 || (!i
.tm
.opcode_modifier
.evex
7793 && is_evex_encoding (&i
.tm
))))
7794 i
.tm
.opcode_modifier
.evex
= EVEX128
;
7796 else if (i
.tm
.operand_types
[op
].bitfield
.ymmword
7797 && !i
.tm
.operand_types
[op
].bitfield
.xmmword
7798 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7799 || (!i
.tm
.opcode_modifier
.evex
7800 && is_evex_encoding (&i
.tm
))))
7801 i
.tm
.opcode_modifier
.evex
= EVEX256
;
7803 else if (is_evex_encoding (&i
.tm
)
7804 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7806 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7807 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7808 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7809 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7810 if (!i
.tm
.opcode_modifier
.evex
7811 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7812 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7815 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7816 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7817 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7820 /* Any properly sized operand disambiguates the insn. */
7821 if (i
.types
[op
].bitfield
.xmmword
7822 || i
.types
[op
].bitfield
.ymmword
7823 || i
.types
[op
].bitfield
.zmmword
)
7825 suffixes
&= ~(7 << 6);
7830 if ((i
.flags
[op
] & Operand_Mem
)
7831 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7833 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7835 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7837 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7839 if (is_evex_encoding (&i
.tm
))
7845 /* Are multiple suffixes / operand sizes allowed? */
7846 if (suffixes
& (suffixes
- 1))
7849 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7850 || operand_check
== check_error
))
7852 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7855 if (operand_check
== check_error
)
7857 as_bad (_("no instruction mnemonic suffix given and "
7858 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7861 if (operand_check
== check_warning
)
7862 as_warn (_("%s; using default for `%s'"),
7864 ? _("ambiguous operand size")
7865 : _("no instruction mnemonic suffix given and "
7866 "no register operands"),
7869 if (i
.tm
.opcode_modifier
.floatmf
)
7870 i
.suffix
= SHORT_MNEM_SUFFIX
;
7872 /* handled below */;
7874 i
.tm
.opcode_modifier
.evex
= evex
;
7875 else if (flag_code
== CODE_16BIT
)
7876 i
.suffix
= WORD_MNEM_SUFFIX
;
7877 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7878 i
.suffix
= LONG_MNEM_SUFFIX
;
7880 i
.suffix
= QWORD_MNEM_SUFFIX
;
7886 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7887 In AT&T syntax, if there is no suffix (warned about above), the default
7888 will be byte extension. */
7889 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7890 i
.tm
.base_opcode
|= 1;
7892 /* For further processing, the suffix should represent the destination
7893 (register). This is already the case when one was used with
7894 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7895 no suffix to begin with. */
7896 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7898 if (i
.types
[1].bitfield
.word
)
7899 i
.suffix
= WORD_MNEM_SUFFIX
;
7900 else if (i
.types
[1].bitfield
.qword
)
7901 i
.suffix
= QWORD_MNEM_SUFFIX
;
7903 i
.suffix
= LONG_MNEM_SUFFIX
;
7905 i
.tm
.opcode_modifier
.w
= 0;
7909 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7910 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7911 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7913 /* Change the opcode based on the operand size given by i.suffix. */
7916 /* Size floating point instruction. */
7917 case LONG_MNEM_SUFFIX
:
7918 if (i
.tm
.opcode_modifier
.floatmf
)
7920 i
.tm
.base_opcode
^= 4;
7924 case WORD_MNEM_SUFFIX
:
7925 case QWORD_MNEM_SUFFIX
:
7926 /* It's not a byte, select word/dword operation. */
7927 if (i
.tm
.opcode_modifier
.w
)
7930 i
.tm
.base_opcode
|= 8;
7932 i
.tm
.base_opcode
|= 1;
7935 case SHORT_MNEM_SUFFIX
:
7936 /* Now select between word & dword operations via the operand
7937 size prefix, except for instructions that will ignore this
7939 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7940 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7941 && !i
.tm
.opcode_modifier
.floatmf
7942 && !is_any_vex_encoding (&i
.tm
)
7943 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7944 || (flag_code
== CODE_64BIT
7945 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7947 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7949 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7950 prefix
= ADDR_PREFIX_OPCODE
;
7952 if (!add_prefix (prefix
))
7956 /* Set mode64 for an operand. */
7957 if (i
.suffix
== QWORD_MNEM_SUFFIX
7958 && flag_code
== CODE_64BIT
7959 && !i
.tm
.opcode_modifier
.norex64
7960 && !i
.tm
.opcode_modifier
.vexw
7961 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7963 && ! (i
.operands
== 2
7964 && i
.tm
.base_opcode
== 0x90
7965 && i
.tm
.opcode_space
== SPACE_BASE
7966 && i
.types
[0].bitfield
.instance
== Accum
7967 && i
.types
[0].bitfield
.qword
7968 && i
.types
[1].bitfield
.instance
== Accum
))
7974 /* Select word/dword/qword operation with explicit data sizing prefix
7975 when there are no suitable register operands. */
7976 if (i
.tm
.opcode_modifier
.w
7977 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7979 || (i
.reg_operands
== 1
7981 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7983 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7984 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7985 || i
.tm
.mnem_off
== MN_crc32
))))
7986 i
.tm
.base_opcode
|= 1;
7990 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7992 gas_assert (!i
.suffix
);
7993 gas_assert (i
.reg_operands
);
7995 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7998 /* The address size override prefix changes the size of the
8000 if (flag_code
== CODE_64BIT
8001 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
8003 as_bad (_("16-bit addressing unavailable for `%s'"),
8008 if ((flag_code
== CODE_32BIT
8009 ? i
.op
[0].regs
->reg_type
.bitfield
.word
8010 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
8011 && !add_prefix (ADDR_PREFIX_OPCODE
))
8016 /* Check invalid register operand when the address size override
8017 prefix changes the size of register operands. */
8019 enum { need_word
, need_dword
, need_qword
} need
;
8021 /* Check the register operand for the address size prefix if
8022 the memory operand has no real registers, like symbol, DISP
8023 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
8024 if (i
.mem_operands
== 1
8025 && i
.reg_operands
== 1
8027 && i
.types
[1].bitfield
.class == Reg
8028 && (flag_code
== CODE_32BIT
8029 ? i
.op
[1].regs
->reg_type
.bitfield
.word
8030 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
8031 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
8032 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8033 || (x86_elf_abi
== X86_64_X32_ABI
8035 && i
.base_reg
->reg_num
== RegIP
8036 && i
.base_reg
->reg_type
.bitfield
.qword
))
8040 && !add_prefix (ADDR_PREFIX_OPCODE
))
8043 if (flag_code
== CODE_32BIT
)
8044 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
8045 else if (i
.prefix
[ADDR_PREFIX
])
8048 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
8050 for (op
= 0; op
< i
.operands
; op
++)
8052 if (i
.types
[op
].bitfield
.class != Reg
)
8058 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
8062 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
8066 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
8071 as_bad (_("invalid register operand size for `%s'"),
8082 check_byte_reg (void)
8086 for (op
= i
.operands
; --op
>= 0;)
8088 /* Skip non-register operands. */
8089 if (i
.types
[op
].bitfield
.class != Reg
)
8092 /* If this is an eight bit register, it's OK. If it's the 16 or
8093 32 bit version of an eight bit register, we will just use the
8094 low portion, and that's OK too. */
8095 if (i
.types
[op
].bitfield
.byte
)
8098 /* I/O port address operands are OK too. */
8099 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
8100 && i
.tm
.operand_types
[op
].bitfield
.word
)
8103 /* crc32 only wants its source operand checked here. */
8104 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
8107 /* Any other register is bad. */
8108 as_bad (_("`%s%s' not allowed with `%s%c'"),
8109 register_prefix
, i
.op
[op
].regs
->reg_name
,
8110 insn_name (&i
.tm
), i
.suffix
);
8117 check_long_reg (void)
8121 for (op
= i
.operands
; --op
>= 0;)
8122 /* Skip non-register operands. */
8123 if (i
.types
[op
].bitfield
.class != Reg
)
8125 /* Reject eight bit registers, except where the template requires
8126 them. (eg. movzb) */
8127 else if (i
.types
[op
].bitfield
.byte
8128 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8129 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8130 && (i
.tm
.operand_types
[op
].bitfield
.word
8131 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8133 as_bad (_("`%s%s' not allowed with `%s%c'"),
8135 i
.op
[op
].regs
->reg_name
,
8140 /* Error if the e prefix on a general reg is missing. */
8141 else if (i
.types
[op
].bitfield
.word
8142 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8143 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8144 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8146 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8147 register_prefix
, i
.op
[op
].regs
->reg_name
,
8151 /* Warn if the r prefix on a general reg is present. */
8152 else if (i
.types
[op
].bitfield
.qword
8153 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8154 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8155 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8157 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8158 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8165 check_qword_reg (void)
8169 for (op
= i
.operands
; --op
>= 0; )
8170 /* Skip non-register operands. */
8171 if (i
.types
[op
].bitfield
.class != Reg
)
8173 /* Reject eight bit registers, except where the template requires
8174 them. (eg. movzb) */
8175 else if (i
.types
[op
].bitfield
.byte
8176 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8177 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8178 && (i
.tm
.operand_types
[op
].bitfield
.word
8179 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8181 as_bad (_("`%s%s' not allowed with `%s%c'"),
8183 i
.op
[op
].regs
->reg_name
,
8188 /* Warn if the r prefix on a general reg is missing. */
8189 else if ((i
.types
[op
].bitfield
.word
8190 || i
.types
[op
].bitfield
.dword
)
8191 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8192 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8193 && i
.tm
.operand_types
[op
].bitfield
.qword
)
8195 /* Prohibit these changes in the 64bit mode, since the
8196 lowering is more complicated. */
8197 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8198 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8205 check_word_reg (void)
8208 for (op
= i
.operands
; --op
>= 0;)
8209 /* Skip non-register operands. */
8210 if (i
.types
[op
].bitfield
.class != Reg
)
8212 /* Reject eight bit registers, except where the template requires
8213 them. (eg. movzb) */
8214 else if (i
.types
[op
].bitfield
.byte
8215 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8216 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8217 && (i
.tm
.operand_types
[op
].bitfield
.word
8218 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8220 as_bad (_("`%s%s' not allowed with `%s%c'"),
8222 i
.op
[op
].regs
->reg_name
,
8227 /* Error if the e or r prefix on a general reg is present. */
8228 else if ((i
.types
[op
].bitfield
.dword
8229 || i
.types
[op
].bitfield
.qword
)
8230 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8231 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8232 && i
.tm
.operand_types
[op
].bitfield
.word
)
8234 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8235 register_prefix
, i
.op
[op
].regs
->reg_name
,
8243 update_imm (unsigned int j
)
8245 i386_operand_type overlap
= i
.types
[j
];
8247 if (i
.tm
.operand_types
[j
].bitfield
.imm8
8248 && i
.tm
.operand_types
[j
].bitfield
.imm8s
8249 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
8251 /* This combination is used on 8-bit immediates where e.g. $~0 is
8252 desirable to permit. We're past operand type matching, so simply
8253 put things back in the shape they were before introducing the
8254 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
8255 overlap
.bitfield
.imm8s
= 0;
8258 if (overlap
.bitfield
.imm8
8259 + overlap
.bitfield
.imm8s
8260 + overlap
.bitfield
.imm16
8261 + overlap
.bitfield
.imm32
8262 + overlap
.bitfield
.imm32s
8263 + overlap
.bitfield
.imm64
> 1)
8265 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
8266 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
8267 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
8268 static const i386_operand_type imm16_32
= { .bitfield
=
8269 { .imm16
= 1, .imm32
= 1 }
8271 static const i386_operand_type imm16_32s
= { .bitfield
=
8272 { .imm16
= 1, .imm32s
= 1 }
8274 static const i386_operand_type imm16_32_32s
= { .bitfield
=
8275 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
8280 i386_operand_type temp
;
8282 operand_type_set (&temp
, 0);
8283 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
8285 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
8286 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
8288 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
8289 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
8290 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
8292 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
8293 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
8296 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
8299 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
8300 || operand_type_equal (&overlap
, &imm16_32
)
8301 || operand_type_equal (&overlap
, &imm16_32s
))
8303 if ((flag_code
== CODE_16BIT
)
8304 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
8309 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
8310 overlap
= operand_type_and (overlap
, imm32s
);
8311 else if (i
.prefix
[DATA_PREFIX
])
8312 overlap
= operand_type_and (overlap
,
8313 flag_code
!= CODE_16BIT
? imm16
: imm32
);
8314 if (overlap
.bitfield
.imm8
8315 + overlap
.bitfield
.imm8s
8316 + overlap
.bitfield
.imm16
8317 + overlap
.bitfield
.imm32
8318 + overlap
.bitfield
.imm32s
8319 + overlap
.bitfield
.imm64
!= 1)
8321 as_bad (_("no instruction mnemonic suffix given; "
8322 "can't determine immediate size"));
8326 i
.types
[j
] = overlap
;
8336 /* Update the first 2 immediate operands. */
8337 n
= i
.operands
> 2 ? 2 : i
.operands
;
8340 for (j
= 0; j
< n
; j
++)
8341 if (update_imm (j
) == 0)
8344 /* The 3rd operand can't be immediate operand. */
8345 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
8351 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8354 if (r
->reg_flags
& RegRex
)
8356 if (i
.rex
& rex_bit
)
8357 as_bad (_("same type of prefix used twice"));
8360 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8362 gas_assert (i
.vex
.register_specifier
== r
);
8363 i
.vex
.register_specifier
+= 8;
8366 if (r
->reg_flags
& RegVRex
)
8371 process_operands (void)
8373 /* Default segment register this instruction will use for memory
8374 accesses. 0 means unknown. This is only for optimizing out
8375 unnecessary segment overrides. */
8376 const reg_entry
*default_seg
= NULL
;
8378 /* We only need to check those implicit registers for instructions
8379 with 3 operands or less. */
8380 if (i
.operands
<= 3)
8381 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8382 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8385 if (i
.tm
.opcode_modifier
.sse2avx
)
8387 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8389 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8390 i
.prefix
[REX_PREFIX
] = 0;
8393 /* ImmExt should be processed after SSE2AVX. */
8394 else if (i
.tm
.opcode_modifier
.immext
)
8397 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8398 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8399 new destination operand here, while converting the source one to register
8401 if (i
.tm
.mnem_off
== MN_tilezero
)
8403 i
.op
[1].regs
= i
.op
[0].regs
;
8404 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8405 i
.types
[1] = i
.types
[0];
8406 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8407 i
.flags
[1] = i
.flags
[0];
8413 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8415 static const i386_operand_type regxmm
= {
8416 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8418 unsigned int dupl
= i
.operands
;
8419 unsigned int dest
= dupl
- 1;
8422 /* The destination must be an xmm register. */
8423 gas_assert (i
.reg_operands
8424 && MAX_OPERANDS
> dupl
8425 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8427 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8428 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8430 /* Keep xmm0 for instructions with VEX prefix and 3
8432 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8433 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8438 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8440 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8442 /* Add the implicit xmm0 for instructions with VEX prefix
8444 for (j
= i
.operands
; j
> 0; j
--)
8446 i
.op
[j
] = i
.op
[j
- 1];
8447 i
.types
[j
] = i
.types
[j
- 1];
8448 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8449 i
.flags
[j
] = i
.flags
[j
- 1];
8452 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8453 i
.types
[0] = regxmm
;
8454 i
.tm
.operand_types
[0] = regxmm
;
8457 i
.reg_operands
+= 2;
8462 i
.op
[dupl
] = i
.op
[dest
];
8463 i
.types
[dupl
] = i
.types
[dest
];
8464 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8465 i
.flags
[dupl
] = i
.flags
[dest
];
8474 i
.op
[dupl
] = i
.op
[dest
];
8475 i
.types
[dupl
] = i
.types
[dest
];
8476 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8477 i
.flags
[dupl
] = i
.flags
[dest
];
8480 if (i
.tm
.opcode_modifier
.immext
)
8483 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8484 && i
.tm
.opcode_modifier
.modrm
)
8488 for (j
= 1; j
< i
.operands
; j
++)
8490 i
.op
[j
- 1] = i
.op
[j
];
8491 i
.types
[j
- 1] = i
.types
[j
];
8493 /* We need to adjust fields in i.tm since they are used by
8494 build_modrm_byte. */
8495 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8497 i
.flags
[j
- 1] = i
.flags
[j
];
8500 /* No adjustment to i.reg_operands: This was already done at the top
8505 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8507 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8509 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8510 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8511 regnum
= register_number (i
.op
[1].regs
);
8512 first_reg_in_group
= regnum
& ~3;
8513 last_reg_in_group
= first_reg_in_group
+ 3;
8514 if (regnum
!= first_reg_in_group
)
8515 as_warn (_("source register `%s%s' implicitly denotes"
8516 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8517 register_prefix
, i
.op
[1].regs
->reg_name
,
8518 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8519 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8522 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8524 /* The imul $imm, %reg instruction is converted into
8525 imul $imm, %reg, %reg, and the clr %reg instruction
8526 is converted into xor %reg, %reg. */
8528 unsigned int first_reg_op
;
8530 if (operand_type_check (i
.types
[0], reg
))
8534 /* Pretend we saw the extra register operand. */
8535 gas_assert (i
.reg_operands
== 1
8536 && i
.op
[first_reg_op
+ 1].regs
== 0);
8537 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8538 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8543 if (i
.tm
.opcode_modifier
.modrm
)
8545 /* The opcode is completed (modulo i.tm.extension_opcode which
8546 must be put into the modrm byte). Now, we make the modrm and
8547 index base bytes based on all the info we've collected. */
8549 default_seg
= build_modrm_byte ();
8551 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8553 /* Warn about some common errors, but press on regardless. */
8554 if (i
.operands
== 2)
8556 /* Reversed arguments on faddp or fmulp. */
8557 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8558 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8559 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8561 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8563 /* Extraneous `l' suffix on fp insn. */
8564 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8565 register_prefix
, i
.op
[0].regs
->reg_name
);
8569 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
8571 if (flag_code
!= CODE_64BIT
8572 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8573 && i
.op
[0].regs
->reg_num
== 1
8574 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8575 && i
.op
[0].regs
->reg_num
< 4)
8577 as_bad (_("you can't `%s %s%s'"),
8578 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8581 if (i
.op
[0].regs
->reg_num
> 3
8582 && i
.tm
.opcode_space
== SPACE_BASE
)
8584 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8585 i
.tm
.opcode_space
= SPACE_0F
;
8587 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8589 else if (i
.tm
.opcode_space
== SPACE_BASE
8590 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8592 default_seg
= reg_ds
;
8594 else if (i
.tm
.opcode_modifier
.isstring
)
8596 /* For the string instructions that allow a segment override
8597 on one of their operands, the default segment is ds. */
8598 default_seg
= reg_ds
;
8600 else if (i
.short_form
)
8602 /* The register operand is in the 1st or 2nd non-immediate operand. */
8603 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
8606 && r
->reg_type
.bitfield
.instance
== Accum
8607 && i
.op
[i
.imm_operands
+ 1].regs
)
8608 r
= i
.op
[i
.imm_operands
+ 1].regs
;
8609 /* Register goes in low 3 bits of opcode. */
8610 i
.tm
.base_opcode
|= r
->reg_num
;
8611 set_rex_vrex (r
, REX_B
, false);
8613 if (dot_insn () && i
.reg_operands
== 2)
8615 gas_assert (is_any_vex_encoding (&i
.tm
)
8616 || i
.vec_encoding
!= vex_encoding_default
);
8617 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8620 else if (i
.reg_operands
== 1
8621 && !i
.flags
[i
.operands
- 1]
8622 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
8625 gas_assert (is_any_vex_encoding (&i
.tm
)
8626 || i
.vec_encoding
!= vex_encoding_default
);
8627 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8630 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8631 && i
.tm
.mnem_off
== MN_lea
)
8633 if (!quiet_warnings
)
8634 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8635 if (optimize
&& !i
.no_optimize
)
8638 i
.prefix
[SEG_PREFIX
] = 0;
8642 /* If a segment was explicitly specified, and the specified segment
8643 is neither the default nor the one already recorded from a prefix,
8644 use an opcode prefix to select it. If we never figured out what
8645 the default segment is, then default_seg will be zero at this
8646 point, and the specified segment prefix will always be used. */
8648 && i
.seg
[0] != default_seg
8649 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8651 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8657 static const reg_entry
*
8658 build_modrm_byte (void)
8660 const reg_entry
*default_seg
= NULL
;
8661 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8662 /* Compensate for kludge in md_assemble(). */
8663 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8664 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8665 unsigned int v
, op
, reg_slot
= ~0;
8667 /* Accumulator (in particular %st), shift count (%cl), and alike need
8668 to be skipped just like immediate operands do. */
8669 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8671 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8674 for (op
= source
; op
< i
.operands
; ++op
)
8675 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8678 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8682 /* There are 2 kinds of instructions:
8683 1. 5 operands: 4 register operands or 3 register operands
8684 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8685 VexW0 or VexW1. The destination must be either XMM, YMM or
8687 2. 4 operands: 4 register operands or 3 register operands
8688 plus 1 memory operand, with VexXDS.
8689 3. Other equivalent combinations when coming from s_insn(). */
8690 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8691 && i
.tm
.opcode_modifier
.vexw
);
8692 gas_assert (dot_insn ()
8693 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8695 /* Of the first two non-immediate operands the one with the template
8696 not allowing for a memory one is encoded in the immediate operand. */
8698 reg_slot
= source
+ 1;
8700 reg_slot
= source
++;
8704 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8705 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
8708 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
8710 if (i
.imm_operands
== 0)
8712 /* When there is no immediate operand, generate an 8bit
8713 immediate operand to encode the first operand. */
8714 exp
= &im_expressions
[i
.imm_operands
++];
8715 i
.op
[i
.operands
].imms
= exp
;
8716 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8719 exp
->X_op
= O_constant
;
8723 gas_assert (i
.imm_operands
== 1);
8724 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8725 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8727 /* Turn on Imm8 again so that output_imm will generate it. */
8728 i
.types
[0].bitfield
.imm8
= 1;
8732 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
8733 << (3 + !(is_evex_encoding (&i
.tm
)
8734 || i
.vec_encoding
== vex_encoding_evex
));
8737 for (v
= source
+ 1; v
< dest
; ++v
)
8742 if (i
.tm
.extension_opcode
!= None
)
8748 gas_assert (source
< dest
);
8749 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8752 unsigned int tmp
= source
;
8758 if (v
< MAX_OPERANDS
)
8760 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8761 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8764 if (op
< i
.operands
)
8768 unsigned int fake_zero_displacement
= 0;
8770 gas_assert (i
.flags
[op
] & Operand_Mem
);
8772 if (i
.tm
.opcode_modifier
.sib
)
8774 /* The index register of VSIB shouldn't be RegIZ. */
8775 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8776 && i
.index_reg
->reg_num
== RegIZ
)
8779 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8782 i
.sib
.base
= NO_BASE_REGISTER
;
8783 i
.sib
.scale
= i
.log2_scale_factor
;
8784 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8785 i
.types
[op
].bitfield
.disp32
= 1;
8788 /* Since the mandatory SIB always has index register, so
8789 the code logic remains unchanged. The non-mandatory SIB
8790 without index register is allowed and will be handled
8794 if (i
.index_reg
->reg_num
== RegIZ
)
8795 i
.sib
.index
= NO_INDEX_REGISTER
;
8797 i
.sib
.index
= i
.index_reg
->reg_num
;
8798 set_rex_vrex (i
.index_reg
, REX_X
, false);
8802 default_seg
= reg_ds
;
8804 if (i
.base_reg
== 0)
8807 if (!i
.disp_operands
)
8808 fake_zero_displacement
= 1;
8809 if (i
.index_reg
== 0)
8811 /* Both check for VSIB and mandatory non-vector SIB. */
8812 gas_assert (!i
.tm
.opcode_modifier
.sib
8813 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8814 /* Operand is just <disp> */
8815 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8816 if (flag_code
== CODE_64BIT
)
8818 /* 64bit mode overwrites the 32bit absolute
8819 addressing by RIP relative addressing and
8820 absolute addressing is encoded by one of the
8821 redundant SIB forms. */
8822 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8823 i
.sib
.base
= NO_BASE_REGISTER
;
8824 i
.sib
.index
= NO_INDEX_REGISTER
;
8825 i
.types
[op
].bitfield
.disp32
= 1;
8827 else if ((flag_code
== CODE_16BIT
)
8828 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8830 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8831 i
.types
[op
].bitfield
.disp16
= 1;
8835 i
.rm
.regmem
= NO_BASE_REGISTER
;
8836 i
.types
[op
].bitfield
.disp32
= 1;
8839 else if (!i
.tm
.opcode_modifier
.sib
)
8841 /* !i.base_reg && i.index_reg */
8842 if (i
.index_reg
->reg_num
== RegIZ
)
8843 i
.sib
.index
= NO_INDEX_REGISTER
;
8845 i
.sib
.index
= i
.index_reg
->reg_num
;
8846 i
.sib
.base
= NO_BASE_REGISTER
;
8847 i
.sib
.scale
= i
.log2_scale_factor
;
8848 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8849 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8850 i
.types
[op
].bitfield
.disp32
= 1;
8851 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8855 /* RIP addressing for 64bit mode. */
8856 else if (i
.base_reg
->reg_num
== RegIP
)
8858 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8859 i
.rm
.regmem
= NO_BASE_REGISTER
;
8860 i
.types
[op
].bitfield
.disp8
= 0;
8861 i
.types
[op
].bitfield
.disp16
= 0;
8862 i
.types
[op
].bitfield
.disp32
= 1;
8863 i
.types
[op
].bitfield
.disp64
= 0;
8864 i
.flags
[op
] |= Operand_PCrel
;
8865 if (! i
.disp_operands
)
8866 fake_zero_displacement
= 1;
8868 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8870 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8871 switch (i
.base_reg
->reg_num
)
8874 if (i
.index_reg
== 0)
8876 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8877 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8880 default_seg
= reg_ss
;
8881 if (i
.index_reg
== 0)
8884 if (operand_type_check (i
.types
[op
], disp
) == 0)
8886 /* fake (%bp) into 0(%bp) */
8887 if (i
.disp_encoding
== disp_encoding_16bit
)
8888 i
.types
[op
].bitfield
.disp16
= 1;
8890 i
.types
[op
].bitfield
.disp8
= 1;
8891 fake_zero_displacement
= 1;
8894 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8895 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8897 default: /* (%si) -> 4 or (%di) -> 5 */
8898 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8900 if (!fake_zero_displacement
8904 fake_zero_displacement
= 1;
8905 if (i
.disp_encoding
== disp_encoding_8bit
)
8906 i
.types
[op
].bitfield
.disp8
= 1;
8908 i
.types
[op
].bitfield
.disp16
= 1;
8910 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8912 else /* i.base_reg and 32/64 bit mode */
8914 if (operand_type_check (i
.types
[op
], disp
))
8916 i
.types
[op
].bitfield
.disp16
= 0;
8917 i
.types
[op
].bitfield
.disp64
= 0;
8918 i
.types
[op
].bitfield
.disp32
= 1;
8921 if (!i
.tm
.opcode_modifier
.sib
)
8922 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8923 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8925 i
.sib
.base
= i
.base_reg
->reg_num
;
8926 /* x86-64 ignores REX prefix bit here to avoid decoder
8928 if (!(i
.base_reg
->reg_flags
& RegRex
)
8929 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8930 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8931 default_seg
= reg_ss
;
8932 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8934 fake_zero_displacement
= 1;
8935 if (i
.disp_encoding
== disp_encoding_32bit
)
8936 i
.types
[op
].bitfield
.disp32
= 1;
8938 i
.types
[op
].bitfield
.disp8
= 1;
8940 i
.sib
.scale
= i
.log2_scale_factor
;
8941 if (i
.index_reg
== 0)
8943 /* Only check for VSIB. */
8944 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8945 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8946 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8948 /* <disp>(%esp) becomes two byte modrm with no index
8949 register. We've already stored the code for esp
8950 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8951 Any base register besides %esp will not use the
8952 extra modrm byte. */
8953 i
.sib
.index
= NO_INDEX_REGISTER
;
8955 else if (!i
.tm
.opcode_modifier
.sib
)
8957 if (i
.index_reg
->reg_num
== RegIZ
)
8958 i
.sib
.index
= NO_INDEX_REGISTER
;
8960 i
.sib
.index
= i
.index_reg
->reg_num
;
8961 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8962 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8967 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8968 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8972 if (!fake_zero_displacement
8976 fake_zero_displacement
= 1;
8977 if (i
.disp_encoding
== disp_encoding_8bit
)
8978 i
.types
[op
].bitfield
.disp8
= 1;
8980 i
.types
[op
].bitfield
.disp32
= 1;
8982 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8986 if (fake_zero_displacement
)
8988 /* Fakes a zero displacement assuming that i.types[op]
8989 holds the correct displacement size. */
8992 gas_assert (i
.op
[op
].disps
== 0);
8993 exp
= &disp_expressions
[i
.disp_operands
++];
8994 i
.op
[op
].disps
= exp
;
8995 exp
->X_op
= O_constant
;
8996 exp
->X_add_number
= 0;
8997 exp
->X_add_symbol
= (symbolS
*) 0;
8998 exp
->X_op_symbol
= (symbolS
*) 0;
9004 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
9005 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
9016 if (!i
.tm
.opcode_modifier
.regmem
)
9018 gas_assert (source
< MAX_OPERANDS
);
9019 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
9020 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
9021 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
9026 gas_assert (dest
< MAX_OPERANDS
);
9027 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
9028 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
9033 /* Fill in i.rm.reg field with extension opcode (if any) or the
9034 appropriate register. */
9035 if (i
.tm
.extension_opcode
!= None
)
9036 i
.rm
.reg
= i
.tm
.extension_opcode
;
9037 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
9039 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
9040 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
9044 gas_assert (source
< MAX_OPERANDS
);
9045 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
9046 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
9049 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
9051 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
9053 add_prefix (LOCK_PREFIX_OPCODE
);
9060 frag_opcode_byte (unsigned char byte
)
9062 if (now_seg
!= absolute_section
)
9063 FRAG_APPEND_1_CHAR (byte
);
9065 ++abs_section_offset
;
9069 flip_code16 (unsigned int code16
)
9071 gas_assert (i
.tm
.operands
== 1);
9073 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
9074 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
9075 : i
.tm
.operand_types
[0].bitfield
.disp16
)
9080 output_branch (void)
9086 relax_substateT subtype
;
9090 if (now_seg
== absolute_section
)
9092 as_bad (_("relaxable branches not supported in absolute section"));
9096 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
9097 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
9100 if (i
.prefix
[DATA_PREFIX
] != 0)
9104 code16
^= flip_code16(code16
);
9106 /* Pentium4 branch hints. */
9107 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9108 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9113 if (i
.prefix
[REX_PREFIX
] != 0)
9119 /* BND prefixed jump. */
9120 if (i
.prefix
[BND_PREFIX
] != 0)
9126 if (i
.prefixes
!= 0)
9127 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9129 /* It's always a symbol; End frag & setup for relax.
9130 Make sure there is enough room in this frag for the largest
9131 instruction we may generate in md_convert_frag. This is 2
9132 bytes for the opcode and room for the prefix and largest
9134 frag_grow (prefix
+ 2 + 4);
9135 /* Prefix and 1 opcode byte go in fr_fix. */
9136 p
= frag_more (prefix
+ 1);
9137 if (i
.prefix
[DATA_PREFIX
] != 0)
9138 *p
++ = DATA_PREFIX_OPCODE
;
9139 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
9140 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
9141 *p
++ = i
.prefix
[SEG_PREFIX
];
9142 if (i
.prefix
[BND_PREFIX
] != 0)
9143 *p
++ = BND_PREFIX_OPCODE
;
9144 if (i
.prefix
[REX_PREFIX
] != 0)
9145 *p
++ = i
.prefix
[REX_PREFIX
];
9146 *p
= i
.tm
.base_opcode
;
9148 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
9149 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
9150 else if (cpu_arch_flags
.bitfield
.cpui386
)
9151 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
9153 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
9156 sym
= i
.op
[0].disps
->X_add_symbol
;
9157 off
= i
.op
[0].disps
->X_add_number
;
9159 if (i
.op
[0].disps
->X_op
!= O_constant
9160 && i
.op
[0].disps
->X_op
!= O_symbol
)
9162 /* Handle complex expressions. */
9163 sym
= make_expr_symbol (i
.op
[0].disps
);
9167 /* 1 possible extra opcode + 4 byte displacement go in var part.
9168 Pass reloc in fr_var. */
9169 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
9172 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9173 /* Return TRUE iff PLT32 relocation should be used for branching to
9177 need_plt32_p (symbolS
*s
)
9179 /* PLT32 relocation is ELF only. */
9184 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
9185 krtld support it. */
9189 /* Since there is no need to prepare for PLT branch on x86-64, we
9190 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
9191 be used as a marker for 32-bit PC-relative branches. */
9198 /* Weak or undefined symbol need PLT32 relocation. */
9199 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
9202 /* Non-global symbol doesn't need PLT32 relocation. */
9203 if (! S_IS_EXTERNAL (s
))
9206 /* Other global symbols need PLT32 relocation. NB: Symbol with
9207 non-default visibilities are treated as normal global symbol
9208 so that PLT32 relocation can be used as a marker for 32-bit
9209 PC-relative branches. It is useful for linker relaxation. */
9220 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
9222 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
9224 /* This is a loop or jecxz type instruction. */
9226 if (i
.prefix
[ADDR_PREFIX
] != 0)
9228 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
9231 /* Pentium4 branch hints. */
9232 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9233 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9235 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
9244 if (flag_code
== CODE_16BIT
)
9247 if (i
.prefix
[DATA_PREFIX
] != 0)
9249 frag_opcode_byte (DATA_PREFIX_OPCODE
);
9251 code16
^= flip_code16(code16
);
9259 /* BND prefixed jump. */
9260 if (i
.prefix
[BND_PREFIX
] != 0)
9262 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
9266 if (i
.prefix
[REX_PREFIX
] != 0)
9268 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
9272 if (i
.prefixes
!= 0)
9273 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9275 if (now_seg
== absolute_section
)
9277 abs_section_offset
+= i
.opcode_length
+ size
;
9281 p
= frag_more (i
.opcode_length
+ size
);
9282 switch (i
.opcode_length
)
9285 *p
++ = i
.tm
.base_opcode
>> 8;
9288 *p
++ = i
.tm
.base_opcode
;
9294 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9295 if (flag_code
== CODE_64BIT
&& size
== 4
9296 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
9297 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
9298 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
9301 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
9303 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9304 i
.op
[0].disps
, 1, jump_reloc
);
9306 /* All jumps handled here are signed, but don't unconditionally use a
9307 signed limit check for 32 and 16 bit jumps as we want to allow wrap
9308 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
9313 fixP
->fx_signed
= 1;
9317 if (i
.tm
.mnem_off
== MN_xbegin
)
9318 fixP
->fx_signed
= 1;
9322 if (flag_code
== CODE_64BIT
)
9323 fixP
->fx_signed
= 1;
9329 output_interseg_jump (void)
9337 if (flag_code
== CODE_16BIT
)
9341 if (i
.prefix
[DATA_PREFIX
] != 0)
9348 gas_assert (!i
.prefix
[REX_PREFIX
]);
9354 if (i
.prefixes
!= 0)
9355 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9357 if (now_seg
== absolute_section
)
9359 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9363 /* 1 opcode; 2 segment; offset */
9364 p
= frag_more (prefix
+ 1 + 2 + size
);
9366 if (i
.prefix
[DATA_PREFIX
] != 0)
9367 *p
++ = DATA_PREFIX_OPCODE
;
9369 if (i
.prefix
[REX_PREFIX
] != 0)
9370 *p
++ = i
.prefix
[REX_PREFIX
];
9372 *p
++ = i
.tm
.base_opcode
;
9373 if (i
.op
[1].imms
->X_op
== O_constant
)
9375 offsetT n
= i
.op
[1].imms
->X_add_number
;
9378 && !fits_in_unsigned_word (n
)
9379 && !fits_in_signed_word (n
))
9381 as_bad (_("16-bit jump out of range"));
9384 md_number_to_chars (p
, n
, size
);
9387 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9388 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9391 if (i
.op
[0].imms
->X_op
== O_constant
)
9392 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9394 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9395 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9398 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9403 asection
*seg
= now_seg
;
9404 subsegT subseg
= now_subseg
;
9406 unsigned int alignment
, align_size_1
;
9407 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9408 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9409 unsigned int padding
;
9411 if (!IS_ELF
|| !x86_used_note
)
9414 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9416 /* The .note.gnu.property section layout:
9418 Field Length Contents
9421 n_descsz 4 The note descriptor size
9422 n_type 4 NT_GNU_PROPERTY_TYPE_0
9424 n_desc n_descsz The program property array
9428 /* Create the .note.gnu.property section. */
9429 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9430 bfd_set_section_flags (sec
,
9437 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9448 bfd_set_section_alignment (sec
, alignment
);
9449 elf_section_type (sec
) = SHT_NOTE
;
9451 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9453 isa_1_descsz_raw
= 4 + 4 + 4;
9454 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9455 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9457 feature_2_descsz_raw
= isa_1_descsz
;
9458 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9460 feature_2_descsz_raw
+= 4 + 4 + 4;
9461 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9462 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9465 descsz
= feature_2_descsz
;
9466 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9467 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9469 /* Write n_namsz. */
9470 md_number_to_chars (p
, (valueT
) 4, 4);
9472 /* Write n_descsz. */
9473 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9476 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9479 memcpy (p
+ 4 * 3, "GNU", 4);
9481 /* Write 4-byte type. */
9482 md_number_to_chars (p
+ 4 * 4,
9483 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9485 /* Write 4-byte data size. */
9486 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9488 /* Write 4-byte data. */
9489 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9491 /* Zero out paddings. */
9492 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9494 memset (p
+ 4 * 7, 0, padding
);
9496 /* Write 4-byte type. */
9497 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9498 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9500 /* Write 4-byte data size. */
9501 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9503 /* Write 4-byte data. */
9504 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9505 (valueT
) x86_feature_2_used
, 4);
9507 /* Zero out paddings. */
9508 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9510 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9512 /* We probably can't restore the current segment, for there likely
9515 subseg_set (seg
, subseg
);
9519 x86_support_sframe_p (void)
9521 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9522 return (x86_elf_abi
== X86_64_ABI
);
9526 x86_sframe_ra_tracking_p (void)
9528 /* In AMD64, return address is always stored on the stack at a fixed offset
9529 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9530 Do not track explicitly via an SFrame Frame Row Entry. */
9535 x86_sframe_cfa_ra_offset (void)
9537 gas_assert (x86_elf_abi
== X86_64_ABI
);
9538 return (offsetT
) -8;
9542 x86_sframe_get_abi_arch (void)
9544 unsigned char sframe_abi_arch
= 0;
9546 if (x86_support_sframe_p ())
9548 gas_assert (!target_big_endian
);
9549 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9552 return sframe_abi_arch
;
9558 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9559 const char *frag_now_ptr
)
9561 unsigned int len
= 0;
9563 if (start_frag
!= frag_now
)
9565 const fragS
*fr
= start_frag
;
9570 } while (fr
&& fr
!= frag_now
);
9573 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9576 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9577 be macro-fused with conditional jumps.
9578 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9579 or is one of the following format:
9592 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9594 /* No RIP address. */
9595 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9598 /* No opcodes outside of base encoding space. */
9599 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9602 /* add, sub without add/sub m, imm. */
9603 if (i
.tm
.base_opcode
<= 5
9604 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9605 || ((i
.tm
.base_opcode
| 3) == 0x83
9606 && (i
.tm
.extension_opcode
== 0x5
9607 || i
.tm
.extension_opcode
== 0x0)))
9609 *mf_cmp_p
= mf_cmp_alu_cmp
;
9610 return !(i
.mem_operands
&& i
.imm_operands
);
9613 /* and without and m, imm. */
9614 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9615 || ((i
.tm
.base_opcode
| 3) == 0x83
9616 && i
.tm
.extension_opcode
== 0x4))
9618 *mf_cmp_p
= mf_cmp_test_and
;
9619 return !(i
.mem_operands
&& i
.imm_operands
);
9622 /* test without test m imm. */
9623 if ((i
.tm
.base_opcode
| 1) == 0x85
9624 || (i
.tm
.base_opcode
| 1) == 0xa9
9625 || ((i
.tm
.base_opcode
| 1) == 0xf7
9626 && i
.tm
.extension_opcode
== 0))
9628 *mf_cmp_p
= mf_cmp_test_and
;
9629 return !(i
.mem_operands
&& i
.imm_operands
);
9632 /* cmp without cmp m, imm. */
9633 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9634 || ((i
.tm
.base_opcode
| 3) == 0x83
9635 && (i
.tm
.extension_opcode
== 0x7)))
9637 *mf_cmp_p
= mf_cmp_alu_cmp
;
9638 return !(i
.mem_operands
&& i
.imm_operands
);
9641 /* inc, dec without inc/dec m. */
9642 if ((is_cpu (&i
.tm
, CpuNo64
)
9643 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9644 || ((i
.tm
.base_opcode
| 1) == 0xff
9645 && i
.tm
.extension_opcode
<= 0x1))
9647 *mf_cmp_p
= mf_cmp_incdec
;
9648 return !i
.mem_operands
;
9654 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9657 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9659 /* NB: Don't work with COND_JUMP86 without i386. */
9660 if (!align_branch_power
9661 || now_seg
== absolute_section
9662 || !cpu_arch_flags
.bitfield
.cpui386
9663 || !(align_branch
& align_branch_fused_bit
))
9666 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9668 if (last_insn
.kind
== last_insn_other
9669 || last_insn
.seg
!= now_seg
)
9672 as_warn_where (last_insn
.file
, last_insn
.line
,
9673 _("`%s` skips -malign-branch-boundary on `%s`"),
9674 last_insn
.name
, insn_name (&i
.tm
));
9680 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9683 add_branch_prefix_frag_p (void)
9685 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9686 to PadLock instructions since they include prefixes in opcode. */
9687 if (!align_branch_power
9688 || !align_branch_prefix_size
9689 || now_seg
== absolute_section
9690 || is_cpu (&i
.tm
, CpuPadLock
)
9691 || !cpu_arch_flags
.bitfield
.cpui386
)
9694 /* Don't add prefix if it is a prefix or there is no operand in case
9695 that segment prefix is special. */
9696 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9699 if (last_insn
.kind
== last_insn_other
9700 || last_insn
.seg
!= now_seg
)
9704 as_warn_where (last_insn
.file
, last_insn
.line
,
9705 _("`%s` skips -malign-branch-boundary on `%s`"),
9706 last_insn
.name
, insn_name (&i
.tm
));
9711 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9714 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9715 enum mf_jcc_kind
*mf_jcc_p
)
9719 /* NB: Don't work with COND_JUMP86 without i386. */
9720 if (!align_branch_power
9721 || now_seg
== absolute_section
9722 || !cpu_arch_flags
.bitfield
.cpui386
9723 || i
.tm
.opcode_space
!= SPACE_BASE
)
9728 /* Check for jcc and direct jmp. */
9729 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9731 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9733 *branch_p
= align_branch_jmp
;
9734 add_padding
= align_branch
& align_branch_jmp_bit
;
9738 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9739 igore the lowest bit. */
9740 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9741 *branch_p
= align_branch_jcc
;
9742 if ((align_branch
& align_branch_jcc_bit
))
9746 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9749 *branch_p
= align_branch_ret
;
9750 if ((align_branch
& align_branch_ret_bit
))
9755 /* Check for indirect jmp, direct and indirect calls. */
9756 if (i
.tm
.base_opcode
== 0xe8)
9759 *branch_p
= align_branch_call
;
9760 if ((align_branch
& align_branch_call_bit
))
9763 else if (i
.tm
.base_opcode
== 0xff
9764 && (i
.tm
.extension_opcode
== 2
9765 || i
.tm
.extension_opcode
== 4))
9767 /* Indirect call and jmp. */
9768 *branch_p
= align_branch_indirect
;
9769 if ((align_branch
& align_branch_indirect_bit
))
9776 && (i
.op
[0].disps
->X_op
== O_symbol
9777 || (i
.op
[0].disps
->X_op
== O_subtract
9778 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9780 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9781 /* No padding to call to global or undefined tls_get_addr. */
9782 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9783 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9789 && last_insn
.kind
!= last_insn_other
9790 && last_insn
.seg
== now_seg
)
9793 as_warn_where (last_insn
.file
, last_insn
.line
,
9794 _("`%s` skips -malign-branch-boundary on `%s`"),
9795 last_insn
.name
, insn_name (&i
.tm
));
9805 fragS
*insn_start_frag
;
9806 offsetT insn_start_off
;
9807 fragS
*fragP
= NULL
;
9808 enum align_branch_kind branch
= align_branch_none
;
9809 /* The initializer is arbitrary just to avoid uninitialized error.
9810 it's actually either assigned in add_branch_padding_frag_p
9811 or never be used. */
9812 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9814 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9815 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9817 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9818 || is_cpu (&i
.tm
, CpuAMX_TILE
))
9819 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9821 if (is_cpu (&i
.tm
, Cpu8087
)
9822 || is_cpu (&i
.tm
, Cpu287
)
9823 || is_cpu (&i
.tm
, Cpu387
)
9824 || is_cpu (&i
.tm
, Cpu687
)
9825 || is_cpu (&i
.tm
, CpuFISTTP
))
9826 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9828 if ((i
.xstate
& xstate_mmx
)
9829 || i
.tm
.mnem_off
== MN_emms
9830 || i
.tm
.mnem_off
== MN_femms
)
9831 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9835 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9836 i
.xstate
|= xstate_zmm
;
9837 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9838 i
.xstate
|= xstate_ymm
;
9839 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9840 i
.xstate
|= xstate_xmm
;
9843 /* vzeroall / vzeroupper */
9844 if (i
.tm
.base_opcode
== 0x77 && is_cpu (&i
.tm
, CpuAVX
))
9845 i
.xstate
|= xstate_ymm
;
9847 if ((i
.xstate
& xstate_xmm
)
9848 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9849 || (i
.tm
.base_opcode
== 0xae
9850 && (is_cpu (&i
.tm
, CpuSSE
)
9851 || is_cpu (&i
.tm
, CpuAVX
)))
9852 || is_cpu (&i
.tm
, CpuWideKL
)
9853 || is_cpu (&i
.tm
, CpuKL
))
9854 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9856 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9857 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9858 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9859 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9860 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9861 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9862 if (is_cpu (&i
.tm
, CpuFXSR
))
9863 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9864 if (is_cpu (&i
.tm
, CpuXsave
))
9865 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9866 if (is_cpu (&i
.tm
, CpuXsaveopt
))
9867 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9868 if (is_cpu (&i
.tm
, CpuXSAVEC
))
9869 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9871 if (x86_feature_2_used
9872 || is_cpu (&i
.tm
, CpuCMOV
)
9873 || is_cpu (&i
.tm
, CpuSYSCALL
)
9874 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9875 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9876 if (is_cpu (&i
.tm
, CpuSSE3
)
9877 || is_cpu (&i
.tm
, CpuSSSE3
)
9878 || is_cpu (&i
.tm
, CpuSSE4_1
)
9879 || is_cpu (&i
.tm
, CpuSSE4_2
)
9880 || is_cpu (&i
.tm
, CpuCX16
)
9881 || is_cpu (&i
.tm
, CpuPOPCNT
)
9882 /* LAHF-SAHF insns in 64-bit mode. */
9883 || (flag_code
== CODE_64BIT
9884 && (i
.tm
.base_opcode
| 1) == 0x9f
9885 && i
.tm
.opcode_space
== SPACE_BASE
))
9886 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9887 if (is_cpu (&i
.tm
, CpuAVX
)
9888 || is_cpu (&i
.tm
, CpuAVX2
)
9889 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9890 XOP, FMA4, LPW, TBM, and AMX. */
9891 || (i
.tm
.opcode_modifier
.vex
9892 && !is_cpu (&i
.tm
, CpuAVX512F
)
9893 && !is_cpu (&i
.tm
, CpuAVX512BW
)
9894 && !is_cpu (&i
.tm
, CpuAVX512DQ
)
9895 && !is_cpu (&i
.tm
, CpuXOP
)
9896 && !is_cpu (&i
.tm
, CpuFMA4
)
9897 && !is_cpu (&i
.tm
, CpuLWP
)
9898 && !is_cpu (&i
.tm
, CpuTBM
)
9899 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9900 || is_cpu (&i
.tm
, CpuF16C
)
9901 || is_cpu (&i
.tm
, CpuFMA
)
9902 || is_cpu (&i
.tm
, CpuLZCNT
)
9903 || is_cpu (&i
.tm
, CpuMovbe
)
9904 || is_cpu (&i
.tm
, CpuXSAVES
)
9905 || (x86_feature_2_used
9906 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9907 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9908 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9909 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9910 if (is_cpu (&i
.tm
, CpuAVX512F
)
9911 || is_cpu (&i
.tm
, CpuAVX512BW
)
9912 || is_cpu (&i
.tm
, CpuAVX512DQ
)
9913 || is_cpu (&i
.tm
, CpuAVX512VL
)
9914 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9915 AVX512-4FMAPS, and AVX512-4VNNIW. */
9916 || (i
.tm
.opcode_modifier
.evex
9917 && !is_cpu (&i
.tm
, CpuAVX512ER
)
9918 && !is_cpu (&i
.tm
, CpuAVX512PF
)
9919 && !is_cpu (&i
.tm
, CpuAVX512_4FMAPS
)
9920 && !is_cpu (&i
.tm
, CpuAVX512_4VNNIW
)))
9921 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9925 /* Tie dwarf2 debug info to the address at the start of the insn.
9926 We can't do this after the insn has been output as the current
9927 frag may have been closed off. eg. by frag_var. */
9928 dwarf2_emit_insn (0);
9930 insn_start_frag
= frag_now
;
9931 insn_start_off
= frag_now_fix ();
9933 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9936 /* Branch can be 8 bytes. Leave some room for prefixes. */
9937 unsigned int max_branch_padding_size
= 14;
9939 /* Align section to boundary. */
9940 record_alignment (now_seg
, align_branch_power
);
9942 /* Make room for padding. */
9943 frag_grow (max_branch_padding_size
);
9945 /* Start of the padding. */
9950 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9951 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9954 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9955 fragP
->tc_frag_data
.branch_type
= branch
;
9956 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9959 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9960 && !pre_386_16bit_warned
)
9962 as_warn (_("use .code16 to ensure correct addressing mode"));
9963 pre_386_16bit_warned
= true;
9967 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9969 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9970 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9972 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9973 output_interseg_jump ();
9976 /* Output normal instructions here. */
9980 enum mf_cmp_kind mf_cmp
;
9983 && (i
.tm
.base_opcode
== 0xaee8
9984 || i
.tm
.base_opcode
== 0xaef0
9985 || i
.tm
.base_opcode
== 0xaef8))
9987 /* Encode lfence, mfence, and sfence as
9988 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9989 if (flag_code
== CODE_16BIT
)
9990 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9991 else if (omit_lock_prefix
)
9992 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9994 else if (now_seg
!= absolute_section
)
9996 offsetT val
= 0x240483f0ULL
;
9999 md_number_to_chars (p
, val
, 5);
10002 abs_section_offset
+= 5;
10006 /* Some processors fail on LOCK prefix. This options makes
10007 assembler ignore LOCK prefix and serves as a workaround. */
10008 if (omit_lock_prefix
)
10010 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
10011 && i
.tm
.opcode_modifier
.isprefix
)
10013 i
.prefix
[LOCK_PREFIX
] = 0;
10017 /* Skip if this is a branch. */
10019 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
10021 /* Make room for padding. */
10022 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
10027 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
10028 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
10031 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
10032 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
10033 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
10035 else if (add_branch_prefix_frag_p ())
10037 unsigned int max_prefix_size
= align_branch_prefix_size
;
10039 /* Make room for padding. */
10040 frag_grow (max_prefix_size
);
10045 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
10046 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
10049 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
10052 /* Since the VEX/EVEX prefix contains the implicit prefix, we
10053 don't need the explicit prefix. */
10054 if (!is_any_vex_encoding (&i
.tm
))
10056 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
10065 if (!is_cpu (&i
.tm
, CpuPadLock
)
10066 || (i
.prefix
[REP_PREFIX
] != 0xf3))
10070 switch (i
.opcode_length
)
10075 /* Check for pseudo prefixes. */
10076 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
10078 as_bad_where (insn_start_frag
->fr_file
,
10079 insn_start_frag
->fr_line
,
10080 _("pseudo prefix without instruction"));
10090 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10091 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
10092 R_X86_64_GOTTPOFF relocation so that linker can safely
10093 perform IE->LE optimization. A dummy REX_OPCODE prefix
10094 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
10095 relocation for GDesc -> IE/LE optimization. */
10096 if (x86_elf_abi
== X86_64_X32_ABI
10098 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
10099 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
10100 && i
.prefix
[REX_PREFIX
] == 0)
10101 add_prefix (REX_OPCODE
);
10104 /* The prefix bytes. */
10105 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
10107 frag_opcode_byte (*q
);
10111 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
10117 frag_opcode_byte (*q
);
10120 /* There should be no other prefixes for instructions
10121 with VEX prefix. */
10125 /* For EVEX instructions i.vrex should become 0 after
10126 build_evex_prefix. For VEX instructions upper 16 registers
10127 aren't available, so VREX should be 0. */
10130 /* Now the VEX prefix. */
10131 if (now_seg
!= absolute_section
)
10133 p
= frag_more (i
.vex
.length
);
10134 for (j
= 0; j
< i
.vex
.length
; j
++)
10135 p
[j
] = i
.vex
.bytes
[j
];
10138 abs_section_offset
+= i
.vex
.length
;
10141 /* Now the opcode; be careful about word order here! */
10142 j
= i
.opcode_length
;
10144 switch (i
.tm
.opcode_space
)
10159 if (now_seg
== absolute_section
)
10160 abs_section_offset
+= j
;
10163 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
10169 && i
.tm
.opcode_space
!= SPACE_BASE
)
10172 if (i
.tm
.opcode_space
!= SPACE_0F
)
10173 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
10177 switch (i
.opcode_length
)
10180 /* Put out high byte first: can't use md_number_to_chars! */
10181 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
10182 /* Fall through. */
10184 *p
= i
.tm
.base_opcode
& 0xff;
10193 /* Now the modrm byte and sib byte (if present). */
10194 if (i
.tm
.opcode_modifier
.modrm
)
10196 frag_opcode_byte ((i
.rm
.regmem
<< 0)
10198 | (i
.rm
.mode
<< 6));
10199 /* If i.rm.regmem == ESP (4)
10200 && i.rm.mode != (Register mode)
10202 ==> need second modrm byte. */
10203 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
10205 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
10206 frag_opcode_byte ((i
.sib
.base
<< 0)
10207 | (i
.sib
.index
<< 3)
10208 | (i
.sib
.scale
<< 6));
10211 if (i
.disp_operands
)
10212 output_disp (insn_start_frag
, insn_start_off
);
10214 if (i
.imm_operands
)
10215 output_imm (insn_start_frag
, insn_start_off
);
10218 * frag_now_fix () returning plain abs_section_offset when we're in the
10219 * absolute section, and abs_section_offset not getting updated as data
10220 * gets added to the frag breaks the logic below.
10222 if (now_seg
!= absolute_section
)
10224 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
10226 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
10230 /* NB: Don't add prefix with GOTPC relocation since
10231 output_disp() above depends on the fixed encoding
10232 length. Can't add prefix with TLS relocation since
10233 it breaks TLS linker optimization. */
10234 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
10235 /* Prefix count on the current instruction. */
10236 unsigned int count
= i
.vex
.length
;
10238 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
10239 /* REX byte is encoded in VEX/EVEX prefix. */
10240 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
10243 /* Count prefixes for extended opcode maps. */
10245 switch (i
.tm
.opcode_space
)
10260 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10263 /* Set the maximum prefix size in BRANCH_PREFIX
10265 if (fragP
->tc_frag_data
.max_bytes
> max
)
10266 fragP
->tc_frag_data
.max_bytes
= max
;
10267 if (fragP
->tc_frag_data
.max_bytes
> count
)
10268 fragP
->tc_frag_data
.max_bytes
-= count
;
10270 fragP
->tc_frag_data
.max_bytes
= 0;
10274 /* Remember the maximum prefix size in FUSED_JCC_PADDING
10276 unsigned int max_prefix_size
;
10277 if (align_branch_prefix_size
> max
)
10278 max_prefix_size
= max
;
10280 max_prefix_size
= align_branch_prefix_size
;
10281 if (max_prefix_size
> count
)
10282 fragP
->tc_frag_data
.max_prefix_length
10283 = max_prefix_size
- count
;
10286 /* Use existing segment prefix if possible. Use CS
10287 segment prefix in 64-bit mode. In 32-bit mode, use SS
10288 segment prefix with ESP/EBP base register and use DS
10289 segment prefix without ESP/EBP base register. */
10290 if (i
.prefix
[SEG_PREFIX
])
10291 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
10292 else if (flag_code
== CODE_64BIT
)
10293 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
10294 else if (i
.base_reg
10295 && (i
.base_reg
->reg_num
== 4
10296 || i
.base_reg
->reg_num
== 5))
10297 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
10299 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
10304 /* NB: Don't work with COND_JUMP86 without i386. */
10305 if (align_branch_power
10306 && now_seg
!= absolute_section
10307 && cpu_arch_flags
.bitfield
.cpui386
)
10309 /* Terminate each frag so that we can add prefix and check for
10311 frag_wane (frag_now
);
10318 pi ("" /*line*/, &i
);
10320 #endif /* DEBUG386 */
10323 /* Return the size of the displacement operand N. */
10326 disp_size (unsigned int n
)
10330 if (i
.types
[n
].bitfield
.disp64
)
10332 else if (i
.types
[n
].bitfield
.disp8
)
10334 else if (i
.types
[n
].bitfield
.disp16
)
10339 /* Return the size of the immediate operand N. */
10342 imm_size (unsigned int n
)
10345 if (i
.types
[n
].bitfield
.imm64
)
10347 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10349 else if (i
.types
[n
].bitfield
.imm16
)
10355 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10360 for (n
= 0; n
< i
.operands
; n
++)
10362 if (operand_type_check (i
.types
[n
], disp
))
10364 int size
= disp_size (n
);
10366 if (now_seg
== absolute_section
)
10367 abs_section_offset
+= size
;
10368 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10370 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10372 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10374 p
= frag_more (size
);
10375 md_number_to_chars (p
, val
, size
);
10379 enum bfd_reloc_code_real reloc_type
;
10380 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10381 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10382 && (!want_disp32 (&i
.tm
)
10383 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10384 && !i
.types
[n
].bitfield
.baseindex
)))
10388 /* We can't have 8 bit displacement here. */
10389 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10391 /* The PC relative address is computed relative
10392 to the instruction boundary, so in case immediate
10393 fields follows, we need to adjust the value. */
10394 if (pcrel
&& i
.imm_operands
)
10399 for (n1
= 0; n1
< i
.operands
; n1
++)
10400 if (operand_type_check (i
.types
[n1
], imm
))
10402 /* Only one immediate is allowed for PC
10403 relative address, except with .insn. */
10404 gas_assert (sz
== 0 || dot_insn ());
10405 sz
+= imm_size (n1
);
10407 /* We should find at least one immediate. */
10408 gas_assert (sz
!= 0);
10409 i
.op
[n
].disps
->X_add_number
-= sz
;
10412 p
= frag_more (size
);
10413 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10415 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10416 && (((reloc_type
== BFD_RELOC_32
10417 || reloc_type
== BFD_RELOC_X86_64_32S
10418 || (reloc_type
== BFD_RELOC_64
10420 && (i
.op
[n
].disps
->X_op
== O_symbol
10421 || (i
.op
[n
].disps
->X_op
== O_add
10422 && ((symbol_get_value_expression
10423 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10425 || reloc_type
== BFD_RELOC_32_PCREL
))
10429 reloc_type
= BFD_RELOC_386_GOTPC
;
10430 i
.has_gotpc_tls_reloc
= true;
10431 i
.op
[n
].disps
->X_add_number
+=
10432 encoding_length (insn_start_frag
, insn_start_off
, p
);
10434 else if (reloc_type
== BFD_RELOC_64
)
10435 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10437 /* Don't do the adjustment for x86-64, as there
10438 the pcrel addressing is relative to the _next_
10439 insn, and that is taken care of in other code. */
10440 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10442 else if (align_branch_power
)
10444 switch (reloc_type
)
10446 case BFD_RELOC_386_TLS_GD
:
10447 case BFD_RELOC_386_TLS_LDM
:
10448 case BFD_RELOC_386_TLS_IE
:
10449 case BFD_RELOC_386_TLS_IE_32
:
10450 case BFD_RELOC_386_TLS_GOTIE
:
10451 case BFD_RELOC_386_TLS_GOTDESC
:
10452 case BFD_RELOC_386_TLS_DESC_CALL
:
10453 case BFD_RELOC_X86_64_TLSGD
:
10454 case BFD_RELOC_X86_64_TLSLD
:
10455 case BFD_RELOC_X86_64_GOTTPOFF
:
10456 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10457 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10458 i
.has_gotpc_tls_reloc
= true;
10463 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10464 size
, i
.op
[n
].disps
, pcrel
,
10467 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10468 && !i
.prefix
[ADDR_PREFIX
])
10469 fixP
->fx_signed
= 1;
10471 /* Check for "call/jmp *mem", "mov mem, %reg",
10472 "test %reg, mem" and "binop mem, %reg" where binop
10473 is one of adc, add, and, cmp, or, sbb, sub, xor
10474 instructions without data prefix. Always generate
10475 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10476 if (i
.prefix
[DATA_PREFIX
] == 0
10477 && (generate_relax_relocations
10480 && i
.rm
.regmem
== 5))
10482 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10483 && i
.tm
.opcode_space
== SPACE_BASE
10484 && ((i
.operands
== 1
10485 && i
.tm
.base_opcode
== 0xff
10486 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10487 || (i
.operands
== 2
10488 && (i
.tm
.base_opcode
== 0x8b
10489 || i
.tm
.base_opcode
== 0x85
10490 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10494 fixP
->fx_tcbit
= i
.rex
!= 0;
10496 && (i
.base_reg
->reg_num
== RegIP
))
10497 fixP
->fx_tcbit2
= 1;
10500 fixP
->fx_tcbit2
= 1;
10508 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10513 for (n
= 0; n
< i
.operands
; n
++)
10515 if (operand_type_check (i
.types
[n
], imm
))
10517 int size
= imm_size (n
);
10519 if (now_seg
== absolute_section
)
10520 abs_section_offset
+= size
;
10521 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10525 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10527 p
= frag_more (size
);
10528 md_number_to_chars (p
, val
, size
);
10532 /* Not absolute_section.
10533 Need a 32-bit fixup (don't support 8bit
10534 non-absolute imms). Try to support other
10536 enum bfd_reloc_code_real reloc_type
;
10539 if (i
.types
[n
].bitfield
.imm32s
10540 && (i
.suffix
== QWORD_MNEM_SUFFIX
10541 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
10542 || (i
.prefix
[REX_PREFIX
] & REX_W
)
10548 p
= frag_more (size
);
10549 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10551 /* This is tough to explain. We end up with this one if we
10552 * have operands that look like
10553 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10554 * obtain the absolute address of the GOT, and it is strongly
10555 * preferable from a performance point of view to avoid using
10556 * a runtime relocation for this. The actual sequence of
10557 * instructions often look something like:
10562 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10564 * The call and pop essentially return the absolute address
10565 * of the label .L66 and store it in %ebx. The linker itself
10566 * will ultimately change the first operand of the addl so
10567 * that %ebx points to the GOT, but to keep things simple, the
10568 * .o file must have this operand set so that it generates not
10569 * the absolute address of .L66, but the absolute address of
10570 * itself. This allows the linker itself simply treat a GOTPC
10571 * relocation as asking for a pcrel offset to the GOT to be
10572 * added in, and the addend of the relocation is stored in the
10573 * operand field for the instruction itself.
10575 * Our job here is to fix the operand so that it would add
10576 * the correct offset so that %ebx would point to itself. The
10577 * thing that is tricky is that .-.L66 will point to the
10578 * beginning of the instruction, so we need to further modify
10579 * the operand so that it will point to itself. There are
10580 * other cases where you have something like:
10582 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10584 * and here no correction would be required. Internally in
10585 * the assembler we treat operands of this form as not being
10586 * pcrel since the '.' is explicitly mentioned, and I wonder
10587 * whether it would simplify matters to do it this way. Who
10588 * knows. In earlier versions of the PIC patches, the
10589 * pcrel_adjust field was used to store the correction, but
10590 * since the expression is not pcrel, I felt it would be
10591 * confusing to do it this way. */
10593 if ((reloc_type
== BFD_RELOC_32
10594 || reloc_type
== BFD_RELOC_X86_64_32S
10595 || reloc_type
== BFD_RELOC_64
)
10597 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10598 && (i
.op
[n
].imms
->X_op
== O_symbol
10599 || (i
.op
[n
].imms
->X_op
== O_add
10600 && ((symbol_get_value_expression
10601 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10605 reloc_type
= BFD_RELOC_386_GOTPC
;
10606 else if (size
== 4)
10607 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10608 else if (size
== 8)
10609 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10610 i
.has_gotpc_tls_reloc
= true;
10611 i
.op
[n
].imms
->X_add_number
+=
10612 encoding_length (insn_start_frag
, insn_start_off
, p
);
10614 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10615 i
.op
[n
].imms
, 0, reloc_type
);
10621 /* x86_cons_fix_new is called via the expression parsing code when a
10622 reloc is needed. We use this hook to get the correct .got reloc. */
10623 static int cons_sign
= -1;
10626 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10627 expressionS
*exp
, bfd_reloc_code_real_type r
)
10629 r
= reloc (len
, 0, cons_sign
, r
);
10632 if (exp
->X_op
== O_secrel
)
10634 exp
->X_op
= O_symbol
;
10635 r
= BFD_RELOC_32_SECREL
;
10637 else if (exp
->X_op
== O_secidx
)
10638 r
= BFD_RELOC_16_SECIDX
;
10641 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10644 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10645 purpose of the `.dc.a' internal pseudo-op. */
10648 x86_address_bytes (void)
10650 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10652 return stdoutput
->arch_info
->bits_per_address
/ 8;
10655 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10656 || defined (LEX_AT)) && !defined (TE_PE)
10657 # define lex_got(reloc, adjust, types) NULL
10659 /* Parse operands of the form
10660 <symbol>@GOTOFF+<nnn>
10661 and similar .plt or .got references.
10663 If we find one, set up the correct relocation in RELOC and copy the
10664 input string, minus the `@GOTOFF' into a malloc'd buffer for
10665 parsing by the calling routine. Return this buffer, and if ADJUST
10666 is non-null set it to the length of the string we removed from the
10667 input line. Otherwise return NULL. */
10669 lex_got (enum bfd_reloc_code_real
*rel
,
10671 i386_operand_type
*types
)
10673 /* Some of the relocations depend on the size of what field is to
10674 be relocated. But in our callers i386_immediate and i386_displacement
10675 we don't yet know the operand size (this will be set by insn
10676 matching). Hence we record the word32 relocation here,
10677 and adjust the reloc according to the real size in reloc(). */
10678 static const struct
10682 const enum bfd_reloc_code_real rel
[2];
10683 const i386_operand_type types64
;
10684 bool need_GOT_symbol
;
10689 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10690 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10691 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10692 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10693 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10694 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10695 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10696 { .imm64 = 1, .disp64 = 1 } }
10699 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10700 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10701 BFD_RELOC_SIZE32
},
10702 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10704 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10705 BFD_RELOC_X86_64_PLTOFF64
},
10706 { .bitfield
= { .imm64
= 1 } }, true },
10707 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10708 BFD_RELOC_X86_64_PLT32
},
10709 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10710 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10711 BFD_RELOC_X86_64_GOTPLT64
},
10712 OPERAND_TYPE_IMM64_DISP64
, true },
10713 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10714 BFD_RELOC_X86_64_GOTOFF64
},
10715 OPERAND_TYPE_IMM64_DISP64
, true },
10716 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10717 BFD_RELOC_X86_64_GOTPCREL
},
10718 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10719 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10720 BFD_RELOC_X86_64_TLSGD
},
10721 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10722 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10723 _dummy_first_bfd_reloc_code_real
},
10724 OPERAND_TYPE_NONE
, true },
10725 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10726 BFD_RELOC_X86_64_TLSLD
},
10727 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10728 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10729 BFD_RELOC_X86_64_GOTTPOFF
},
10730 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10731 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10732 BFD_RELOC_X86_64_TPOFF32
},
10733 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10734 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10735 _dummy_first_bfd_reloc_code_real
},
10736 OPERAND_TYPE_NONE
, true },
10737 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10738 BFD_RELOC_X86_64_DTPOFF32
},
10739 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10740 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10741 _dummy_first_bfd_reloc_code_real
},
10742 OPERAND_TYPE_NONE
, true },
10743 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10744 _dummy_first_bfd_reloc_code_real
},
10745 OPERAND_TYPE_NONE
, true },
10746 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10747 BFD_RELOC_X86_64_GOT32
},
10748 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10749 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10750 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10751 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10752 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10753 BFD_RELOC_X86_64_TLSDESC_CALL
},
10754 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10756 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10757 BFD_RELOC_32_SECREL
},
10758 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10761 #undef OPERAND_TYPE_IMM32_32S_DISP32
10762 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10763 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10764 #undef OPERAND_TYPE_IMM64_DISP64
10770 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10775 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10776 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10779 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10781 int len
= gotrel
[j
].len
;
10782 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10784 if (gotrel
[j
].rel
[object_64bit
] != 0)
10787 char *tmpbuf
, *past_reloc
;
10789 *rel
= gotrel
[j
].rel
[object_64bit
];
10793 if (flag_code
!= CODE_64BIT
)
10795 types
->bitfield
.imm32
= 1;
10796 types
->bitfield
.disp32
= 1;
10799 *types
= gotrel
[j
].types64
;
10802 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10803 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10805 /* The length of the first part of our input line. */
10806 first
= cp
- input_line_pointer
;
10808 /* The second part goes from after the reloc token until
10809 (and including) an end_of_line char or comma. */
10810 past_reloc
= cp
+ 1 + len
;
10812 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10814 second
= cp
+ 1 - past_reloc
;
10816 /* Allocate and copy string. The trailing NUL shouldn't
10817 be necessary, but be safe. */
10818 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10819 memcpy (tmpbuf
, input_line_pointer
, first
);
10820 if (second
!= 0 && *past_reloc
!= ' ')
10821 /* Replace the relocation token with ' ', so that
10822 errors like foo@GOTOFF1 will be detected. */
10823 tmpbuf
[first
++] = ' ';
10825 /* Increment length by 1 if the relocation token is
10830 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10831 tmpbuf
[first
+ second
] = '\0';
10835 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10836 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10841 /* Might be a symbol version string. Don't as_bad here. */
10846 bfd_reloc_code_real_type
10847 x86_cons (expressionS
*exp
, int size
)
10849 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10851 intel_syntax
= -intel_syntax
;
10853 expr_mode
= expr_operator_none
;
10855 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10856 && !defined (LEX_AT)) \
10858 if (size
== 4 || (object_64bit
&& size
== 8))
10860 /* Handle @GOTOFF and the like in an expression. */
10862 char *gotfree_input_line
;
10865 save
= input_line_pointer
;
10866 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10867 if (gotfree_input_line
)
10868 input_line_pointer
= gotfree_input_line
;
10872 if (gotfree_input_line
)
10874 /* expression () has merrily parsed up to the end of line,
10875 or a comma - in the wrong buffer. Transfer how far
10876 input_line_pointer has moved to the right buffer. */
10877 input_line_pointer
= (save
10878 + (input_line_pointer
- gotfree_input_line
)
10880 free (gotfree_input_line
);
10881 if (exp
->X_op
== O_constant
10882 || exp
->X_op
== O_absent
10883 || exp
->X_op
== O_illegal
10884 || exp
->X_op
== O_register
10885 || exp
->X_op
== O_big
)
10887 char c
= *input_line_pointer
;
10888 *input_line_pointer
= 0;
10889 as_bad (_("missing or invalid expression `%s'"), save
);
10890 *input_line_pointer
= c
;
10892 else if ((got_reloc
== BFD_RELOC_386_PLT32
10893 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10894 && exp
->X_op
!= O_symbol
)
10896 char c
= *input_line_pointer
;
10897 *input_line_pointer
= 0;
10898 as_bad (_("invalid PLT expression `%s'"), save
);
10899 *input_line_pointer
= c
;
10907 intel_syntax
= -intel_syntax
;
10910 i386_intel_simplify (exp
);
10912 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10913 if (size
<= 4 && expr_mode
== expr_operator_present
10914 && exp
->X_op
== O_constant
&& !object_64bit
)
10915 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10921 signed_cons (int size
)
10930 s_insn (int dummy ATTRIBUTE_UNUSED
)
10932 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
10933 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10937 bool vex
= false, xop
= false, evex
= false;
10938 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10942 saved_char
= *saved_ilp
;
10945 end
= parse_insn (line
, mnemonic
, true);
10949 *saved_ilp
= saved_char
;
10950 ignore_rest_of_line ();
10954 line
+= end
- line
;
10956 current_templates
= &tt
;
10957 i
.tm
.mnem_off
= MN__insn
;
10958 i
.tm
.extension_opcode
= None
;
10960 if (startswith (line
, "VEX")
10961 && (line
[3] == '.' || is_space_char (line
[3])))
10966 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10969 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10971 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10972 && (*e
== '.' || is_space_char (*e
)))
10975 /* Arrange for build_vex_prefix() to emit 0x8f. */
10976 i
.tm
.opcode_space
= SPACE_XOP08
;
10977 i
.insn_opcode_space
= n
;
10981 else if (startswith (line
, "EVEX")
10982 && (line
[4] == '.' || is_space_char (line
[4])))
10989 ? i
.vec_encoding
== vex_encoding_evex
10991 ? i
.vec_encoding
== vex_encoding_vex
10992 || i
.vec_encoding
== vex_encoding_vex3
10993 : i
.vec_encoding
!= vex_encoding_default
)
10995 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
10999 if (line
> end
&& i
.vec_encoding
== vex_encoding_default
)
11000 i
.vec_encoding
= evex
? vex_encoding_evex
: vex_encoding_vex
;
11002 if (i
.vec_encoding
!= vex_encoding_default
)
11004 /* Only address size and segment override prefixes are permitted with
11005 VEX/XOP/EVEX encodings. */
11006 const unsigned char *p
= i
.prefix
;
11008 for (j
= 0; j
< ARRAY_SIZE (i
.prefix
); ++j
, ++p
)
11019 as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
11025 if (line
> end
&& *line
== '.')
11027 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
11035 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11037 i
.tm
.opcode_modifier
.vex
= VEX128
;
11042 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11044 i
.tm
.opcode_modifier
.vex
= VEX256
;
11049 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11054 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
11058 if (line
[3] == 'G')
11061 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11063 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11069 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
11074 if (line
[2] == '2' && line
[3] == '8')
11077 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11079 i
.tm
.opcode_modifier
.vex
= VEX128
;
11085 if (line
[2] == '5' && line
[3] == '6')
11088 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11090 i
.tm
.opcode_modifier
.vex
= VEX256
;
11096 if (evex
&& line
[2] == '1' && line
[3] == '2')
11098 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11105 if (line
> end
&& *line
== '.')
11107 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
11111 if (line
[2] == 'P')
11116 if (line
[2] == '6')
11118 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
11123 case 'F': case 'f':
11124 if (line
[2] == '3')
11126 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
11129 else if (line
[2] == '2')
11131 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
11138 if (line
> end
&& !xop
&& *line
== '.')
11140 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
11144 if (TOUPPER (line
[2]) != 'F')
11146 if (line
[3] == '.' || is_space_char (line
[3]))
11148 i
.insn_opcode_space
= SPACE_0F
;
11151 else if (line
[3] == '3'
11152 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
11153 && (line
[5] == '.' || is_space_char (line
[5])))
11155 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
11161 if (ISDIGIT (line
[2]) && line
[2] != '0')
11164 unsigned long n
= strtoul (line
+ 2, &e
, 10);
11166 if (n
<= (evex
? 15 : 31)
11167 && (*e
== '.' || is_space_char (*e
)))
11169 i
.insn_opcode_space
= n
;
11177 if (line
> end
&& *line
== '.' && line
[1] == 'W')
11179 /* VEX.W, XOP.W, EVEX.W */
11183 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11187 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11191 if (line
[3] == 'G')
11193 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11199 if (i
.tm
.opcode_modifier
.vexw
)
11203 if (line
> end
&& *line
&& !is_space_char (*line
))
11205 /* Improve diagnostic a little. */
11206 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
11211 /* Before processing the opcode expression, find trailing "+r" or
11212 "/<digit>" specifiers. */
11213 for (ptr
= line
; ; ++ptr
)
11218 ptr
= strpbrk (ptr
, "+/,");
11219 if (ptr
== NULL
|| *ptr
== ',')
11222 if (*ptr
== '+' && ptr
[1] == 'r'
11223 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11227 i
.short_form
= true;
11231 if (*ptr
== '/' && ISDIGIT (ptr
[1])
11232 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
11234 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11238 i
.tm
.extension_opcode
= n
;
11239 i
.tm
.opcode_modifier
.modrm
= 1;
11244 input_line_pointer
= line
;
11245 val
= get_absolute_expression ();
11246 line
= input_line_pointer
;
11248 if (i
.short_form
&& (val
& 7))
11249 as_warn ("`+r' assumes low three opcode bits to be clear");
11251 for (j
= 1; j
< sizeof(val
); ++j
)
11252 if (!(val
>> (j
* 8)))
11255 /* Trim off a prefix if present. */
11256 if (j
> 1 && !vex
&& !xop
&& !evex
)
11258 uint8_t byte
= val
>> ((j
- 1) * 8);
11262 case DATA_PREFIX_OPCODE
:
11263 case REPE_PREFIX_OPCODE
:
11264 case REPNE_PREFIX_OPCODE
:
11265 if (!add_prefix (byte
))
11267 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
11272 /* Trim off encoding space. */
11273 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
11275 uint8_t byte
= val
>> ((--j
- 1) * 8);
11277 i
.insn_opcode_space
= SPACE_0F
;
11278 switch (byte
& -(j
> 1))
11281 i
.insn_opcode_space
= SPACE_0F38
;
11285 i
.insn_opcode_space
= SPACE_0F3A
;
11289 i
.tm
.opcode_space
= i
.insn_opcode_space
;
11290 val
&= ((uint64_t)1 << (j
* 8)) - 1;
11292 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
11293 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
11294 Also avoid hitting abort() there or in build_evex_prefix(). */
11295 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
11300 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
11303 i
.opcode_length
= j
;
11305 /* Handle operands, if any. */
11308 i386_operand_type combined
;
11309 expressionS
*disp_exp
= NULL
;
11314 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
11322 as_bad (_("expecting operand after ','; got nothing"));
11326 if (i
.mem_operands
> 1)
11328 as_bad (_("too many memory references for `%s'"),
11329 &i386_mnemonics
[MN__insn
]);
11333 /* No need to distinguish vex_encoding_evex and vex_encoding_evex512. */
11334 if (i
.vec_encoding
== vex_encoding_evex512
)
11335 i
.vec_encoding
= vex_encoding_evex
;
11337 /* Are we to emit ModR/M encoding? */
11340 || i
.reg_operands
> (i
.vec_encoding
!= vex_encoding_default
)
11341 || i
.tm
.extension_opcode
!= None
))
11342 i
.tm
.opcode_modifier
.modrm
= 1;
11344 if (!i
.tm
.opcode_modifier
.modrm
11346 > i
.short_form
+ 0U + (i
.vec_encoding
!= vex_encoding_default
)
11347 || i
.mem_operands
))
11349 as_bad (_("too many register/memory operands"));
11353 /* Enforce certain constraints on operands. */
11354 switch (i
.reg_operands
+ i
.mem_operands
11355 + (i
.tm
.extension_opcode
!= None
))
11360 as_bad (_("too few register/memory operands"));
11363 /* Fall through. */
11365 if (i
.tm
.opcode_modifier
.modrm
)
11367 as_bad (_("too few register/memory operands"));
11377 && (i
.op
[0].imms
->X_op
!= O_constant
11378 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
11380 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
11383 /* Fall through. */
11385 if (i
.vec_encoding
!= vex_encoding_default
)
11387 i
.tm
.opcode_modifier
.vexvvvv
= 1;
11390 /* Fall through. */
11392 as_bad (_("too many register/memory operands"));
11396 /* Bring operands into canonical order (imm, mem, reg). */
11401 for (j
= 1; j
< i
.operands
; ++j
)
11403 if ((!operand_type_check (i
.types
[j
- 1], imm
)
11404 && operand_type_check (i
.types
[j
], imm
))
11405 || (i
.types
[j
- 1].bitfield
.class != ClassNone
11406 && i
.types
[j
].bitfield
.class == ClassNone
))
11408 swap_2_operands (j
- 1, j
);
11415 /* For Intel syntax swap the order of register operands. */
11417 switch (i
.reg_operands
)
11424 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
11425 /* Fall through. */
11428 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
11435 /* Enforce constraints when using VSIB. */
11437 && (i
.index_reg
->reg_type
.bitfield
.xmmword
11438 || i
.index_reg
->reg_type
.bitfield
.ymmword
11439 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
11441 if (i
.vec_encoding
== vex_encoding_default
)
11443 as_bad (_("VSIB unavailable with legacy encoding"));
11447 if (i
.vec_encoding
== vex_encoding_evex
11448 && i
.reg_operands
> 1)
11450 /* We could allow two register operands, encoding the 2nd one in
11451 an 8-bit immediate like for 4-register-operand insns, but that
11452 would require ugly fiddling with process_operands() and/or
11453 build_modrm_byte(). */
11454 as_bad (_("too many register operands with VSIB"));
11458 i
.tm
.opcode_modifier
.sib
= 1;
11461 /* Establish operand size encoding. */
11462 operand_type_set (&combined
, 0);
11464 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
11466 i
.types
[j
].bitfield
.instance
= InstanceNone
;
11468 if (operand_type_check (i
.types
[j
], disp
))
11470 i
.types
[j
].bitfield
.baseindex
= 1;
11471 disp_exp
= i
.op
[j
].disps
;
11474 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
11476 unsigned int n
= i
.memshift
;
11478 if (i
.types
[j
].bitfield
.byte
)
11480 else if (i
.types
[j
].bitfield
.word
)
11482 else if (i
.types
[j
].bitfield
.dword
)
11484 else if (i
.types
[j
].bitfield
.qword
)
11486 else if (i
.types
[j
].bitfield
.xmmword
)
11488 else if (i
.types
[j
].bitfield
.ymmword
)
11490 else if (i
.types
[j
].bitfield
.zmmword
)
11493 if (i
.memshift
< 32 && n
!= i
.memshift
)
11494 as_warn ("conflicting memory operand size specifiers");
11498 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11499 && j
== i
.broadcast
.operand
)
11502 combined
= operand_type_or (combined
, i
.types
[j
]);
11503 combined
.bitfield
.class = ClassNone
;
11506 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
11507 << (i
.memshift
< 32 ? i
.memshift
: 0))
11509 case 64: combined
.bitfield
.zmmword
= 1; break;
11510 case 32: combined
.bitfield
.ymmword
= 1; break;
11511 case 16: combined
.bitfield
.xmmword
= 1; break;
11512 case 8: combined
.bitfield
.qword
= 1; break;
11513 case 4: combined
.bitfield
.dword
= 1; break;
11516 if (i
.vec_encoding
== vex_encoding_default
)
11518 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
11520 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
11521 : combined
.bitfield
.word
)
11522 && !add_prefix (DATA_PREFIX_OPCODE
))
11525 else if (!i
.tm
.opcode_modifier
.vexw
)
11527 if (flag_code
== CODE_64BIT
)
11529 if (combined
.bitfield
.qword
)
11530 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11531 else if (combined
.bitfield
.dword
)
11532 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11535 if (!i
.tm
.opcode_modifier
.vexw
)
11536 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11541 if (!i
.tm
.opcode_modifier
.vex
)
11543 if (combined
.bitfield
.ymmword
)
11544 i
.tm
.opcode_modifier
.vex
= VEX256
;
11545 else if (combined
.bitfield
.xmmword
)
11546 i
.tm
.opcode_modifier
.vex
= VEX128
;
11551 if (!i
.tm
.opcode_modifier
.evex
)
11553 /* Do _not_ consider AVX512VL here. */
11554 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
11555 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11556 else if (combined
.bitfield
.ymmword
)
11557 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11558 else if (combined
.bitfield
.xmmword
)
11559 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11562 if (i
.memshift
>= 32)
11564 unsigned int n
= 0;
11566 switch (i
.tm
.opcode_modifier
.evex
)
11568 case EVEX512
: n
= 64; break;
11569 case EVEX256
: n
= 32; break;
11570 case EVEX128
: n
= 16; break;
11573 if (i
.broadcast
.type
)
11574 n
/= i
.broadcast
.type
;
11577 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11579 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
11580 && disp_exp
->X_add_number
!= 0
11581 && i
.disp_encoding
!= disp_encoding_32bit
)
11583 if (!quiet_warnings
)
11584 as_warn ("cannot determine memory operand size");
11585 i
.disp_encoding
= disp_encoding_32bit
;
11590 if (i
.memshift
>= 32)
11593 i
.vec_encoding
= vex_encoding_error
;
11595 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
11598 /* Establish size for immediate operands. */
11599 for (j
= 0; j
< i
.imm_operands
; ++j
)
11601 expressionS
*expP
= i
.op
[j
].imms
;
11603 gas_assert (operand_type_check (i
.types
[j
], imm
));
11604 operand_type_set (&i
.types
[j
], 0);
11606 if (i
.imm_bits
[j
] > 32)
11607 i
.types
[j
].bitfield
.imm64
= 1;
11608 else if (i
.imm_bits
[j
] > 16)
11610 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
11611 i
.types
[j
].bitfield
.imm32s
= 1;
11613 i
.types
[j
].bitfield
.imm32
= 1;
11615 else if (i
.imm_bits
[j
] > 8)
11616 i
.types
[j
].bitfield
.imm16
= 1;
11617 else if (i
.imm_bits
[j
] > 0)
11619 if (i
.flags
[j
] & Operand_Signed
)
11620 i
.types
[j
].bitfield
.imm8s
= 1;
11622 i
.types
[j
].bitfield
.imm8
= 1;
11624 else if (expP
->X_op
== O_constant
)
11626 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
11627 i
.types
[j
].bitfield
.imm1
= 0;
11628 /* Oddly enough imm_size() checks imm64 first, so the bit needs
11629 zapping since smallest_imm_type() sets it unconditionally. */
11630 if (flag_code
!= CODE_64BIT
)
11632 i
.types
[j
].bitfield
.imm64
= 0;
11633 i
.types
[j
].bitfield
.imm32s
= 0;
11634 i
.types
[j
].bitfield
.imm32
= 1;
11636 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
11637 i
.types
[j
].bitfield
.imm64
= 0;
11640 /* Non-constant expressions are sized heuristically. */
11643 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
11644 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
11645 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
11649 for (j
= 0; j
< i
.operands
; ++j
)
11650 i
.tm
.operand_types
[j
] = i
.types
[j
];
11652 process_operands ();
11655 /* Don't set opcode until after processing operands, to avoid any
11656 potential special casing there. */
11657 i
.tm
.base_opcode
|= val
;
11659 if (i
.vec_encoding
== vex_encoding_error
11660 || (i
.vec_encoding
!= vex_encoding_evex
11661 ? i
.broadcast
.type
|| i
.broadcast
.bytes
11662 || i
.rounding
.type
!= rc_none
11664 : (i
.mem_operands
&& i
.rounding
.type
!= rc_none
)
11665 || ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11666 && !(i
.flags
[i
.broadcast
.operand
] & Operand_Mem
))))
11668 as_bad (_("conflicting .insn operands"));
11674 if (!i
.tm
.opcode_modifier
.vex
)
11675 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11677 build_vex_prefix (NULL
);
11678 i
.rex
&= REX_OPCODE
;
11682 if (!i
.tm
.opcode_modifier
.evex
)
11683 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11685 build_evex_prefix ();
11686 i
.rex
&= REX_OPCODE
;
11688 else if (i
.rex
!= 0)
11689 add_prefix (REX_OPCODE
| i
.rex
);
11694 *saved_ilp
= saved_char
;
11695 input_line_pointer
= line
;
11697 demand_empty_rest_of_line ();
11699 /* Make sure dot_insn() won't yield "true" anymore. */
11705 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
11712 if (exp
.X_op
== O_symbol
)
11713 exp
.X_op
= O_secrel
;
11715 emit_expr (&exp
, 4);
11717 while (*input_line_pointer
++ == ',');
11719 input_line_pointer
--;
11720 demand_empty_rest_of_line ();
11724 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
11731 if (exp
.X_op
== O_symbol
)
11732 exp
.X_op
= O_secidx
;
11734 emit_expr (&exp
, 2);
11736 while (*input_line_pointer
++ == ',');
11738 input_line_pointer
--;
11739 demand_empty_rest_of_line ();
11743 /* Handle Rounding Control / SAE specifiers. */
11746 RC_SAE_specifier (const char *pstr
)
11750 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11752 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11754 if (i
.rounding
.type
!= rc_none
)
11756 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
11760 if (i
.vec_encoding
== vex_encoding_default
)
11761 i
.vec_encoding
= vex_encoding_evex512
;
11762 else if (i
.vec_encoding
!= vex_encoding_evex
11763 && i
.vec_encoding
!= vex_encoding_evex512
)
11766 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11768 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
11775 /* Handle Vector operations. */
11778 check_VecOperations (char *op_string
)
11780 const reg_entry
*mask
;
11787 if (*op_string
== '{')
11791 /* Check broadcasts. */
11792 if (startswith (op_string
, "1to"))
11794 unsigned int bcst_type
;
11796 if (i
.broadcast
.type
)
11797 goto duplicated_vec_op
;
11800 if (*op_string
== '8')
11802 else if (*op_string
== '4')
11804 else if (*op_string
== '2')
11806 else if (*op_string
== '1'
11807 && *(op_string
+1) == '6')
11812 else if (*op_string
== '3'
11813 && *(op_string
+1) == '2')
11820 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11825 if (i
.vec_encoding
== vex_encoding_default
)
11826 i
.vec_encoding
= vex_encoding_evex
;
11827 else if (i
.vec_encoding
!= vex_encoding_evex
11828 && i
.vec_encoding
!= vex_encoding_evex512
)
11829 goto unknown_vec_op
;
11831 i
.broadcast
.type
= bcst_type
;
11832 i
.broadcast
.operand
= this_operand
;
11834 /* For .insn a data size specifier may be appended. */
11835 if (dot_insn () && *op_string
== ':')
11836 goto dot_insn_modifier
;
11838 /* Check .insn special cases. */
11839 else if (dot_insn () && *op_string
== ':')
11842 switch (op_string
[1])
11847 if (i
.memshift
< 32)
11848 goto duplicated_vec_op
;
11850 n
= strtoul (op_string
+ 2, &end_op
, 0);
11852 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11854 if (i
.memshift
< 32 && n
== 1)
11855 op_string
= end_op
;
11858 case 's': case 'u':
11859 /* This isn't really a "vector" operation, but a sign/size
11860 specifier for immediate operands of .insn. Note that AT&T
11861 syntax handles the same in i386_immediate(). */
11865 if (i
.imm_bits
[this_operand
])
11866 goto duplicated_vec_op
;
11868 n
= strtoul (op_string
+ 2, &end_op
, 0);
11869 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11871 i
.imm_bits
[this_operand
] = n
;
11872 if (op_string
[1] == 's')
11873 i
.flags
[this_operand
] |= Operand_Signed
;
11874 op_string
= end_op
;
11879 /* Check masking operation. */
11880 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11882 if (mask
== &bad_reg
)
11885 /* k0 can't be used for write mask. */
11886 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11888 as_bad (_("`%s%s' can't be used for write mask"),
11889 register_prefix
, mask
->reg_name
);
11896 i
.mask
.operand
= this_operand
;
11898 else if (i
.mask
.reg
->reg_num
)
11899 goto duplicated_vec_op
;
11904 /* Only "{z}" is allowed here. No need to check
11905 zeroing mask explicitly. */
11906 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11908 as_bad (_("invalid write mask `%s'"), saved
);
11913 op_string
= end_op
;
11915 /* Check zeroing-flag for masking operation. */
11916 else if (*op_string
== 'z')
11920 i
.mask
.reg
= reg_k0
;
11921 i
.mask
.zeroing
= 1;
11922 i
.mask
.operand
= this_operand
;
11926 if (i
.mask
.zeroing
)
11929 as_bad (_("duplicated `%s'"), saved
);
11933 i
.mask
.zeroing
= 1;
11935 /* Only "{%k}" is allowed here. No need to check mask
11936 register explicitly. */
11937 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11939 as_bad (_("invalid zeroing-masking `%s'"),
11947 else if (intel_syntax
11948 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11949 i
.rounding
.modifier
= true;
11951 goto unknown_vec_op
;
11953 if (*op_string
!= '}')
11955 as_bad (_("missing `}' in `%s'"), saved
);
11960 /* Strip whitespace since the addition of pseudo prefixes
11961 changed how the scrubber treats '{'. */
11962 if (is_space_char (*op_string
))
11968 /* We don't know this one. */
11969 as_bad (_("unknown vector operation: `%s'"), saved
);
11973 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11975 as_bad (_("zeroing-masking only allowed with write mask"));
11983 i386_immediate (char *imm_start
)
11985 char *save_input_line_pointer
;
11986 char *gotfree_input_line
;
11989 i386_operand_type types
;
11991 operand_type_set (&types
, ~0);
11993 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
11995 as_bad (_("at most %d immediate operands are allowed"),
11996 MAX_IMMEDIATE_OPERANDS
);
12000 exp
= &im_expressions
[i
.imm_operands
++];
12001 i
.op
[this_operand
].imms
= exp
;
12003 if (is_space_char (*imm_start
))
12006 save_input_line_pointer
= input_line_pointer
;
12007 input_line_pointer
= imm_start
;
12009 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12010 if (gotfree_input_line
)
12011 input_line_pointer
= gotfree_input_line
;
12013 expr_mode
= expr_operator_none
;
12014 exp_seg
= expression (exp
);
12016 /* For .insn immediates there may be a size specifier. */
12017 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
12018 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
12021 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
12023 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
12025 i
.imm_bits
[this_operand
] = n
;
12026 if (input_line_pointer
[2] == 's')
12027 i
.flags
[this_operand
] |= Operand_Signed
;
12028 input_line_pointer
= e
+ 1;
12032 SKIP_WHITESPACE ();
12033 if (*input_line_pointer
)
12034 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12036 input_line_pointer
= save_input_line_pointer
;
12037 if (gotfree_input_line
)
12039 free (gotfree_input_line
);
12041 if (exp
->X_op
== O_constant
)
12042 exp
->X_op
= O_illegal
;
12045 if (exp_seg
== reg_section
)
12047 as_bad (_("illegal immediate register operand %s"), imm_start
);
12051 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
12055 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12056 i386_operand_type types
, const char *imm_start
)
12058 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
12061 as_bad (_("missing or invalid immediate expression `%s'"),
12065 else if (exp
->X_op
== O_constant
)
12067 /* Size it properly later. */
12068 i
.types
[this_operand
].bitfield
.imm64
= 1;
12070 /* If not 64bit, sign/zero extend val, to account for wraparound
12072 if (expr_mode
== expr_operator_present
12073 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12074 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12076 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12077 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12078 && exp_seg
!= absolute_section
12079 && exp_seg
!= text_section
12080 && exp_seg
!= data_section
12081 && exp_seg
!= bss_section
12082 && exp_seg
!= undefined_section
12083 && !bfd_is_com_section (exp_seg
))
12085 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12091 /* This is an address. The size of the address will be
12092 determined later, depending on destination register,
12093 suffix, or the default for the section. */
12094 i
.types
[this_operand
].bitfield
.imm8
= 1;
12095 i
.types
[this_operand
].bitfield
.imm16
= 1;
12096 i
.types
[this_operand
].bitfield
.imm32
= 1;
12097 i
.types
[this_operand
].bitfield
.imm32s
= 1;
12098 i
.types
[this_operand
].bitfield
.imm64
= 1;
12099 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
12107 i386_scale (char *scale
)
12110 char *save
= input_line_pointer
;
12112 input_line_pointer
= scale
;
12113 val
= get_absolute_expression ();
12118 i
.log2_scale_factor
= 0;
12121 i
.log2_scale_factor
= 1;
12124 i
.log2_scale_factor
= 2;
12127 i
.log2_scale_factor
= 3;
12131 char sep
= *input_line_pointer
;
12133 *input_line_pointer
= '\0';
12134 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
12136 *input_line_pointer
= sep
;
12137 input_line_pointer
= save
;
12141 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
12143 as_warn (_("scale factor of %d without an index register"),
12144 1 << i
.log2_scale_factor
);
12145 i
.log2_scale_factor
= 0;
12147 scale
= input_line_pointer
;
12148 input_line_pointer
= save
;
12153 i386_displacement (char *disp_start
, char *disp_end
)
12157 char *save_input_line_pointer
;
12158 char *gotfree_input_line
;
12160 i386_operand_type bigdisp
, types
= anydisp
;
12163 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
12165 as_bad (_("at most %d displacement operands are allowed"),
12166 MAX_MEMORY_OPERANDS
);
12170 operand_type_set (&bigdisp
, 0);
12172 || i
.types
[this_operand
].bitfield
.baseindex
12173 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
12174 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
12176 i386_addressing_mode ();
12177 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
12178 if (flag_code
== CODE_64BIT
)
12180 bigdisp
.bitfield
.disp32
= 1;
12182 bigdisp
.bitfield
.disp64
= 1;
12184 else if ((flag_code
== CODE_16BIT
) ^ override
)
12185 bigdisp
.bitfield
.disp16
= 1;
12187 bigdisp
.bitfield
.disp32
= 1;
12191 /* For PC-relative branches, the width of the displacement may be
12192 dependent upon data size, but is never dependent upon address size.
12193 Also make sure to not unintentionally match against a non-PC-relative
12194 branch template. */
12195 static templates aux_templates
;
12196 const insn_template
*t
= current_templates
->start
;
12197 bool has_intel64
= false;
12199 aux_templates
.start
= t
;
12200 while (++t
< current_templates
->end
)
12202 if (t
->opcode_modifier
.jump
12203 != current_templates
->start
->opcode_modifier
.jump
)
12205 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
12206 has_intel64
= true;
12208 if (t
< current_templates
->end
)
12210 aux_templates
.end
= t
;
12211 current_templates
= &aux_templates
;
12214 override
= (i
.prefix
[DATA_PREFIX
] != 0);
12215 if (flag_code
== CODE_64BIT
)
12217 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
12218 && (!intel64
|| !has_intel64
))
12219 bigdisp
.bitfield
.disp16
= 1;
12221 bigdisp
.bitfield
.disp32
= 1;
12226 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
12228 : LONG_MNEM_SUFFIX
));
12229 bigdisp
.bitfield
.disp32
= 1;
12230 if ((flag_code
== CODE_16BIT
) ^ override
)
12232 bigdisp
.bitfield
.disp32
= 0;
12233 bigdisp
.bitfield
.disp16
= 1;
12237 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12240 exp
= &disp_expressions
[i
.disp_operands
];
12241 i
.op
[this_operand
].disps
= exp
;
12243 save_input_line_pointer
= input_line_pointer
;
12244 input_line_pointer
= disp_start
;
12245 END_STRING_AND_SAVE (disp_end
);
12247 #ifndef GCC_ASM_O_HACK
12248 #define GCC_ASM_O_HACK 0
12251 END_STRING_AND_SAVE (disp_end
+ 1);
12252 if (i
.types
[this_operand
].bitfield
.baseIndex
12253 && displacement_string_end
[-1] == '+')
12255 /* This hack is to avoid a warning when using the "o"
12256 constraint within gcc asm statements.
12259 #define _set_tssldt_desc(n,addr,limit,type) \
12260 __asm__ __volatile__ ( \
12261 "movw %w2,%0\n\t" \
12262 "movw %w1,2+%0\n\t" \
12263 "rorl $16,%1\n\t" \
12264 "movb %b1,4+%0\n\t" \
12265 "movb %4,5+%0\n\t" \
12266 "movb $0,6+%0\n\t" \
12267 "movb %h1,7+%0\n\t" \
12269 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
12271 This works great except that the output assembler ends
12272 up looking a bit weird if it turns out that there is
12273 no offset. You end up producing code that looks like:
12286 So here we provide the missing zero. */
12288 *displacement_string_end
= '0';
12291 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12292 if (gotfree_input_line
)
12293 input_line_pointer
= gotfree_input_line
;
12295 expr_mode
= expr_operator_none
;
12296 exp_seg
= expression (exp
);
12298 SKIP_WHITESPACE ();
12299 if (*input_line_pointer
)
12300 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12302 RESTORE_END_STRING (disp_end
+ 1);
12304 input_line_pointer
= save_input_line_pointer
;
12305 if (gotfree_input_line
)
12307 free (gotfree_input_line
);
12309 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
12310 exp
->X_op
= O_illegal
;
12313 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
12315 RESTORE_END_STRING (disp_end
);
12321 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12322 i386_operand_type types
, const char *disp_start
)
12326 /* We do this to make sure that the section symbol is in
12327 the symbol table. We will ultimately change the relocation
12328 to be relative to the beginning of the section. */
12329 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
12330 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
12331 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12333 if (exp
->X_op
!= O_symbol
)
12336 if (S_IS_LOCAL (exp
->X_add_symbol
)
12337 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
12338 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
12339 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
12340 exp
->X_op
= O_subtract
;
12341 exp
->X_op_symbol
= GOT_symbol
;
12342 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
12343 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
12344 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12345 i
.reloc
[this_operand
] = BFD_RELOC_64
;
12347 i
.reloc
[this_operand
] = BFD_RELOC_32
;
12350 else if (exp
->X_op
== O_absent
12351 || exp
->X_op
== O_illegal
12352 || exp
->X_op
== O_big
)
12355 as_bad (_("missing or invalid displacement expression `%s'"),
12360 else if (exp
->X_op
== O_constant
)
12362 /* Sizing gets taken care of by optimize_disp().
12364 If not 64bit, sign/zero extend val, to account for wraparound
12366 if (expr_mode
== expr_operator_present
12367 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12368 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12371 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12372 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12373 && exp_seg
!= absolute_section
12374 && exp_seg
!= text_section
12375 && exp_seg
!= data_section
12376 && exp_seg
!= bss_section
12377 && exp_seg
!= undefined_section
12378 && !bfd_is_com_section (exp_seg
))
12380 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12385 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
12386 i
.types
[this_operand
].bitfield
.disp8
= 1;
12388 /* Check if this is a displacement only operand. */
12389 if (!i
.types
[this_operand
].bitfield
.baseindex
)
12390 i
.types
[this_operand
] =
12391 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
12392 operand_type_and (i
.types
[this_operand
], types
));
12397 /* Return the active addressing mode, taking address override and
12398 registers forming the address into consideration. Update the
12399 address override prefix if necessary. */
12401 static enum flag_code
12402 i386_addressing_mode (void)
12404 enum flag_code addr_mode
;
12406 if (i
.prefix
[ADDR_PREFIX
])
12407 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
12408 else if (flag_code
== CODE_16BIT
12409 && is_cpu (current_templates
->start
, CpuMPX
)
12410 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
12411 from md_assemble() by "is not a valid base/index expression"
12412 when there is a base and/or index. */
12413 && !i
.types
[this_operand
].bitfield
.baseindex
)
12415 /* MPX insn memory operands with neither base nor index must be forced
12416 to use 32-bit addressing in 16-bit mode. */
12417 addr_mode
= CODE_32BIT
;
12418 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12420 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
12421 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
12425 addr_mode
= flag_code
;
12427 #if INFER_ADDR_PREFIX
12428 if (i
.mem_operands
== 0)
12430 /* Infer address prefix from the first memory operand. */
12431 const reg_entry
*addr_reg
= i
.base_reg
;
12433 if (addr_reg
== NULL
)
12434 addr_reg
= i
.index_reg
;
12438 if (addr_reg
->reg_type
.bitfield
.dword
)
12439 addr_mode
= CODE_32BIT
;
12440 else if (flag_code
!= CODE_64BIT
12441 && addr_reg
->reg_type
.bitfield
.word
)
12442 addr_mode
= CODE_16BIT
;
12444 if (addr_mode
!= flag_code
)
12446 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12448 /* Change the size of any displacement too. At most one
12449 of Disp16 or Disp32 is set.
12450 FIXME. There doesn't seem to be any real need for
12451 separate Disp16 and Disp32 flags. The same goes for
12452 Imm16 and Imm32. Removing them would probably clean
12453 up the code quite a lot. */
12454 if (flag_code
!= CODE_64BIT
12455 && (i
.types
[this_operand
].bitfield
.disp16
12456 || i
.types
[this_operand
].bitfield
.disp32
))
12458 static const i386_operand_type disp16_32
= {
12459 .bitfield
= { .disp16
= 1, .disp32
= 1 }
12462 i
.types
[this_operand
]
12463 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
12474 /* Make sure the memory operand we've been dealt is valid.
12475 Return 1 on success, 0 on a failure. */
12478 i386_index_check (const char *operand_string
)
12480 const char *kind
= "base/index";
12481 enum flag_code addr_mode
= i386_addressing_mode ();
12482 const insn_template
*t
= current_templates
->end
- 1;
12484 if (t
->opcode_modifier
.isstring
)
12486 /* Memory operands of string insns are special in that they only allow
12487 a single register (rDI, rSI, or rBX) as their memory address. */
12488 const reg_entry
*expected_reg
;
12489 static const char di_si
[][2][4] =
12495 static const char bx
[][4] = { "ebx", "bx", "rbx" };
12497 kind
= "string address";
12499 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
12501 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
12504 if (!t
->operand_types
[0].bitfield
.baseindex
12505 || ((!i
.mem_operands
!= !intel_syntax
)
12506 && t
->operand_types
[1].bitfield
.baseindex
))
12509 = (const reg_entry
*) str_hash_find (reg_hash
,
12510 di_si
[addr_mode
][op
== es_op
]);
12514 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
12516 if (i
.base_reg
!= expected_reg
12518 || operand_type_check (i
.types
[this_operand
], disp
))
12520 /* The second memory operand must have the same size as
12524 && !((addr_mode
== CODE_64BIT
12525 && i
.base_reg
->reg_type
.bitfield
.qword
)
12526 || (addr_mode
== CODE_32BIT
12527 ? i
.base_reg
->reg_type
.bitfield
.dword
12528 : i
.base_reg
->reg_type
.bitfield
.word
)))
12531 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
12533 intel_syntax
? '[' : '(',
12535 expected_reg
->reg_name
,
12536 intel_syntax
? ']' : ')');
12543 as_bad (_("`%s' is not a valid %s expression"),
12544 operand_string
, kind
);
12549 t
= current_templates
->start
;
12551 if (addr_mode
!= CODE_16BIT
)
12553 /* 32-bit/64-bit checks. */
12554 if (i
.disp_encoding
== disp_encoding_16bit
)
12557 as_bad (_("invalid `%s' prefix"),
12558 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
12563 && ((addr_mode
== CODE_64BIT
12564 ? !i
.base_reg
->reg_type
.bitfield
.qword
12565 : !i
.base_reg
->reg_type
.bitfield
.dword
)
12566 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
12567 || i
.base_reg
->reg_num
== RegIZ
))
12569 && !i
.index_reg
->reg_type
.bitfield
.xmmword
12570 && !i
.index_reg
->reg_type
.bitfield
.ymmword
12571 && !i
.index_reg
->reg_type
.bitfield
.zmmword
12572 && ((addr_mode
== CODE_64BIT
12573 ? !i
.index_reg
->reg_type
.bitfield
.qword
12574 : !i
.index_reg
->reg_type
.bitfield
.dword
)
12575 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
12578 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
12579 if (t
->mnem_off
== MN_bndmk
12580 || t
->mnem_off
== MN_bndldx
12581 || t
->mnem_off
== MN_bndstx
12582 || t
->opcode_modifier
.sib
== SIBMEM
)
12584 /* They cannot use RIP-relative addressing. */
12585 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12587 as_bad (_("`%s' cannot be used here"), operand_string
);
12591 /* bndldx and bndstx ignore their scale factor. */
12592 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
12593 && i
.log2_scale_factor
)
12594 as_warn (_("register scaling is being ignored here"));
12599 /* 16-bit checks. */
12600 if (i
.disp_encoding
== disp_encoding_32bit
)
12604 && (!i
.base_reg
->reg_type
.bitfield
.word
12605 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
12607 && (!i
.index_reg
->reg_type
.bitfield
.word
12608 || !i
.index_reg
->reg_type
.bitfield
.baseindex
12610 && i
.base_reg
->reg_num
< 6
12611 && i
.index_reg
->reg_num
>= 6
12612 && i
.log2_scale_factor
== 0))))
12619 /* Handle vector immediates. */
12622 RC_SAE_immediate (const char *imm_start
)
12624 const char *pstr
= imm_start
;
12629 pstr
= RC_SAE_specifier (pstr
+ 1);
12633 if (*pstr
++ != '}')
12635 as_bad (_("Missing '}': '%s'"), imm_start
);
12638 /* RC/SAE immediate string should contain nothing more. */;
12641 as_bad (_("Junk after '}': '%s'"), imm_start
);
12645 /* Internally this doesn't count as an operand. */
12651 static INLINE
bool starts_memory_operand (char c
)
12654 || is_name_beginner (c
)
12655 || strchr ("([\"+-!~", c
);
12658 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
12662 i386_att_operand (char *operand_string
)
12664 const reg_entry
*r
;
12666 char *op_string
= operand_string
;
12668 if (is_space_char (*op_string
))
12671 /* We check for an absolute prefix (differentiating,
12672 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
12673 if (*op_string
== ABSOLUTE_PREFIX
12674 && current_templates
->start
->opcode_modifier
.jump
)
12677 if (is_space_char (*op_string
))
12679 i
.jumpabsolute
= true;
12682 /* Check if operand is a register. */
12683 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
12685 i386_operand_type temp
;
12690 /* Check for a segment override by searching for ':' after a
12691 segment register. */
12692 op_string
= end_op
;
12693 if (is_space_char (*op_string
))
12695 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
12697 i
.seg
[i
.mem_operands
] = r
;
12699 /* Skip the ':' and whitespace. */
12701 if (is_space_char (*op_string
))
12704 /* Handle case of %es:*foo. */
12705 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
12706 && current_templates
->start
->opcode_modifier
.jump
)
12709 if (is_space_char (*op_string
))
12711 i
.jumpabsolute
= true;
12714 if (!starts_memory_operand (*op_string
))
12716 as_bad (_("bad memory operand `%s'"), op_string
);
12719 goto do_memory_reference
;
12722 /* Handle vector operations. */
12723 if (*op_string
== '{')
12725 op_string
= check_VecOperations (op_string
);
12726 if (op_string
== NULL
)
12732 as_bad (_("junk `%s' after register"), op_string
);
12736 /* Reject pseudo registers for .insn. */
12737 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
12739 as_bad (_("`%s%s' cannot be used here"),
12740 register_prefix
, r
->reg_name
);
12744 temp
= r
->reg_type
;
12745 temp
.bitfield
.baseindex
= 0;
12746 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12748 i
.types
[this_operand
].bitfield
.unspecified
= 0;
12749 i
.op
[this_operand
].regs
= r
;
12752 /* A GPR may follow an RC or SAE immediate only if a (vector) register
12753 operand was also present earlier on. */
12754 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
12755 && i
.reg_operands
== 1)
12759 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
12760 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
12762 as_bad (_("`%s': misplaced `{%s}'"),
12763 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
12767 else if (*op_string
== REGISTER_PREFIX
)
12769 as_bad (_("bad register name `%s'"), op_string
);
12772 else if (*op_string
== IMMEDIATE_PREFIX
)
12775 if (i
.jumpabsolute
)
12777 as_bad (_("immediate operand illegal with absolute jump"));
12780 if (!i386_immediate (op_string
))
12782 if (i
.rounding
.type
!= rc_none
)
12784 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
12785 insn_name (current_templates
->start
));
12789 else if (RC_SAE_immediate (operand_string
))
12791 /* If it is a RC or SAE immediate, do the necessary placement check:
12792 Only another immediate or a GPR may precede it. */
12793 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
12794 || (i
.reg_operands
== 1
12795 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
12797 as_bad (_("`%s': misplaced `%s'"),
12798 insn_name (current_templates
->start
), operand_string
);
12802 else if (starts_memory_operand (*op_string
))
12804 /* This is a memory reference of some sort. */
12807 /* Start and end of displacement string expression (if found). */
12808 char *displacement_string_start
;
12809 char *displacement_string_end
;
12811 do_memory_reference
:
12812 /* Check for base index form. We detect the base index form by
12813 looking for an ')' at the end of the operand, searching
12814 for the '(' matching it, and finding a REGISTER_PREFIX or ','
12816 base_string
= op_string
+ strlen (op_string
);
12818 /* Handle vector operations. */
12820 if (is_space_char (*base_string
))
12823 if (*base_string
== '}')
12825 char *vop_start
= NULL
;
12827 while (base_string
-- > op_string
)
12829 if (*base_string
== '"')
12831 if (*base_string
!= '{')
12834 vop_start
= base_string
;
12837 if (is_space_char (*base_string
))
12840 if (*base_string
!= '}')
12848 as_bad (_("unbalanced figure braces"));
12852 if (check_VecOperations (vop_start
) == NULL
)
12856 /* If we only have a displacement, set-up for it to be parsed later. */
12857 displacement_string_start
= op_string
;
12858 displacement_string_end
= base_string
+ 1;
12860 if (*base_string
== ')')
12863 unsigned int parens_not_balanced
= 0;
12864 bool in_quotes
= false;
12866 /* We've already checked that the number of left & right ()'s are
12867 equal, and that there's a matching set of double quotes. */
12868 end_op
= base_string
;
12869 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
12871 if (*temp_string
== '\\' && temp_string
[1] == '"')
12873 else if (*temp_string
== '"')
12874 in_quotes
= !in_quotes
;
12875 else if (!in_quotes
)
12877 if (*temp_string
== '(' && !parens_not_balanced
++)
12878 base_string
= temp_string
;
12879 if (*temp_string
== ')')
12880 --parens_not_balanced
;
12884 temp_string
= base_string
;
12886 /* Skip past '(' and whitespace. */
12887 gas_assert (*base_string
== '(');
12889 if (is_space_char (*base_string
))
12892 if (*base_string
== ','
12893 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12896 displacement_string_end
= temp_string
;
12898 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12902 if (i
.base_reg
== &bad_reg
)
12904 base_string
= end_op
;
12905 if (is_space_char (*base_string
))
12909 /* There may be an index reg or scale factor here. */
12910 if (*base_string
== ',')
12913 if (is_space_char (*base_string
))
12916 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12919 if (i
.index_reg
== &bad_reg
)
12921 base_string
= end_op
;
12922 if (is_space_char (*base_string
))
12924 if (*base_string
== ',')
12927 if (is_space_char (*base_string
))
12930 else if (*base_string
!= ')')
12932 as_bad (_("expecting `,' or `)' "
12933 "after index register in `%s'"),
12938 else if (*base_string
== REGISTER_PREFIX
)
12940 end_op
= strchr (base_string
, ',');
12943 as_bad (_("bad register name `%s'"), base_string
);
12947 /* Check for scale factor. */
12948 if (*base_string
!= ')')
12950 char *end_scale
= i386_scale (base_string
);
12955 base_string
= end_scale
;
12956 if (is_space_char (*base_string
))
12958 if (*base_string
!= ')')
12960 as_bad (_("expecting `)' "
12961 "after scale factor in `%s'"),
12966 else if (!i
.index_reg
)
12968 as_bad (_("expecting index register or scale factor "
12969 "after `,'; got '%c'"),
12974 else if (*base_string
!= ')')
12976 as_bad (_("expecting `,' or `)' "
12977 "after base register in `%s'"),
12982 else if (*base_string
== REGISTER_PREFIX
)
12984 end_op
= strchr (base_string
, ',');
12987 as_bad (_("bad register name `%s'"), base_string
);
12992 /* If there's an expression beginning the operand, parse it,
12993 assuming displacement_string_start and
12994 displacement_string_end are meaningful. */
12995 if (displacement_string_start
!= displacement_string_end
)
12997 if (!i386_displacement (displacement_string_start
,
12998 displacement_string_end
))
13002 /* Special case for (%dx) while doing input/output op. */
13004 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
13005 && i
.base_reg
->reg_type
.bitfield
.word
13006 && i
.index_reg
== 0
13007 && i
.log2_scale_factor
== 0
13008 && i
.seg
[i
.mem_operands
] == 0
13009 && !operand_type_check (i
.types
[this_operand
], disp
))
13011 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
13012 i
.input_output_operand
= true;
13016 if (i386_index_check (operand_string
) == 0)
13018 i
.flags
[this_operand
] |= Operand_Mem
;
13023 /* It's not a memory operand; argh! */
13024 as_bad (_("invalid char %s beginning operand %d `%s'"),
13025 output_invalid (*op_string
),
13030 return 1; /* Normal return. */
13033 /* Calculate the maximum variable size (i.e., excluding fr_fix)
13034 that an rs_machine_dependent frag may reach. */
13037 i386_frag_max_var (fragS
*frag
)
13039 /* The only relaxable frags are for jumps.
13040 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
13041 gas_assert (frag
->fr_type
== rs_machine_dependent
);
13042 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
13045 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13047 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
13049 /* STT_GNU_IFUNC symbol must go through PLT. */
13050 if ((symbol_get_bfdsym (fr_symbol
)->flags
13051 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
13054 if (!S_IS_EXTERNAL (fr_symbol
))
13055 /* Symbol may be weak or local. */
13056 return !S_IS_WEAK (fr_symbol
);
13058 /* Global symbols with non-default visibility can't be preempted. */
13059 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
13062 if (fr_var
!= NO_RELOC
)
13063 switch ((enum bfd_reloc_code_real
) fr_var
)
13065 case BFD_RELOC_386_PLT32
:
13066 case BFD_RELOC_X86_64_PLT32
:
13067 /* Symbol with PLT relocation may be preempted. */
13073 /* Global symbols with default visibility in a shared library may be
13074 preempted by another definition. */
13079 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
13080 Note also work for Skylake and Cascadelake.
13081 ---------------------------------------------------------------------
13082 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
13083 | ------ | ----------- | ------- | -------- |
13085 | Jno | N | N | Y |
13086 | Jc/Jb | Y | N | Y |
13087 | Jae/Jnb | Y | N | Y |
13088 | Je/Jz | Y | Y | Y |
13089 | Jne/Jnz | Y | Y | Y |
13090 | Jna/Jbe | Y | N | Y |
13091 | Ja/Jnbe | Y | N | Y |
13093 | Jns | N | N | Y |
13094 | Jp/Jpe | N | N | Y |
13095 | Jnp/Jpo | N | N | Y |
13096 | Jl/Jnge | Y | Y | Y |
13097 | Jge/Jnl | Y | Y | Y |
13098 | Jle/Jng | Y | Y | Y |
13099 | Jg/Jnle | Y | Y | Y |
13100 --------------------------------------------------------------------- */
13102 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
13104 if (mf_cmp
== mf_cmp_alu_cmp
)
13105 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
13106 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
13107 if (mf_cmp
== mf_cmp_incdec
)
13108 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
13109 || mf_jcc
== mf_jcc_jle
);
13110 if (mf_cmp
== mf_cmp_test_and
)
13115 /* Return the next non-empty frag. */
13118 i386_next_non_empty_frag (fragS
*fragP
)
13120 /* There may be a frag with a ".fill 0" when there is no room in
13121 the current frag for frag_grow in output_insn. */
13122 for (fragP
= fragP
->fr_next
;
13124 && fragP
->fr_type
== rs_fill
13125 && fragP
->fr_fix
== 0);
13126 fragP
= fragP
->fr_next
)
13131 /* Return the next jcc frag after BRANCH_PADDING. */
13134 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
13136 fragS
*branch_fragP
;
13140 if (pad_fragP
->fr_type
== rs_machine_dependent
13141 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
13142 == BRANCH_PADDING
))
13144 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
13145 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
13147 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
13148 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
13149 pad_fragP
->tc_frag_data
.mf_type
))
13150 return branch_fragP
;
13156 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
13159 i386_classify_machine_dependent_frag (fragS
*fragP
)
13163 fragS
*branch_fragP
;
13165 unsigned int max_prefix_length
;
13167 if (fragP
->tc_frag_data
.classified
)
13170 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
13171 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
13172 for (next_fragP
= fragP
;
13173 next_fragP
!= NULL
;
13174 next_fragP
= next_fragP
->fr_next
)
13176 next_fragP
->tc_frag_data
.classified
= 1;
13177 if (next_fragP
->fr_type
== rs_machine_dependent
)
13178 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
13180 case BRANCH_PADDING
:
13181 /* The BRANCH_PADDING frag must be followed by a branch
13183 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
13184 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13186 case FUSED_JCC_PADDING
:
13187 /* Check if this is a fused jcc:
13189 CMP like instruction
13193 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
13194 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
13195 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
13198 /* The BRANCH_PADDING frag is merged with the
13199 FUSED_JCC_PADDING frag. */
13200 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13201 /* CMP like instruction size. */
13202 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
13203 frag_wane (pad_fragP
);
13204 /* Skip to branch_fragP. */
13205 next_fragP
= branch_fragP
;
13207 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
13209 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
13211 next_fragP
->fr_subtype
13212 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
13213 next_fragP
->tc_frag_data
.max_bytes
13214 = next_fragP
->tc_frag_data
.max_prefix_length
;
13215 /* This will be updated in the BRANCH_PREFIX scan. */
13216 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
13219 frag_wane (next_fragP
);
13224 /* Stop if there is no BRANCH_PREFIX. */
13225 if (!align_branch_prefix_size
)
13228 /* Scan for BRANCH_PREFIX. */
13229 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
13231 if (fragP
->fr_type
!= rs_machine_dependent
13232 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13236 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
13237 COND_JUMP_PREFIX. */
13238 max_prefix_length
= 0;
13239 for (next_fragP
= fragP
;
13240 next_fragP
!= NULL
;
13241 next_fragP
= next_fragP
->fr_next
)
13243 if (next_fragP
->fr_type
== rs_fill
)
13244 /* Skip rs_fill frags. */
13246 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
13247 /* Stop for all other frags. */
13250 /* rs_machine_dependent frags. */
13251 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13254 /* Count BRANCH_PREFIX frags. */
13255 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
13257 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
13258 frag_wane (next_fragP
);
13262 += next_fragP
->tc_frag_data
.max_bytes
;
13264 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13266 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13267 == FUSED_JCC_PADDING
))
13269 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
13270 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
13274 /* Stop for other rs_machine_dependent frags. */
13278 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
13280 /* Skip to the next frag. */
13281 fragP
= next_fragP
;
13285 /* Compute padding size for
13288 CMP like instruction
13290 COND_JUMP/UNCOND_JUMP
13295 COND_JUMP/UNCOND_JUMP
13299 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
13301 unsigned int offset
, size
, padding_size
;
13302 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
13304 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
13306 address
= fragP
->fr_address
;
13307 address
+= fragP
->fr_fix
;
13309 /* CMP like instrunction size. */
13310 size
= fragP
->tc_frag_data
.cmp_size
;
13312 /* The base size of the branch frag. */
13313 size
+= branch_fragP
->fr_fix
;
13315 /* Add opcode and displacement bytes for the rs_machine_dependent
13317 if (branch_fragP
->fr_type
== rs_machine_dependent
)
13318 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
13320 /* Check if branch is within boundary and doesn't end at the last
13322 offset
= address
& ((1U << align_branch_power
) - 1);
13323 if ((offset
+ size
) >= (1U << align_branch_power
))
13324 /* Padding needed to avoid crossing boundary. */
13325 padding_size
= (1U << align_branch_power
) - offset
;
13327 /* No padding needed. */
13330 /* The return value may be saved in tc_frag_data.length which is
13332 if (!fits_in_unsigned_byte (padding_size
))
13335 return padding_size
;
13338 /* i386_generic_table_relax_frag()
13340 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
13341 grow/shrink padding to align branch frags. Hand others to
13345 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
13347 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13348 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13350 long padding_size
= i386_branch_padding_size (fragP
, 0);
13351 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
13353 /* When the BRANCH_PREFIX frag is used, the computed address
13354 must match the actual address and there should be no padding. */
13355 if (fragP
->tc_frag_data
.padding_address
13356 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
13360 /* Update the padding size. */
13362 fragP
->tc_frag_data
.length
= padding_size
;
13366 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13368 fragS
*padding_fragP
, *next_fragP
;
13369 long padding_size
, left_size
, last_size
;
13371 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13372 if (!padding_fragP
)
13373 /* Use the padding set by the leading BRANCH_PREFIX frag. */
13374 return (fragP
->tc_frag_data
.length
13375 - fragP
->tc_frag_data
.last_length
);
13377 /* Compute the relative address of the padding frag in the very
13378 first time where the BRANCH_PREFIX frag sizes are zero. */
13379 if (!fragP
->tc_frag_data
.padding_address
)
13380 fragP
->tc_frag_data
.padding_address
13381 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
13383 /* First update the last length from the previous interation. */
13384 left_size
= fragP
->tc_frag_data
.prefix_length
;
13385 for (next_fragP
= fragP
;
13386 next_fragP
!= padding_fragP
;
13387 next_fragP
= next_fragP
->fr_next
)
13388 if (next_fragP
->fr_type
== rs_machine_dependent
13389 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13394 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13398 if (max
> left_size
)
13403 next_fragP
->tc_frag_data
.last_length
= size
;
13407 next_fragP
->tc_frag_data
.last_length
= 0;
13410 /* Check the padding size for the padding frag. */
13411 padding_size
= i386_branch_padding_size
13412 (padding_fragP
, (fragP
->fr_address
13413 + fragP
->tc_frag_data
.padding_address
));
13415 last_size
= fragP
->tc_frag_data
.prefix_length
;
13416 /* Check if there is change from the last interation. */
13417 if (padding_size
== last_size
)
13419 /* Update the expected address of the padding frag. */
13420 padding_fragP
->tc_frag_data
.padding_address
13421 = (fragP
->fr_address
+ padding_size
13422 + fragP
->tc_frag_data
.padding_address
);
13426 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
13428 /* No padding if there is no sufficient room. Clear the
13429 expected address of the padding frag. */
13430 padding_fragP
->tc_frag_data
.padding_address
= 0;
13434 /* Store the expected address of the padding frag. */
13435 padding_fragP
->tc_frag_data
.padding_address
13436 = (fragP
->fr_address
+ padding_size
13437 + fragP
->tc_frag_data
.padding_address
);
13439 fragP
->tc_frag_data
.prefix_length
= padding_size
;
13441 /* Update the length for the current interation. */
13442 left_size
= padding_size
;
13443 for (next_fragP
= fragP
;
13444 next_fragP
!= padding_fragP
;
13445 next_fragP
= next_fragP
->fr_next
)
13446 if (next_fragP
->fr_type
== rs_machine_dependent
13447 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13452 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13456 if (max
> left_size
)
13461 next_fragP
->tc_frag_data
.length
= size
;
13465 next_fragP
->tc_frag_data
.length
= 0;
13468 return (fragP
->tc_frag_data
.length
13469 - fragP
->tc_frag_data
.last_length
);
13471 return relax_frag (segment
, fragP
, stretch
);
13474 /* md_estimate_size_before_relax()
13476 Called just before relax() for rs_machine_dependent frags. The x86
13477 assembler uses these frags to handle variable size jump
13480 Any symbol that is now undefined will not become defined.
13481 Return the correct fr_subtype in the frag.
13482 Return the initial "guess for variable size of frag" to caller.
13483 The guess is actually the growth beyond the fixed part. Whatever
13484 we do to grow the fixed or variable part contributes to our
13488 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
13490 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13491 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
13492 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13494 i386_classify_machine_dependent_frag (fragP
);
13495 return fragP
->tc_frag_data
.length
;
13498 /* We've already got fragP->fr_subtype right; all we have to do is
13499 check for un-relaxable symbols. On an ELF system, we can't relax
13500 an externally visible symbol, because it may be overridden by a
13502 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
13503 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13505 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
13508 #if defined (OBJ_COFF) && defined (TE_PE)
13509 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
13510 && S_IS_WEAK (fragP
->fr_symbol
))
13514 /* Symbol is undefined in this segment, or we need to keep a
13515 reloc so that weak symbols can be overridden. */
13516 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
13517 enum bfd_reloc_code_real reloc_type
;
13518 unsigned char *opcode
;
13522 if (fragP
->fr_var
!= NO_RELOC
)
13523 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
13524 else if (size
== 2)
13525 reloc_type
= BFD_RELOC_16_PCREL
;
13526 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13527 else if (fragP
->tc_frag_data
.code
== CODE_64BIT
13528 && fragP
->fr_offset
== 0
13529 && need_plt32_p (fragP
->fr_symbol
))
13530 reloc_type
= BFD_RELOC_X86_64_PLT32
;
13533 reloc_type
= BFD_RELOC_32_PCREL
;
13535 old_fr_fix
= fragP
->fr_fix
;
13536 opcode
= (unsigned char *) fragP
->fr_opcode
;
13538 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
13541 /* Make jmp (0xeb) a (d)word displacement jump. */
13543 fragP
->fr_fix
+= size
;
13544 fixP
= fix_new (fragP
, old_fr_fix
, size
,
13546 fragP
->fr_offset
, 1,
13552 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
13554 /* Negate the condition, and branch past an
13555 unconditional jump. */
13558 /* Insert an unconditional jump. */
13560 /* We added two extra opcode bytes, and have a two byte
13562 fragP
->fr_fix
+= 2 + 2;
13563 fix_new (fragP
, old_fr_fix
+ 2, 2,
13565 fragP
->fr_offset
, 1,
13569 /* Fall through. */
13572 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
13574 fragP
->fr_fix
+= 1;
13575 fixP
= fix_new (fragP
, old_fr_fix
, 1,
13577 fragP
->fr_offset
, 1,
13578 BFD_RELOC_8_PCREL
);
13579 fixP
->fx_signed
= 1;
13583 /* This changes the byte-displacement jump 0x7N
13584 to the (d)word-displacement jump 0x0f,0x8N. */
13585 opcode
[1] = opcode
[0] + 0x10;
13586 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13587 /* We've added an opcode byte. */
13588 fragP
->fr_fix
+= 1 + size
;
13589 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
13591 fragP
->fr_offset
, 1,
13596 BAD_CASE (fragP
->fr_subtype
);
13600 /* All jumps handled here are signed, but don't unconditionally use a
13601 signed limit check for 32 and 16 bit jumps as we want to allow wrap
13602 around at 4G (outside of 64-bit mode) and 64k. */
13603 if (size
== 4 && flag_code
== CODE_64BIT
)
13604 fixP
->fx_signed
= 1;
13607 return fragP
->fr_fix
- old_fr_fix
;
13610 /* Guess size depending on current relax state. Initially the relax
13611 state will correspond to a short jump and we return 1, because
13612 the variable part of the frag (the branch offset) is one byte
13613 long. However, we can relax a section more than once and in that
13614 case we must either set fr_subtype back to the unrelaxed state,
13615 or return the value for the appropriate branch. */
13616 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
13619 /* Called after relax() is finished.
13621 In: Address of frag.
13622 fr_type == rs_machine_dependent.
13623 fr_subtype is what the address relaxed to.
13625 Out: Any fixSs and constants are set up.
13626 Caller will turn frag into a ".space 0". */
13629 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
13632 unsigned char *opcode
;
13633 unsigned char *where_to_put_displacement
= NULL
;
13634 offsetT target_address
;
13635 offsetT opcode_address
;
13636 unsigned int extension
= 0;
13637 offsetT displacement_from_opcode_start
;
13639 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13640 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
13641 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13643 /* Generate nop padding. */
13644 unsigned int size
= fragP
->tc_frag_data
.length
;
13647 if (size
> fragP
->tc_frag_data
.max_bytes
)
13653 const char *branch
= "branch";
13654 const char *prefix
= "";
13655 fragS
*padding_fragP
;
13656 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13659 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13660 switch (fragP
->tc_frag_data
.default_prefix
)
13665 case CS_PREFIX_OPCODE
:
13668 case DS_PREFIX_OPCODE
:
13671 case ES_PREFIX_OPCODE
:
13674 case FS_PREFIX_OPCODE
:
13677 case GS_PREFIX_OPCODE
:
13680 case SS_PREFIX_OPCODE
:
13685 msg
= _("%s:%u: add %d%s at 0x%llx to align "
13686 "%s within %d-byte boundary\n");
13688 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
13689 "align %s within %d-byte boundary\n");
13693 padding_fragP
= fragP
;
13694 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
13695 "%s within %d-byte boundary\n");
13699 switch (padding_fragP
->tc_frag_data
.branch_type
)
13701 case align_branch_jcc
:
13704 case align_branch_fused
:
13705 branch
= "fused jcc";
13707 case align_branch_jmp
:
13710 case align_branch_call
:
13713 case align_branch_indirect
:
13714 branch
= "indiret branch";
13716 case align_branch_ret
:
13723 fprintf (stdout
, msg
,
13724 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
13725 (long long) fragP
->fr_address
, branch
,
13726 1 << align_branch_power
);
13728 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13729 memset (fragP
->fr_opcode
,
13730 fragP
->tc_frag_data
.default_prefix
, size
);
13732 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
13734 fragP
->fr_fix
+= size
;
13739 opcode
= (unsigned char *) fragP
->fr_opcode
;
13741 /* Address we want to reach in file space. */
13742 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
13744 /* Address opcode resides at in file space. */
13745 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
13747 /* Displacement from opcode start to fill into instruction. */
13748 displacement_from_opcode_start
= target_address
- opcode_address
;
13750 if ((fragP
->fr_subtype
& BIG
) == 0)
13752 /* Don't have to change opcode. */
13753 extension
= 1; /* 1 opcode + 1 displacement */
13754 where_to_put_displacement
= &opcode
[1];
13758 if (no_cond_jump_promotion
13759 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
13760 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
13761 _("long jump required"));
13763 switch (fragP
->fr_subtype
)
13765 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
13766 extension
= 4; /* 1 opcode + 4 displacement */
13768 where_to_put_displacement
= &opcode
[1];
13771 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
13772 extension
= 2; /* 1 opcode + 2 displacement */
13774 where_to_put_displacement
= &opcode
[1];
13777 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
13778 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
13779 extension
= 5; /* 2 opcode + 4 displacement */
13780 opcode
[1] = opcode
[0] + 0x10;
13781 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13782 where_to_put_displacement
= &opcode
[2];
13785 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
13786 extension
= 3; /* 2 opcode + 2 displacement */
13787 opcode
[1] = opcode
[0] + 0x10;
13788 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13789 where_to_put_displacement
= &opcode
[2];
13792 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
13797 where_to_put_displacement
= &opcode
[3];
13801 BAD_CASE (fragP
->fr_subtype
);
13806 /* If size if less then four we are sure that the operand fits,
13807 but if it's 4, then it could be that the displacement is larger
13809 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
13811 && ((addressT
) (displacement_from_opcode_start
- extension
13812 + ((addressT
) 1 << 31))
13813 > (((addressT
) 2 << 31) - 1)))
13815 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
13816 _("jump target out of range"));
13817 /* Make us emit 0. */
13818 displacement_from_opcode_start
= extension
;
13820 /* Now put displacement after opcode. */
13821 md_number_to_chars ((char *) where_to_put_displacement
,
13822 (valueT
) (displacement_from_opcode_start
- extension
),
13823 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
13824 fragP
->fr_fix
+= extension
;
13827 /* Apply a fixup (fixP) to segment data, once it has been determined
13828 by our caller that we have all the info we need to fix it up.
13830 Parameter valP is the pointer to the value of the bits.
13832 On the 386, immediates, displacements, and data pointers are all in
13833 the same (little-endian) format, so we don't need to care about which
13834 we are handling. */
13837 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13839 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
13840 valueT value
= *valP
;
13842 #if !defined (TE_Mach)
13843 if (fixP
->fx_pcrel
)
13845 switch (fixP
->fx_r_type
)
13851 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
13854 case BFD_RELOC_X86_64_32S
:
13855 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
13858 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
13861 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
13866 if (fixP
->fx_addsy
!= NULL
13867 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
13868 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
13869 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
13870 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
13871 && !use_rela_relocations
)
13873 /* This is a hack. There should be a better way to handle this.
13874 This covers for the fact that bfd_install_relocation will
13875 subtract the current location (for partial_inplace, PC relative
13876 relocations); see more below. */
13880 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
13883 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13885 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13888 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
13890 if ((sym_seg
== seg
13891 || (symbol_section_p (fixP
->fx_addsy
)
13892 && sym_seg
!= absolute_section
))
13893 && !generic_force_reloc (fixP
))
13895 /* Yes, we add the values in twice. This is because
13896 bfd_install_relocation subtracts them out again. I think
13897 bfd_install_relocation is broken, but I don't dare change
13899 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13903 #if defined (OBJ_COFF) && defined (TE_PE)
13904 /* For some reason, the PE format does not store a
13905 section address offset for a PC relative symbol. */
13906 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13907 || S_IS_WEAK (fixP
->fx_addsy
))
13908 value
+= md_pcrel_from (fixP
);
13911 #if defined (OBJ_COFF) && defined (TE_PE)
13912 if (fixP
->fx_addsy
!= NULL
13913 && S_IS_WEAK (fixP
->fx_addsy
)
13914 /* PR 16858: Do not modify weak function references. */
13915 && ! fixP
->fx_pcrel
)
13917 #if !defined (TE_PEP)
13918 /* For x86 PE weak function symbols are neither PC-relative
13919 nor do they set S_IS_FUNCTION. So the only reliable way
13920 to detect them is to check the flags of their containing
13922 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13923 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13927 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13931 /* Fix a few things - the dynamic linker expects certain values here,
13932 and we must not disappoint it. */
13933 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13934 if (IS_ELF
&& fixP
->fx_addsy
)
13935 switch (fixP
->fx_r_type
)
13937 case BFD_RELOC_386_PLT32
:
13938 case BFD_RELOC_X86_64_PLT32
:
13939 /* Make the jump instruction point to the address of the operand.
13940 At runtime we merely add the offset to the actual PLT entry.
13941 NB: Subtract the offset size only for jump instructions. */
13942 if (fixP
->fx_pcrel
)
13946 case BFD_RELOC_386_TLS_GD
:
13947 case BFD_RELOC_386_TLS_LDM
:
13948 case BFD_RELOC_386_TLS_IE_32
:
13949 case BFD_RELOC_386_TLS_IE
:
13950 case BFD_RELOC_386_TLS_GOTIE
:
13951 case BFD_RELOC_386_TLS_GOTDESC
:
13952 case BFD_RELOC_X86_64_TLSGD
:
13953 case BFD_RELOC_X86_64_TLSLD
:
13954 case BFD_RELOC_X86_64_GOTTPOFF
:
13955 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13956 value
= 0; /* Fully resolved at runtime. No addend. */
13958 case BFD_RELOC_386_TLS_LE
:
13959 case BFD_RELOC_386_TLS_LDO_32
:
13960 case BFD_RELOC_386_TLS_LE_32
:
13961 case BFD_RELOC_X86_64_DTPOFF32
:
13962 case BFD_RELOC_X86_64_DTPOFF64
:
13963 case BFD_RELOC_X86_64_TPOFF32
:
13964 case BFD_RELOC_X86_64_TPOFF64
:
13965 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13968 case BFD_RELOC_386_TLS_DESC_CALL
:
13969 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13970 value
= 0; /* Fully resolved at runtime. No addend. */
13971 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13975 case BFD_RELOC_VTABLE_INHERIT
:
13976 case BFD_RELOC_VTABLE_ENTRY
:
13983 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13985 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13987 value
= extend_to_32bit_address (value
);
13990 #endif /* !defined (TE_Mach) */
13992 /* Are we finished with this relocation now? */
13993 if (fixP
->fx_addsy
== NULL
)
13996 switch (fixP
->fx_r_type
)
13998 case BFD_RELOC_X86_64_32S
:
13999 fixP
->fx_signed
= 1;
14006 #if defined (OBJ_COFF) && defined (TE_PE)
14007 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
14010 /* Remember value for tc_gen_reloc. */
14011 fixP
->fx_addnumber
= value
;
14012 /* Clear out the frag for now. */
14016 else if (use_rela_relocations
)
14018 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
14019 fixP
->fx_no_overflow
= 1;
14020 /* Remember value for tc_gen_reloc. */
14021 fixP
->fx_addnumber
= value
;
14025 md_number_to_chars (p
, value
, fixP
->fx_size
);
14029 md_atof (int type
, char *litP
, int *sizeP
)
14031 /* This outputs the LITTLENUMs in REVERSE order;
14032 in accord with the bigendian 386. */
14033 return ieee_md_atof (type
, litP
, sizeP
, false);
14036 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
14039 output_invalid (int c
)
14042 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14045 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14046 "(0x%x)", (unsigned char) c
);
14047 return output_invalid_buf
;
14050 /* Verify that @r can be used in the current context. */
14052 static bool check_register (const reg_entry
*r
)
14054 if (allow_pseudo_reg
)
14057 if (operand_type_all_zero (&r
->reg_type
))
14060 if ((r
->reg_type
.bitfield
.dword
14061 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
14062 || r
->reg_type
.bitfield
.class == RegCR
14063 || r
->reg_type
.bitfield
.class == RegDR
)
14064 && !cpu_arch_flags
.bitfield
.cpui386
)
14067 if (r
->reg_type
.bitfield
.class == RegTR
14068 && (flag_code
== CODE_64BIT
14069 || !cpu_arch_flags
.bitfield
.cpui386
14070 || cpu_arch_isa_flags
.bitfield
.cpui586
14071 || cpu_arch_isa_flags
.bitfield
.cpui686
))
14074 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
14077 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
14079 if (r
->reg_type
.bitfield
.zmmword
14080 || r
->reg_type
.bitfield
.class == RegMask
)
14083 if (!cpu_arch_flags
.bitfield
.cpuavx
)
14085 if (r
->reg_type
.bitfield
.ymmword
)
14088 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
14093 if (r
->reg_type
.bitfield
.zmmword
)
14095 if (vector_size
< VSZ512
)
14098 if (i
.vec_encoding
== vex_encoding_default
)
14099 i
.vec_encoding
= vex_encoding_evex512
;
14100 else if (i
.vec_encoding
!= vex_encoding_evex
14101 && i
.vec_encoding
!= vex_encoding_evex512
)
14102 i
.vec_encoding
= vex_encoding_error
;
14105 if (vector_size
< VSZ256
&& r
->reg_type
.bitfield
.ymmword
)
14108 if (r
->reg_type
.bitfield
.tmmword
14109 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
14110 || flag_code
!= CODE_64BIT
))
14113 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
14116 /* Don't allow fake index register unless allow_index_reg isn't 0. */
14117 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
14120 /* Upper 16 vector registers are only available with VREX in 64bit
14121 mode, and require EVEX encoding. */
14122 if (r
->reg_flags
& RegVRex
)
14124 if (!cpu_arch_flags
.bitfield
.cpuavx512f
14125 || flag_code
!= CODE_64BIT
)
14128 if (i
.vec_encoding
== vex_encoding_default
14129 || i
.vec_encoding
== vex_encoding_evex512
)
14130 i
.vec_encoding
= vex_encoding_evex
;
14131 else if (i
.vec_encoding
!= vex_encoding_evex
)
14132 i
.vec_encoding
= vex_encoding_error
;
14135 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
14136 && (!cpu_arch_flags
.bitfield
.cpu64
14137 || r
->reg_type
.bitfield
.class != RegCR
14139 && flag_code
!= CODE_64BIT
)
14142 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
14149 /* REG_STRING starts *before* REGISTER_PREFIX. */
14151 static const reg_entry
*
14152 parse_real_register (const char *reg_string
, char **end_op
)
14154 const char *s
= reg_string
;
14156 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
14157 const reg_entry
*r
;
14159 /* Skip possible REGISTER_PREFIX and possible whitespace. */
14160 if (*s
== REGISTER_PREFIX
)
14163 if (is_space_char (*s
))
14166 p
= reg_name_given
;
14167 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
14169 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
14170 return (const reg_entry
*) NULL
;
14174 if (is_part_of_name (*s
))
14175 return (const reg_entry
*) NULL
;
14177 *end_op
= (char *) s
;
14179 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
14181 /* Handle floating point regs, allowing spaces in the (i) part. */
14184 if (!cpu_arch_flags
.bitfield
.cpu8087
14185 && !cpu_arch_flags
.bitfield
.cpu287
14186 && !cpu_arch_flags
.bitfield
.cpu387
14187 && !allow_pseudo_reg
)
14188 return (const reg_entry
*) NULL
;
14190 if (is_space_char (*s
))
14195 if (is_space_char (*s
))
14197 if (*s
>= '0' && *s
<= '7')
14199 int fpr
= *s
- '0';
14201 if (is_space_char (*s
))
14205 *end_op
= (char *) s
+ 1;
14206 know (r
[fpr
].reg_num
== fpr
);
14210 /* We have "%st(" then garbage. */
14211 return (const reg_entry
*) NULL
;
14215 return r
&& check_register (r
) ? r
: NULL
;
14218 /* REG_STRING starts *before* REGISTER_PREFIX. */
14220 static const reg_entry
*
14221 parse_register (const char *reg_string
, char **end_op
)
14223 const reg_entry
*r
;
14225 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
14226 r
= parse_real_register (reg_string
, end_op
);
14231 char *save
= input_line_pointer
;
14232 char *buf
= xstrdup (reg_string
), *name
;
14235 input_line_pointer
= buf
;
14236 get_symbol_name (&name
);
14237 symbolP
= symbol_find (name
);
14238 while (symbolP
&& symbol_equated_p (symbolP
))
14240 const expressionS
*e
= symbol_get_value_expression(symbolP
);
14242 if (e
->X_add_number
)
14244 symbolP
= e
->X_add_symbol
;
14246 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
14248 const expressionS
*e
= symbol_get_value_expression (symbolP
);
14250 if (e
->X_op
== O_register
)
14252 know (e
->X_add_number
>= 0
14253 && (valueT
) e
->X_add_number
< i386_regtab_size
);
14254 r
= i386_regtab
+ e
->X_add_number
;
14255 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
14257 if (r
&& !check_register (r
))
14259 as_bad (_("register '%s%s' cannot be used here"),
14260 register_prefix
, r
->reg_name
);
14264 input_line_pointer
= save
;
14271 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
14273 const reg_entry
*r
= NULL
;
14274 char *end
= input_line_pointer
;
14276 /* We only know the terminating character here. It being double quote could
14277 be the closing one of a quoted symbol name, or an opening one from a
14278 following string (or another quoted symbol name). Since the latter can't
14279 be valid syntax for anything, bailing in either case is good enough. */
14280 if (*nextcharP
== '"')
14284 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
14285 r
= parse_real_register (name
, &input_line_pointer
);
14286 if (r
&& end
<= input_line_pointer
)
14288 *nextcharP
= *input_line_pointer
;
14289 *input_line_pointer
= 0;
14290 e
->X_op
= O_register
;
14291 e
->X_add_number
= r
- i386_regtab
;
14294 input_line_pointer
= end
;
14296 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
14300 md_operand (expressionS
*e
)
14303 const reg_entry
*r
;
14305 switch (*input_line_pointer
)
14307 case REGISTER_PREFIX
:
14308 r
= parse_real_register (input_line_pointer
, &end
);
14311 e
->X_op
= O_register
;
14312 e
->X_add_number
= r
- i386_regtab
;
14313 input_line_pointer
= end
;
14318 gas_assert (intel_syntax
);
14319 end
= input_line_pointer
++;
14321 if (*input_line_pointer
== ']')
14323 ++input_line_pointer
;
14324 e
->X_op_symbol
= make_expr_symbol (e
);
14325 e
->X_add_symbol
= NULL
;
14326 e
->X_add_number
= 0;
14331 e
->X_op
= O_absent
;
14332 input_line_pointer
= end
;
14339 /* To maintain consistency with !BFD64 builds of gas record, whether any
14340 (binary) operator was involved in an expression. As expressions are
14341 evaluated in only 32 bits when !BFD64, we use this to decide whether to
14342 truncate results. */
14343 bool i386_record_operator (operatorT op
,
14344 const expressionS
*left
,
14345 const expressionS
*right
)
14347 if (op
== O_absent
)
14352 /* Since the expression parser applies unary operators fine to bignum
14353 operands, we don't need to be concerned of respective operands not
14354 fitting in 32 bits. */
14355 if (right
->X_op
== O_constant
&& right
->X_unsigned
14356 && !fits_in_unsigned_long (right
->X_add_number
))
14359 /* This isn't entirely right: The pattern can also result when constant
14360 expressions are folded (e.g. 0xffffffff + 1). */
14361 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
14362 && !fits_in_unsigned_long (left
->X_add_number
))
14363 || (right
->X_op
== O_constant
&& right
->X_unsigned
14364 && !fits_in_unsigned_long (right
->X_add_number
)))
14365 expr_mode
= expr_large_value
;
14367 if (expr_mode
!= expr_large_value
)
14368 expr_mode
= expr_operator_present
;
14374 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14375 const char *md_shortopts
= "kVQ:sqnO::";
14377 const char *md_shortopts
= "qnO::";
14380 #define OPTION_32 (OPTION_MD_BASE + 0)
14381 #define OPTION_64 (OPTION_MD_BASE + 1)
14382 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
14383 #define OPTION_MARCH (OPTION_MD_BASE + 3)
14384 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
14385 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
14386 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
14387 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
14388 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
14389 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
14390 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
14391 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
14392 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
14393 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
14394 #define OPTION_X32 (OPTION_MD_BASE + 14)
14395 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
14396 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
14397 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
14398 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
14399 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
14400 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
14401 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
14402 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
14403 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
14404 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
14405 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
14406 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
14407 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
14408 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
14409 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
14410 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
14411 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
14412 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
14413 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
14414 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
14416 struct option md_longopts
[] =
14418 {"32", no_argument
, NULL
, OPTION_32
},
14419 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14420 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14421 {"64", no_argument
, NULL
, OPTION_64
},
14423 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14424 {"x32", no_argument
, NULL
, OPTION_X32
},
14425 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14426 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
14428 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
14429 {"march", required_argument
, NULL
, OPTION_MARCH
},
14430 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14431 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
14432 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
14433 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
14434 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
14435 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
14436 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
14437 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
14438 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
14439 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
14440 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
14441 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
14442 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
14443 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
14444 # if defined (TE_PE) || defined (TE_PEP)
14445 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
14447 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
14448 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
14449 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
14450 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
14451 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
14452 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
14453 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
14454 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
14455 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
14456 {"mlfence-before-indirect-branch", required_argument
, NULL
,
14457 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
14458 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
14459 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
14460 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
14461 {NULL
, no_argument
, NULL
, 0}
14463 size_t md_longopts_size
= sizeof (md_longopts
);
14466 md_parse_option (int c
, const char *arg
)
14469 char *arch
, *next
, *saved
, *type
;
14474 optimize_align_code
= 0;
14478 quiet_warnings
= 1;
14481 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14482 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
14483 should be emitted or not. FIXME: Not implemented. */
14485 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
14489 /* -V: SVR4 argument to print version ID. */
14491 print_version_id ();
14494 /* -k: Ignore for FreeBSD compatibility. */
14499 /* -s: On i386 Solaris, this tells the native assembler to use
14500 .stab instead of .stab.excl. We always use .stab anyhow. */
14503 case OPTION_MSHARED
:
14507 case OPTION_X86_USED_NOTE
:
14508 if (strcasecmp (arg
, "yes") == 0)
14510 else if (strcasecmp (arg
, "no") == 0)
14513 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
14518 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14519 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14522 const char **list
, **l
;
14524 list
= bfd_target_list ();
14525 for (l
= list
; *l
!= NULL
; l
++)
14526 if (startswith (*l
, "elf64-x86-64")
14527 || strcmp (*l
, "coff-x86-64") == 0
14528 || strcmp (*l
, "pe-x86-64") == 0
14529 || strcmp (*l
, "pei-x86-64") == 0
14530 || strcmp (*l
, "mach-o-x86-64") == 0)
14532 default_arch
= "x86_64";
14536 as_fatal (_("no compiled in support for x86_64"));
14542 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14546 const char **list
, **l
;
14548 list
= bfd_target_list ();
14549 for (l
= list
; *l
!= NULL
; l
++)
14550 if (startswith (*l
, "elf32-x86-64"))
14552 default_arch
= "x86_64:32";
14556 as_fatal (_("no compiled in support for 32bit x86_64"));
14560 as_fatal (_("32bit x86_64 is only supported for ELF"));
14566 const char **list
, **l
;
14568 list
= bfd_target_list ();
14569 for (l
= list
; *l
!= NULL
; l
++)
14570 if (strstr (*l
, "-i386")
14571 || strstr (*l
, "-go32"))
14573 default_arch
= "i386";
14577 as_fatal (_("no compiled in support for ix86"));
14582 case OPTION_DIVIDE
:
14583 #ifdef SVR4_COMMENT_CHARS
14588 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
14590 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
14594 i386_comment_chars
= n
;
14600 saved
= xstrdup (arg
);
14602 /* Allow -march=+nosse. */
14610 as_fatal (_("invalid -march= option: `%s'"), arg
);
14611 next
= strchr (arch
, '+');
14614 vsz
= strchr (arch
, '/');
14617 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14619 if (vsz
&& cpu_arch
[j
].vsz
!= vsz_set
)
14622 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
14623 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
14626 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14629 cpu_arch_name
= cpu_arch
[j
].name
;
14630 free (cpu_sub_arch_name
);
14631 cpu_sub_arch_name
= NULL
;
14632 cpu_arch_flags
= cpu_arch
[j
].enable
;
14633 cpu_arch_isa
= cpu_arch
[j
].type
;
14634 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
14635 if (!cpu_arch_tune_set
)
14636 cpu_arch_tune
= cpu_arch_isa
;
14637 vector_size
= VSZ_DEFAULT
;
14640 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
14641 && strcmp (arch
, cpu_arch
[j
].name
) == 0
14642 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14644 /* ISA extension. */
14647 switch (cpu_arch
[j
].vsz
)
14656 unsigned long val
= strtoul (vsz
, &end
, 0);
14662 case 512: vector_size
= VSZ512
; break;
14663 case 256: vector_size
= VSZ256
; break;
14664 case 128: vector_size
= VSZ128
; break;
14666 as_warn (_("Unrecognized vector size specifier ignored"));
14671 /* Fall through. */
14673 vector_size
= VSZ_DEFAULT
;
14681 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
14683 /* Disable an ISA extension. */
14684 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14685 if (cpu_arch
[j
].type
== PROCESSOR_NONE
14686 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
14689 if (cpu_arch
[j
].vsz
== vsz_set
)
14690 vector_size
= VSZ_DEFAULT
;
14695 if (j
>= ARRAY_SIZE (cpu_arch
))
14696 as_fatal (_("invalid -march= option: `%s'"), arg
);
14700 while (next
!= NULL
);
14706 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14707 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14709 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14710 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
14712 cpu_arch_tune_set
= 1;
14713 cpu_arch_tune
= cpu_arch
[j
].type
;
14717 if (j
>= ARRAY_SIZE (cpu_arch
))
14718 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14721 case OPTION_MMNEMONIC
:
14722 if (strcasecmp (arg
, "att") == 0)
14723 intel_mnemonic
= 0;
14724 else if (strcasecmp (arg
, "intel") == 0)
14725 intel_mnemonic
= 1;
14727 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
14730 case OPTION_MSYNTAX
:
14731 if (strcasecmp (arg
, "att") == 0)
14733 else if (strcasecmp (arg
, "intel") == 0)
14736 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
14739 case OPTION_MINDEX_REG
:
14740 allow_index_reg
= 1;
14743 case OPTION_MNAKED_REG
:
14744 allow_naked_reg
= 1;
14747 case OPTION_MSSE2AVX
:
14751 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
14752 use_unaligned_vector_move
= 1;
14755 case OPTION_MSSE_CHECK
:
14756 if (strcasecmp (arg
, "error") == 0)
14757 sse_check
= check_error
;
14758 else if (strcasecmp (arg
, "warning") == 0)
14759 sse_check
= check_warning
;
14760 else if (strcasecmp (arg
, "none") == 0)
14761 sse_check
= check_none
;
14763 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
14766 case OPTION_MOPERAND_CHECK
:
14767 if (strcasecmp (arg
, "error") == 0)
14768 operand_check
= check_error
;
14769 else if (strcasecmp (arg
, "warning") == 0)
14770 operand_check
= check_warning
;
14771 else if (strcasecmp (arg
, "none") == 0)
14772 operand_check
= check_none
;
14774 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
14777 case OPTION_MAVXSCALAR
:
14778 if (strcasecmp (arg
, "128") == 0)
14779 avxscalar
= vex128
;
14780 else if (strcasecmp (arg
, "256") == 0)
14781 avxscalar
= vex256
;
14783 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
14786 case OPTION_MVEXWIG
:
14787 if (strcmp (arg
, "0") == 0)
14789 else if (strcmp (arg
, "1") == 0)
14792 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
14795 case OPTION_MADD_BND_PREFIX
:
14796 add_bnd_prefix
= 1;
14799 case OPTION_MEVEXLIG
:
14800 if (strcmp (arg
, "128") == 0)
14801 evexlig
= evexl128
;
14802 else if (strcmp (arg
, "256") == 0)
14803 evexlig
= evexl256
;
14804 else if (strcmp (arg
, "512") == 0)
14805 evexlig
= evexl512
;
14807 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
14810 case OPTION_MEVEXRCIG
:
14811 if (strcmp (arg
, "rne") == 0)
14813 else if (strcmp (arg
, "rd") == 0)
14815 else if (strcmp (arg
, "ru") == 0)
14817 else if (strcmp (arg
, "rz") == 0)
14820 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
14823 case OPTION_MEVEXWIG
:
14824 if (strcmp (arg
, "0") == 0)
14826 else if (strcmp (arg
, "1") == 0)
14829 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
14832 # if defined (TE_PE) || defined (TE_PEP)
14833 case OPTION_MBIG_OBJ
:
14838 case OPTION_MOMIT_LOCK_PREFIX
:
14839 if (strcasecmp (arg
, "yes") == 0)
14840 omit_lock_prefix
= 1;
14841 else if (strcasecmp (arg
, "no") == 0)
14842 omit_lock_prefix
= 0;
14844 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
14847 case OPTION_MFENCE_AS_LOCK_ADD
:
14848 if (strcasecmp (arg
, "yes") == 0)
14850 else if (strcasecmp (arg
, "no") == 0)
14853 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
14856 case OPTION_MLFENCE_AFTER_LOAD
:
14857 if (strcasecmp (arg
, "yes") == 0)
14858 lfence_after_load
= 1;
14859 else if (strcasecmp (arg
, "no") == 0)
14860 lfence_after_load
= 0;
14862 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
14865 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
14866 if (strcasecmp (arg
, "all") == 0)
14868 lfence_before_indirect_branch
= lfence_branch_all
;
14869 if (lfence_before_ret
== lfence_before_ret_none
)
14870 lfence_before_ret
= lfence_before_ret_shl
;
14872 else if (strcasecmp (arg
, "memory") == 0)
14873 lfence_before_indirect_branch
= lfence_branch_memory
;
14874 else if (strcasecmp (arg
, "register") == 0)
14875 lfence_before_indirect_branch
= lfence_branch_register
;
14876 else if (strcasecmp (arg
, "none") == 0)
14877 lfence_before_indirect_branch
= lfence_branch_none
;
14879 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
14883 case OPTION_MLFENCE_BEFORE_RET
:
14884 if (strcasecmp (arg
, "or") == 0)
14885 lfence_before_ret
= lfence_before_ret_or
;
14886 else if (strcasecmp (arg
, "not") == 0)
14887 lfence_before_ret
= lfence_before_ret_not
;
14888 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
14889 lfence_before_ret
= lfence_before_ret_shl
;
14890 else if (strcasecmp (arg
, "none") == 0)
14891 lfence_before_ret
= lfence_before_ret_none
;
14893 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
14897 case OPTION_MRELAX_RELOCATIONS
:
14898 if (strcasecmp (arg
, "yes") == 0)
14899 generate_relax_relocations
= 1;
14900 else if (strcasecmp (arg
, "no") == 0)
14901 generate_relax_relocations
= 0;
14903 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
14906 case OPTION_MALIGN_BRANCH_BOUNDARY
:
14909 long int align
= strtoul (arg
, &end
, 0);
14914 align_branch_power
= 0;
14917 else if (align
>= 16)
14920 for (align_power
= 0;
14922 align
>>= 1, align_power
++)
14924 /* Limit alignment power to 31. */
14925 if (align
== 1 && align_power
< 32)
14927 align_branch_power
= align_power
;
14932 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
14936 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
14939 int align
= strtoul (arg
, &end
, 0);
14940 /* Some processors only support 5 prefixes. */
14941 if (*end
== '\0' && align
>= 0 && align
< 6)
14943 align_branch_prefix_size
= align
;
14946 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
14951 case OPTION_MALIGN_BRANCH
:
14953 saved
= xstrdup (arg
);
14957 next
= strchr (type
, '+');
14960 if (strcasecmp (type
, "jcc") == 0)
14961 align_branch
|= align_branch_jcc_bit
;
14962 else if (strcasecmp (type
, "fused") == 0)
14963 align_branch
|= align_branch_fused_bit
;
14964 else if (strcasecmp (type
, "jmp") == 0)
14965 align_branch
|= align_branch_jmp_bit
;
14966 else if (strcasecmp (type
, "call") == 0)
14967 align_branch
|= align_branch_call_bit
;
14968 else if (strcasecmp (type
, "ret") == 0)
14969 align_branch
|= align_branch_ret_bit
;
14970 else if (strcasecmp (type
, "indirect") == 0)
14971 align_branch
|= align_branch_indirect_bit
;
14973 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14976 while (next
!= NULL
);
14980 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14981 align_branch_power
= 5;
14982 align_branch_prefix_size
= 5;
14983 align_branch
= (align_branch_jcc_bit
14984 | align_branch_fused_bit
14985 | align_branch_jmp_bit
);
14988 case OPTION_MAMD64
:
14992 case OPTION_MINTEL64
:
15000 /* Turn off -Os. */
15001 optimize_for_space
= 0;
15003 else if (*arg
== 's')
15005 optimize_for_space
= 1;
15006 /* Turn on all encoding optimizations. */
15007 optimize
= INT_MAX
;
15011 optimize
= atoi (arg
);
15012 /* Turn off -Os. */
15013 optimize_for_space
= 0;
15023 #define MESSAGE_TEMPLATE \
15027 output_message (FILE *stream
, char *p
, char *message
, char *start
,
15028 int *left_p
, const char *name
, int len
)
15030 int size
= sizeof (MESSAGE_TEMPLATE
);
15031 int left
= *left_p
;
15033 /* Reserve 2 spaces for ", " or ",\0" */
15036 /* Check if there is any room. */
15044 p
= mempcpy (p
, name
, len
);
15048 /* Output the current message now and start a new one. */
15051 fprintf (stream
, "%s\n", message
);
15053 left
= size
- (start
- message
) - len
- 2;
15055 gas_assert (left
>= 0);
15057 p
= mempcpy (p
, name
, len
);
15065 show_arch (FILE *stream
, int ext
, int check
)
15067 static char message
[] = MESSAGE_TEMPLATE
;
15068 char *start
= message
+ 27;
15070 int size
= sizeof (MESSAGE_TEMPLATE
);
15077 left
= size
- (start
- message
);
15081 p
= output_message (stream
, p
, message
, start
, &left
,
15082 STRING_COMMA_LEN ("default"));
15083 p
= output_message (stream
, p
, message
, start
, &left
,
15084 STRING_COMMA_LEN ("push"));
15085 p
= output_message (stream
, p
, message
, start
, &left
,
15086 STRING_COMMA_LEN ("pop"));
15089 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15091 /* Should it be skipped? */
15092 if (cpu_arch
[j
].skip
)
15095 name
= cpu_arch
[j
].name
;
15096 len
= cpu_arch
[j
].len
;
15097 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
15099 /* It is an extension. Skip if we aren't asked to show it. */
15100 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15105 /* It is an processor. Skip if we show only extension. */
15108 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
15110 /* It is an impossible processor - skip. */
15114 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
15117 /* Display disabled extensions. */
15119 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15123 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
15124 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15126 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
15127 p
= output_message (stream
, p
, message
, start
, &left
, str
,
15133 fprintf (stream
, "%s\n", message
);
15137 md_show_usage (FILE *stream
)
15139 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15140 fprintf (stream
, _("\
15141 -Qy, -Qn ignored\n\
15142 -V print assembler version number\n\
15145 fprintf (stream
, _("\
15146 -n do not optimize code alignment\n\
15147 -O{012s} attempt some code optimizations\n\
15148 -q quieten some warnings\n"));
15149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15150 fprintf (stream
, _("\
15154 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15155 fprintf (stream
, _("\
15156 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
15157 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
15158 fprintf (stream
, _("\
15159 --32/--64 generate 32bit/64bit object\n"));
15162 #ifdef SVR4_COMMENT_CHARS
15163 fprintf (stream
, _("\
15164 --divide do not treat `/' as a comment character\n"));
15166 fprintf (stream
, _("\
15167 --divide ignored\n"));
15169 fprintf (stream
, _("\
15170 -march=CPU[,+EXTENSION...]\n\
15171 generate code for CPU and EXTENSION, CPU is one of:\n"));
15172 show_arch (stream
, 0, 1);
15173 fprintf (stream
, _("\
15174 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
15175 show_arch (stream
, 1, 0);
15176 fprintf (stream
, _("\
15177 -mtune=CPU optimize for CPU, CPU is one of:\n"));
15178 show_arch (stream
, 0, 0);
15179 fprintf (stream
, _("\
15180 -msse2avx encode SSE instructions with VEX prefix\n"));
15181 fprintf (stream
, _("\
15182 -muse-unaligned-vector-move\n\
15183 encode aligned vector move as unaligned vector move\n"));
15184 fprintf (stream
, _("\
15185 -msse-check=[none|error|warning] (default: warning)\n\
15186 check SSE instructions\n"));
15187 fprintf (stream
, _("\
15188 -moperand-check=[none|error|warning] (default: warning)\n\
15189 check operand combinations for validity\n"));
15190 fprintf (stream
, _("\
15191 -mavxscalar=[128|256] (default: 128)\n\
15192 encode scalar AVX instructions with specific vector\n\
15194 fprintf (stream
, _("\
15195 -mvexwig=[0|1] (default: 0)\n\
15196 encode VEX instructions with specific VEX.W value\n\
15197 for VEX.W bit ignored instructions\n"));
15198 fprintf (stream
, _("\
15199 -mevexlig=[128|256|512] (default: 128)\n\
15200 encode scalar EVEX instructions with specific vector\n\
15202 fprintf (stream
, _("\
15203 -mevexwig=[0|1] (default: 0)\n\
15204 encode EVEX instructions with specific EVEX.W value\n\
15205 for EVEX.W bit ignored instructions\n"));
15206 fprintf (stream
, _("\
15207 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
15208 encode EVEX instructions with specific EVEX.RC value\n\
15209 for SAE-only ignored instructions\n"));
15210 fprintf (stream
, _("\
15211 -mmnemonic=[att|intel] "));
15212 if (SYSV386_COMPAT
)
15213 fprintf (stream
, _("(default: att)\n"));
15215 fprintf (stream
, _("(default: intel)\n"));
15216 fprintf (stream
, _("\
15217 use AT&T/Intel mnemonic\n"));
15218 fprintf (stream
, _("\
15219 -msyntax=[att|intel] (default: att)\n\
15220 use AT&T/Intel syntax\n"));
15221 fprintf (stream
, _("\
15222 -mindex-reg support pseudo index registers\n"));
15223 fprintf (stream
, _("\
15224 -mnaked-reg don't require `%%' prefix for registers\n"));
15225 fprintf (stream
, _("\
15226 -madd-bnd-prefix add BND prefix for all valid branches\n"));
15227 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15228 fprintf (stream
, _("\
15229 -mshared disable branch optimization for shared code\n"));
15230 fprintf (stream
, _("\
15231 -mx86-used-note=[no|yes] "));
15232 if (DEFAULT_X86_USED_NOTE
)
15233 fprintf (stream
, _("(default: yes)\n"));
15235 fprintf (stream
, _("(default: no)\n"));
15236 fprintf (stream
, _("\
15237 generate x86 used ISA and feature properties\n"));
15239 #if defined (TE_PE) || defined (TE_PEP)
15240 fprintf (stream
, _("\
15241 -mbig-obj generate big object files\n"));
15243 fprintf (stream
, _("\
15244 -momit-lock-prefix=[no|yes] (default: no)\n\
15245 strip all lock prefixes\n"));
15246 fprintf (stream
, _("\
15247 -mfence-as-lock-add=[no|yes] (default: no)\n\
15248 encode lfence, mfence and sfence as\n\
15249 lock addl $0x0, (%%{re}sp)\n"));
15250 fprintf (stream
, _("\
15251 -mrelax-relocations=[no|yes] "));
15252 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
15253 fprintf (stream
, _("(default: yes)\n"));
15255 fprintf (stream
, _("(default: no)\n"));
15256 fprintf (stream
, _("\
15257 generate relax relocations\n"));
15258 fprintf (stream
, _("\
15259 -malign-branch-boundary=NUM (default: 0)\n\
15260 align branches within NUM byte boundary\n"));
15261 fprintf (stream
, _("\
15262 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
15263 TYPE is combination of jcc, fused, jmp, call, ret,\n\
15265 specify types of branches to align\n"));
15266 fprintf (stream
, _("\
15267 -malign-branch-prefix-size=NUM (default: 5)\n\
15268 align branches with NUM prefixes per instruction\n"));
15269 fprintf (stream
, _("\
15270 -mbranches-within-32B-boundaries\n\
15271 align branches within 32 byte boundary\n"));
15272 fprintf (stream
, _("\
15273 -mlfence-after-load=[no|yes] (default: no)\n\
15274 generate lfence after load\n"));
15275 fprintf (stream
, _("\
15276 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
15277 generate lfence before indirect near branch\n"));
15278 fprintf (stream
, _("\
15279 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
15280 generate lfence before ret\n"));
15281 fprintf (stream
, _("\
15282 -mamd64 accept only AMD64 ISA [default]\n"));
15283 fprintf (stream
, _("\
15284 -mintel64 accept only Intel64 ISA\n"));
15287 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
15288 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
15289 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
15291 /* Pick the target format to use. */
15294 i386_target_format (void)
15296 if (startswith (default_arch
, "x86_64"))
15298 update_code_flag (CODE_64BIT
, 1);
15299 if (default_arch
[6] == '\0')
15300 x86_elf_abi
= X86_64_ABI
;
15302 x86_elf_abi
= X86_64_X32_ABI
;
15304 else if (!strcmp (default_arch
, "i386"))
15305 update_code_flag (CODE_32BIT
, 1);
15306 else if (!strcmp (default_arch
, "iamcu"))
15308 update_code_flag (CODE_32BIT
, 1);
15309 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
15311 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
15312 cpu_arch_name
= "iamcu";
15313 free (cpu_sub_arch_name
);
15314 cpu_sub_arch_name
= NULL
;
15315 cpu_arch_flags
= iamcu_flags
;
15316 cpu_arch_isa
= PROCESSOR_IAMCU
;
15317 cpu_arch_isa_flags
= iamcu_flags
;
15318 if (!cpu_arch_tune_set
)
15319 cpu_arch_tune
= PROCESSOR_IAMCU
;
15321 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
15322 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
15326 as_fatal (_("unknown architecture"));
15328 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
15329 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15331 switch (OUTPUT_FLAVOR
)
15333 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
15334 case bfd_target_aout_flavour
:
15335 return AOUT_TARGET_FORMAT
;
15337 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
15338 # if defined (TE_PE) || defined (TE_PEP)
15339 case bfd_target_coff_flavour
:
15340 if (flag_code
== CODE_64BIT
)
15343 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
15345 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
15346 # elif defined (TE_GO32)
15347 case bfd_target_coff_flavour
:
15348 return "coff-go32";
15350 case bfd_target_coff_flavour
:
15351 return "coff-i386";
15354 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15355 case bfd_target_elf_flavour
:
15357 const char *format
;
15359 switch (x86_elf_abi
)
15362 format
= ELF_TARGET_FORMAT
;
15364 tls_get_addr
= "___tls_get_addr";
15368 use_rela_relocations
= 1;
15371 tls_get_addr
= "__tls_get_addr";
15373 format
= ELF_TARGET_FORMAT64
;
15375 case X86_64_X32_ABI
:
15376 use_rela_relocations
= 1;
15379 tls_get_addr
= "__tls_get_addr";
15381 disallow_64bit_reloc
= 1;
15382 format
= ELF_TARGET_FORMAT32
;
15385 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
15387 if (x86_elf_abi
!= I386_ABI
)
15388 as_fatal (_("Intel MCU is 32bit only"));
15389 return ELF_TARGET_IAMCU_FORMAT
;
15395 #if defined (OBJ_MACH_O)
15396 case bfd_target_mach_o_flavour
:
15397 if (flag_code
== CODE_64BIT
)
15399 use_rela_relocations
= 1;
15401 return "mach-o-x86-64";
15404 return "mach-o-i386";
15412 #endif /* OBJ_MAYBE_ more than one */
15415 md_undefined_symbol (char *name
)
15417 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
15418 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
15419 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
15420 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
15424 if (symbol_find (name
))
15425 as_bad (_("GOT already in symbol table"));
15426 GOT_symbol
= symbol_new (name
, undefined_section
,
15427 &zero_address_frag
, 0);
15434 /* Round up a section size to the appropriate boundary. */
15437 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
15439 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
15440 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
15442 /* For a.out, force the section size to be aligned. If we don't do
15443 this, BFD will align it for us, but it will not write out the
15444 final bytes of the section. This may be a bug in BFD, but it is
15445 easier to fix it here since that is how the other a.out targets
15449 align
= bfd_section_alignment (segment
);
15450 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
15457 /* On the i386, PC-relative offsets are relative to the start of the
15458 next instruction. That is, the address of the offset, plus its
15459 size, since the offset is always the last part of the insn. */
15462 md_pcrel_from (fixS
*fixP
)
15464 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15470 s_bss (int ignore ATTRIBUTE_UNUSED
)
15474 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15476 obj_elf_section_change_hook ();
15478 temp
= get_absolute_expression ();
15479 subseg_set (bss_section
, (subsegT
) temp
);
15480 demand_empty_rest_of_line ();
15485 /* Remember constant directive. */
15488 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
15490 if (last_insn
.kind
!= last_insn_directive
15491 && (bfd_section_flags (now_seg
) & SEC_CODE
))
15493 last_insn
.seg
= now_seg
;
15494 last_insn
.kind
= last_insn_directive
;
15495 last_insn
.name
= "constant directive";
15496 last_insn
.file
= as_where (&last_insn
.line
);
15497 if (lfence_before_ret
!= lfence_before_ret_none
)
15499 if (lfence_before_indirect_branch
!= lfence_branch_none
)
15500 as_warn (_("constant directive skips -mlfence-before-ret "
15501 "and -mlfence-before-indirect-branch"));
15503 as_warn (_("constant directive skips -mlfence-before-ret"));
15505 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
15506 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
15511 i386_validate_fix (fixS
*fixp
)
15513 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
15515 reloc_howto_type
*howto
;
15517 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
15518 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15519 _("invalid %s relocation against register"),
15520 howto
? howto
->name
: "<unknown>");
15524 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15525 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15526 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
15527 return IS_ELF
&& fixp
->fx_addsy
15528 && (!S_IS_DEFINED (fixp
->fx_addsy
)
15529 || S_IS_EXTERNAL (fixp
->fx_addsy
));
15532 if (fixp
->fx_subsy
)
15534 if (fixp
->fx_subsy
== GOT_symbol
)
15536 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
15540 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15541 if (fixp
->fx_tcbit2
)
15542 fixp
->fx_r_type
= (fixp
->fx_tcbit
15543 ? BFD_RELOC_X86_64_REX_GOTPCRELX
15544 : BFD_RELOC_X86_64_GOTPCRELX
);
15547 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
15552 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
15554 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
15556 fixp
->fx_subsy
= 0;
15559 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15562 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
15563 to section. Since PLT32 relocation must be against symbols,
15564 turn such PLT32 relocation into PC32 relocation. */
15566 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
15567 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
15568 && symbol_section_p (fixp
->fx_addsy
))
15569 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
15572 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
15573 && fixp
->fx_tcbit2
)
15574 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
15583 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
15586 bfd_reloc_code_real_type code
;
15588 switch (fixp
->fx_r_type
)
15590 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15593 case BFD_RELOC_SIZE32
:
15594 case BFD_RELOC_SIZE64
:
15596 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
15597 && (!fixp
->fx_subsy
15598 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
15599 sym
= fixp
->fx_addsy
;
15600 else if (fixp
->fx_subsy
15601 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
15602 && (!fixp
->fx_addsy
15603 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
15604 sym
= fixp
->fx_subsy
;
15607 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
15609 /* Resolve size relocation against local symbol to size of
15610 the symbol plus addend. */
15611 valueT value
= S_GET_SIZE (sym
);
15613 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
15614 value
= bfd_section_size (S_GET_SEGMENT (sym
));
15615 if (sym
== fixp
->fx_subsy
)
15618 if (fixp
->fx_addsy
)
15619 value
+= S_GET_VALUE (fixp
->fx_addsy
);
15621 else if (fixp
->fx_subsy
)
15622 value
-= S_GET_VALUE (fixp
->fx_subsy
);
15623 value
+= fixp
->fx_offset
;
15624 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15626 && !fits_in_unsigned_long (value
))
15627 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15628 _("symbol size computation overflow"));
15629 fixp
->fx_addsy
= NULL
;
15630 fixp
->fx_subsy
= NULL
;
15631 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
15634 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
15636 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15637 "unsupported expression involving @size");
15641 /* Fall through. */
15643 case BFD_RELOC_X86_64_PLT32
:
15644 case BFD_RELOC_X86_64_GOT32
:
15645 case BFD_RELOC_X86_64_GOTPCREL
:
15646 case BFD_RELOC_X86_64_GOTPCRELX
:
15647 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15648 case BFD_RELOC_386_PLT32
:
15649 case BFD_RELOC_386_GOT32
:
15650 case BFD_RELOC_386_GOT32X
:
15651 case BFD_RELOC_386_GOTOFF
:
15652 case BFD_RELOC_386_GOTPC
:
15653 case BFD_RELOC_386_TLS_GD
:
15654 case BFD_RELOC_386_TLS_LDM
:
15655 case BFD_RELOC_386_TLS_LDO_32
:
15656 case BFD_RELOC_386_TLS_IE_32
:
15657 case BFD_RELOC_386_TLS_IE
:
15658 case BFD_RELOC_386_TLS_GOTIE
:
15659 case BFD_RELOC_386_TLS_LE_32
:
15660 case BFD_RELOC_386_TLS_LE
:
15661 case BFD_RELOC_386_TLS_GOTDESC
:
15662 case BFD_RELOC_386_TLS_DESC_CALL
:
15663 case BFD_RELOC_X86_64_TLSGD
:
15664 case BFD_RELOC_X86_64_TLSLD
:
15665 case BFD_RELOC_X86_64_DTPOFF32
:
15666 case BFD_RELOC_X86_64_DTPOFF64
:
15667 case BFD_RELOC_X86_64_GOTTPOFF
:
15668 case BFD_RELOC_X86_64_TPOFF32
:
15669 case BFD_RELOC_X86_64_TPOFF64
:
15670 case BFD_RELOC_X86_64_GOTOFF64
:
15671 case BFD_RELOC_X86_64_GOTPC32
:
15672 case BFD_RELOC_X86_64_GOT64
:
15673 case BFD_RELOC_X86_64_GOTPCREL64
:
15674 case BFD_RELOC_X86_64_GOTPC64
:
15675 case BFD_RELOC_X86_64_GOTPLT64
:
15676 case BFD_RELOC_X86_64_PLTOFF64
:
15677 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15678 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15679 case BFD_RELOC_RVA
:
15680 case BFD_RELOC_VTABLE_ENTRY
:
15681 case BFD_RELOC_VTABLE_INHERIT
:
15683 case BFD_RELOC_32_SECREL
:
15684 case BFD_RELOC_16_SECIDX
:
15686 code
= fixp
->fx_r_type
;
15688 case BFD_RELOC_X86_64_32S
:
15689 if (!fixp
->fx_pcrel
)
15691 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
15692 code
= fixp
->fx_r_type
;
15695 /* Fall through. */
15697 if (fixp
->fx_pcrel
)
15699 switch (fixp
->fx_size
)
15702 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15703 _("can not do %d byte pc-relative relocation"),
15705 code
= BFD_RELOC_32_PCREL
;
15707 case 1: code
= BFD_RELOC_8_PCREL
; break;
15708 case 2: code
= BFD_RELOC_16_PCREL
; break;
15709 case 4: code
= BFD_RELOC_32_PCREL
; break;
15711 case 8: code
= BFD_RELOC_64_PCREL
; break;
15717 switch (fixp
->fx_size
)
15720 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15721 _("can not do %d byte relocation"),
15723 code
= BFD_RELOC_32
;
15725 case 1: code
= BFD_RELOC_8
; break;
15726 case 2: code
= BFD_RELOC_16
; break;
15727 case 4: code
= BFD_RELOC_32
; break;
15729 case 8: code
= BFD_RELOC_64
; break;
15736 if ((code
== BFD_RELOC_32
15737 || code
== BFD_RELOC_32_PCREL
15738 || code
== BFD_RELOC_X86_64_32S
)
15740 && fixp
->fx_addsy
== GOT_symbol
)
15743 code
= BFD_RELOC_386_GOTPC
;
15745 code
= BFD_RELOC_X86_64_GOTPC32
;
15747 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
15749 && fixp
->fx_addsy
== GOT_symbol
)
15751 code
= BFD_RELOC_X86_64_GOTPC64
;
15754 rel
= XNEW (arelent
);
15755 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
15756 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
15758 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
15760 if (!use_rela_relocations
)
15762 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
15763 vtable entry to be used in the relocation's section offset. */
15764 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15765 rel
->address
= fixp
->fx_offset
;
15766 #if defined (OBJ_COFF) && defined (TE_PE)
15767 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
15768 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
15773 /* Use the rela in 64bit mode. */
15776 if (disallow_64bit_reloc
)
15779 case BFD_RELOC_X86_64_DTPOFF64
:
15780 case BFD_RELOC_X86_64_TPOFF64
:
15781 case BFD_RELOC_64_PCREL
:
15782 case BFD_RELOC_X86_64_GOTOFF64
:
15783 case BFD_RELOC_X86_64_GOT64
:
15784 case BFD_RELOC_X86_64_GOTPCREL64
:
15785 case BFD_RELOC_X86_64_GOTPC64
:
15786 case BFD_RELOC_X86_64_GOTPLT64
:
15787 case BFD_RELOC_X86_64_PLTOFF64
:
15788 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15789 _("cannot represent relocation type %s in x32 mode"),
15790 bfd_get_reloc_code_name (code
));
15796 if (!fixp
->fx_pcrel
)
15797 rel
->addend
= fixp
->fx_offset
;
15801 case BFD_RELOC_X86_64_PLT32
:
15802 case BFD_RELOC_X86_64_GOT32
:
15803 case BFD_RELOC_X86_64_GOTPCREL
:
15804 case BFD_RELOC_X86_64_GOTPCRELX
:
15805 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15806 case BFD_RELOC_X86_64_TLSGD
:
15807 case BFD_RELOC_X86_64_TLSLD
:
15808 case BFD_RELOC_X86_64_GOTTPOFF
:
15809 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15810 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15811 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
15814 rel
->addend
= (section
->vma
15816 + fixp
->fx_addnumber
15817 + md_pcrel_from (fixp
));
15822 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
15823 if (rel
->howto
== NULL
)
15825 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15826 _("cannot represent relocation type %s"),
15827 bfd_get_reloc_code_name (code
));
15828 /* Set howto to a garbage value so that we can keep going. */
15829 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
15830 gas_assert (rel
->howto
!= NULL
);
15836 #include "tc-i386-intel.c"
15839 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
15841 int saved_naked_reg
;
15842 char saved_register_dot
;
15844 saved_naked_reg
= allow_naked_reg
;
15845 allow_naked_reg
= 1;
15846 saved_register_dot
= register_chars
['.'];
15847 register_chars
['.'] = '.';
15848 allow_pseudo_reg
= 1;
15849 expression_and_evaluate (exp
);
15850 allow_pseudo_reg
= 0;
15851 register_chars
['.'] = saved_register_dot
;
15852 allow_naked_reg
= saved_naked_reg
;
15854 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
15856 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
15858 exp
->X_op
= O_constant
;
15859 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
15860 .dw2_regnum
[flag_code
>> 1];
15863 exp
->X_op
= O_illegal
;
15868 tc_x86_frame_initial_instructions (void)
15870 static unsigned int sp_regno
[2];
15872 if (!sp_regno
[flag_code
>> 1])
15874 char *saved_input
= input_line_pointer
;
15875 char sp
[][4] = {"esp", "rsp"};
15878 input_line_pointer
= sp
[flag_code
>> 1];
15879 tc_x86_parse_to_dw2regnum (&exp
);
15880 gas_assert (exp
.X_op
== O_constant
);
15881 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
15882 input_line_pointer
= saved_input
;
15885 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
15886 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
15890 x86_dwarf2_addr_size (void)
15892 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15893 if (x86_elf_abi
== X86_64_X32_ABI
)
15896 return bfd_arch_bits_per_address (stdoutput
) / 8;
15900 i386_elf_section_type (const char *str
, size_t len
)
15902 if (flag_code
== CODE_64BIT
15903 && len
== sizeof ("unwind") - 1
15904 && startswith (str
, "unwind"))
15905 return SHT_X86_64_UNWIND
;
15912 i386_solaris_fix_up_eh_frame (segT sec
)
15914 if (flag_code
== CODE_64BIT
)
15915 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
15921 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
15925 exp
.X_op
= O_secrel
;
15926 exp
.X_add_symbol
= symbol
;
15927 exp
.X_add_number
= 0;
15928 emit_expr (&exp
, size
);
15932 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15933 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
15936 x86_64_section_letter (int letter
, const char **ptr_msg
)
15938 if (flag_code
== CODE_64BIT
)
15941 return SHF_X86_64_LARGE
;
15943 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
15946 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
15951 handle_large_common (int small ATTRIBUTE_UNUSED
)
15953 if (flag_code
!= CODE_64BIT
)
15955 s_comm_internal (0, elf_common_parse
);
15956 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
15960 static segT lbss_section
;
15961 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15962 asection
*saved_bss_section
= bss_section
;
15964 if (lbss_section
== NULL
)
15966 flagword applicable
;
15967 segT seg
= now_seg
;
15968 subsegT subseg
= now_subseg
;
15970 /* The .lbss section is for local .largecomm symbols. */
15971 lbss_section
= subseg_new (".lbss", 0);
15972 applicable
= bfd_applicable_section_flags (stdoutput
);
15973 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15974 seg_info (lbss_section
)->bss
= 1;
15976 subseg_set (seg
, subseg
);
15979 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15980 bss_section
= lbss_section
;
15982 s_comm_internal (0, elf_common_parse
);
15984 elf_com_section_ptr
= saved_com_section_ptr
;
15985 bss_section
= saved_bss_section
;
15988 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */