1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 enum { vsz_none
, vsz_set
, vsz_reset
} vsz
; /* vector size control */
135 i386_cpu_flags enable
; /* cpu feature enable flags */
136 i386_cpu_flags disable
; /* cpu feature disable flags */
140 static void update_code_flag (int, int);
141 static void s_insn (int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
151 static void pe_directive_secidx (int);
153 static void signed_cons (int);
154 static char *output_invalid (int c
);
155 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
157 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
159 static int i386_att_operand (char *);
160 static int i386_intel_operand (char *, int);
161 static int i386_intel_simplify (expressionS
*);
162 static int i386_intel_parse_name (const char *, expressionS
*);
163 static const reg_entry
*parse_register (const char *, char **);
164 static const char *parse_insn (const char *, char *, bool);
165 static char *parse_operands (char *, const char *);
166 static void swap_operands (void);
167 static void swap_2_operands (unsigned int, unsigned int);
168 static enum flag_code
i386_addressing_mode (void);
169 static void optimize_imm (void);
170 static bool optimize_disp (const insn_template
*t
);
171 static const insn_template
*match_template (char);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const reg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
190 /* GNU_PROPERTY_X86_ISA_1_USED. */
191 static unsigned int x86_isa_1_used
;
192 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
193 static unsigned int x86_feature_2_used
;
194 /* Generate x86 used ISA and feature properties. */
195 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
198 static const char *default_arch
= DEFAULT_ARCH
;
200 /* parse_register() returns this when a register alias cannot be used. */
201 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
202 { Dw2Inval
, Dw2Inval
} };
204 static const reg_entry
*reg_eax
;
205 static const reg_entry
*reg_ds
;
206 static const reg_entry
*reg_es
;
207 static const reg_entry
*reg_ss
;
208 static const reg_entry
*reg_st0
;
209 static const reg_entry
*reg_k0
;
214 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
215 unsigned char bytes
[4];
217 /* Destination or source register specifier. */
218 const reg_entry
*register_specifier
;
221 /* 'md_assemble ()' gathers together information and puts it into a
228 const reg_entry
*regs
;
233 no_error
, /* Must be first. */
234 operand_size_mismatch
,
235 operand_type_mismatch
,
236 register_type_mismatch
,
237 number_of_operands_mismatch
,
238 invalid_instruction_suffix
,
240 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 invalid_dest_and_src_register_set
,
250 unsupported_vector_index_register
,
251 unsupported_broadcast
,
254 mask_not_on_destination
,
257 invalid_register_operand
,
262 /* TM holds the template for the insn were currently assembling. */
265 /* SUFFIX holds the instruction size suffix for byte, word, dword
266 or qword, if given. */
269 /* OPCODE_LENGTH holds the number of base opcode bytes. */
270 unsigned char opcode_length
;
272 /* OPERANDS gives the number of given operands. */
273 unsigned int operands
;
275 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
276 of given register, displacement, memory operands and immediate
278 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
280 /* TYPES [i] is the type (see above #defines) which tells us how to
281 use OP[i] for the corresponding operand. */
282 i386_operand_type types
[MAX_OPERANDS
];
284 /* Displacement expression, immediate expression, or register for each
286 union i386_op op
[MAX_OPERANDS
];
288 /* Flags for operands. */
289 unsigned int flags
[MAX_OPERANDS
];
290 #define Operand_PCrel 1
291 #define Operand_Mem 2
292 #define Operand_Signed 4 /* .insn only */
294 /* Relocation type for operand */
295 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
297 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
298 the base index byte below. */
299 const reg_entry
*base_reg
;
300 const reg_entry
*index_reg
;
301 unsigned int log2_scale_factor
;
303 /* SEG gives the seg_entries of this insn. They are zero unless
304 explicit segment overrides are given. */
305 const reg_entry
*seg
[2];
307 /* PREFIX holds all the given prefix opcodes (usually null).
308 PREFIXES is the number of prefix opcodes. */
309 unsigned int prefixes
;
310 unsigned char prefix
[MAX_PREFIXES
];
312 /* .insn allows for reserved opcode spaces. */
313 unsigned char insn_opcode_space
;
315 /* .insn also allows (requires) specifying immediate size. */
316 unsigned char imm_bits
[MAX_OPERANDS
];
318 /* Register is in low 3 bits of opcode. */
321 /* The operand to a branch insn indicates an absolute branch. */
324 /* The operand to a branch insn indicates a far branch. */
327 /* There is a memory operand of (%dx) which should be only used
328 with input/output instructions. */
329 bool input_output_operand
;
331 /* Extended states. */
339 xstate_ymm
= 1 << 2 | xstate_xmm
,
341 xstate_zmm
= 1 << 3 | xstate_ymm
,
344 /* Use MASK state. */
348 /* Has GOTPC or TLS relocation. */
349 bool has_gotpc_tls_reloc
;
351 /* RM and SIB are the modrm byte and the sib byte where the
352 addressing modes of this insn are encoded. */
359 /* Masking attributes.
361 The struct describes masking, applied to OPERAND in the instruction.
362 REG is a pointer to the corresponding mask register. ZEROING tells
363 whether merging or zeroing mask is used. */
364 struct Mask_Operation
366 const reg_entry
*reg
;
367 unsigned int zeroing
;
368 /* The operand where this operation is associated. */
369 unsigned int operand
;
372 /* Rounding control and SAE attributes. */
384 /* In Intel syntax the operand modifier form is supposed to be used, but
385 we continue to accept the immediate forms as well. */
389 /* Broadcasting attributes.
391 The struct describes broadcasting, applied to OPERAND. TYPE is
392 expresses the broadcast factor. */
393 struct Broadcast_Operation
395 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
398 /* Index of broadcasted operand. */
399 unsigned int operand
;
401 /* Number of bytes to broadcast. */
405 /* Compressed disp8*N attribute. */
406 unsigned int memshift
;
408 /* Prefer load or store in encoding. */
411 dir_encoding_default
= 0,
417 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
420 disp_encoding_default
= 0,
426 /* Prefer the REX byte in encoding. */
429 /* Disable instruction size optimization. */
432 /* How to encode vector instructions. */
435 vex_encoding_default
= 0,
439 vex_encoding_evex512
,
444 const char *rep_prefix
;
447 const char *hle_prefix
;
449 /* Have BND prefix. */
450 const char *bnd_prefix
;
452 /* Have NOTRACK prefix. */
453 const char *notrack_prefix
;
456 enum i386_error error
;
459 typedef struct _i386_insn i386_insn
;
461 /* Link RC type with corresponding string, that'll be looked for in
470 static const struct RC_name RC_NamesTable
[] =
472 { rne
, STRING_COMMA_LEN ("rn-sae") },
473 { rd
, STRING_COMMA_LEN ("rd-sae") },
474 { ru
, STRING_COMMA_LEN ("ru-sae") },
475 { rz
, STRING_COMMA_LEN ("rz-sae") },
476 { saeonly
, STRING_COMMA_LEN ("sae") },
479 /* To be indexed by segment register number. */
480 static const unsigned char i386_seg_prefixes
[] = {
489 /* List of chars besides those in app.c:symbol_chars that can start an
490 operand. Used to prevent the scrubber eating vital white-space. */
491 const char extra_symbol_chars
[] = "*%-([{}"
500 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
501 && !defined (TE_GNU) \
502 && !defined (TE_LINUX) \
503 && !defined (TE_Haiku) \
504 && !defined (TE_FreeBSD) \
505 && !defined (TE_DragonFly) \
506 && !defined (TE_NetBSD))
507 /* This array holds the chars that always start a comment. If the
508 pre-processor is disabled, these aren't very useful. The option
509 --divide will remove '/' from this list. */
510 const char *i386_comment_chars
= "#/";
511 #define SVR4_COMMENT_CHARS 1
512 #define PREFIX_SEPARATOR '\\'
515 const char *i386_comment_chars
= "#";
516 #define PREFIX_SEPARATOR '/'
519 /* This array holds the chars that only start a comment at the beginning of
520 a line. If the line seems to have the form '# 123 filename'
521 .line and .file directives will appear in the pre-processed output.
522 Note that input_file.c hand checks for '#' at the beginning of the
523 first line of the input file. This is because the compiler outputs
524 #NO_APP at the beginning of its output.
525 Also note that comments started like this one will always work if
526 '/' isn't otherwise defined. */
527 const char line_comment_chars
[] = "#/";
529 const char line_separator_chars
[] = ";";
531 /* Chars that can be used to separate mant from exp in floating point
533 const char EXP_CHARS
[] = "eE";
535 /* Chars that mean this number is a floating point constant
538 const char FLT_CHARS
[] = "fFdDxXhHbB";
540 /* Tables for lexical analysis. */
541 static char mnemonic_chars
[256];
542 static char register_chars
[256];
543 static char operand_chars
[256];
545 /* Lexical macros. */
546 #define is_operand_char(x) (operand_chars[(unsigned char) x])
547 #define is_register_char(x) (register_chars[(unsigned char) x])
548 #define is_space_char(x) ((x) == ' ')
550 /* All non-digit non-letter characters that may occur in an operand and
551 which aren't already in extra_symbol_chars[]. */
552 static const char operand_special_chars
[] = "$+,)._~/<>|&^!=:@]";
554 /* md_assemble() always leaves the strings it's passed unaltered. To
555 effect this we maintain a stack of saved characters that we've smashed
556 with '\0's (indicating end of strings for various sub-fields of the
557 assembler instruction). */
558 static char save_stack
[32];
559 static char *save_stack_p
;
560 #define END_STRING_AND_SAVE(s) \
561 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
562 #define RESTORE_END_STRING(s) \
563 do { *(s) = *--save_stack_p; } while (0)
565 /* The instruction we're assembling. */
568 /* Possible templates for current insn. */
569 static const templates
*current_templates
;
571 /* Per instruction expressionS buffers: max displacements & immediates. */
572 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
573 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
575 /* Current operand we are working on. */
576 static int this_operand
= -1;
578 /* Are we processing a .insn directive? */
579 #define dot_insn() (i.tm.mnem_off == MN__insn)
581 /* We support four different modes. FLAG_CODE variable is used to distinguish
589 static enum flag_code flag_code
;
590 static unsigned int object_64bit
;
591 static unsigned int disallow_64bit_reloc
;
592 static int use_rela_relocations
= 0;
593 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
594 static const char *tls_get_addr
;
596 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
597 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
598 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
600 /* The ELF ABI to use. */
608 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
611 #if defined (TE_PE) || defined (TE_PEP)
612 /* Use big object file format. */
613 static int use_big_obj
= 0;
616 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
617 /* 1 if generating code for a shared library. */
618 static int shared
= 0;
620 unsigned int x86_sframe_cfa_sp_reg
;
621 /* The other CFA base register for SFrame stack trace info. */
622 unsigned int x86_sframe_cfa_fp_reg
;
623 unsigned int x86_sframe_cfa_ra_reg
;
627 /* 1 for intel syntax,
629 static int intel_syntax
= 0;
631 static enum x86_64_isa
633 amd64
= 1, /* AMD64 ISA. */
634 intel64
/* Intel64 ISA. */
637 /* 1 for intel mnemonic,
638 0 if att mnemonic. */
639 static int intel_mnemonic
= !SYSV386_COMPAT
;
641 /* 1 if pseudo registers are permitted. */
642 static int allow_pseudo_reg
= 0;
644 /* 1 if register prefix % not required. */
645 static int allow_naked_reg
= 0;
647 /* 1 if the assembler should add BND prefix for all control-transferring
648 instructions supporting it, even if this prefix wasn't specified
650 static int add_bnd_prefix
= 0;
652 /* 1 if pseudo index register, eiz/riz, is allowed . */
653 static int allow_index_reg
= 0;
655 /* 1 if the assembler should ignore LOCK prefix, even if it was
656 specified explicitly. */
657 static int omit_lock_prefix
= 0;
659 /* 1 if the assembler should encode lfence, mfence, and sfence as
660 "lock addl $0, (%{re}sp)". */
661 static int avoid_fence
= 0;
663 /* 1 if lfence should be inserted after every load. */
664 static int lfence_after_load
= 0;
666 /* Non-zero if lfence should be inserted before indirect branch. */
667 static enum lfence_before_indirect_branch_kind
669 lfence_branch_none
= 0,
670 lfence_branch_register
,
671 lfence_branch_memory
,
674 lfence_before_indirect_branch
;
676 /* Non-zero if lfence should be inserted before ret. */
677 static enum lfence_before_ret_kind
679 lfence_before_ret_none
= 0,
680 lfence_before_ret_not
,
681 lfence_before_ret_or
,
682 lfence_before_ret_shl
686 /* Types of previous instruction is .byte or prefix. */
701 /* 1 if the assembler should generate relax relocations. */
703 static int generate_relax_relocations
704 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
706 static enum check_kind
712 sse_check
, operand_check
= check_warning
;
714 /* Non-zero if branches should be aligned within power of 2 boundary. */
715 static int align_branch_power
= 0;
717 /* Types of branches to align. */
718 enum align_branch_kind
720 align_branch_none
= 0,
721 align_branch_jcc
= 1,
722 align_branch_fused
= 2,
723 align_branch_jmp
= 3,
724 align_branch_call
= 4,
725 align_branch_indirect
= 5,
729 /* Type bits of branches to align. */
730 enum align_branch_bit
732 align_branch_jcc_bit
= 1 << align_branch_jcc
,
733 align_branch_fused_bit
= 1 << align_branch_fused
,
734 align_branch_jmp_bit
= 1 << align_branch_jmp
,
735 align_branch_call_bit
= 1 << align_branch_call
,
736 align_branch_indirect_bit
= 1 << align_branch_indirect
,
737 align_branch_ret_bit
= 1 << align_branch_ret
740 static unsigned int align_branch
= (align_branch_jcc_bit
741 | align_branch_fused_bit
742 | align_branch_jmp_bit
);
744 /* Types of condition jump used by macro-fusion. */
747 mf_jcc_jo
= 0, /* base opcode 0x70 */
748 mf_jcc_jc
, /* base opcode 0x72 */
749 mf_jcc_je
, /* base opcode 0x74 */
750 mf_jcc_jna
, /* base opcode 0x76 */
751 mf_jcc_js
, /* base opcode 0x78 */
752 mf_jcc_jp
, /* base opcode 0x7a */
753 mf_jcc_jl
, /* base opcode 0x7c */
754 mf_jcc_jle
, /* base opcode 0x7e */
757 /* Types of compare flag-modifying insntructions used by macro-fusion. */
760 mf_cmp_test_and
, /* test/cmp */
761 mf_cmp_alu_cmp
, /* add/sub/cmp */
762 mf_cmp_incdec
/* inc/dec */
765 /* The maximum padding size for fused jcc. CMP like instruction can
766 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
768 #define MAX_FUSED_JCC_PADDING_SIZE 20
770 /* The maximum number of prefixes added for an instruction. */
771 static unsigned int align_branch_prefix_size
= 5;
774 1. Clear the REX_W bit with register operand if possible.
775 2. Above plus use 128bit vector instruction to clear the full vector
778 static int optimize
= 0;
781 1. Clear the REX_W bit with register operand if possible.
782 2. Above plus use 128bit vector instruction to clear the full vector
784 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
787 static int optimize_for_space
= 0;
789 /* Register prefix used for error message. */
790 static const char *register_prefix
= "%";
792 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
793 leave, push, and pop instructions so that gcc has the same stack
794 frame as in 32 bit mode. */
795 static char stackop_size
= '\0';
797 /* Non-zero to optimize code alignment. */
798 int optimize_align_code
= 1;
800 /* Non-zero to quieten some warnings. */
801 static int quiet_warnings
= 0;
803 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
804 static bool pre_386_16bit_warned
;
807 static const char *cpu_arch_name
= NULL
;
808 static char *cpu_sub_arch_name
= NULL
;
810 /* CPU feature flags. */
811 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
813 /* If we have selected a cpu we are generating instructions for. */
814 static int cpu_arch_tune_set
= 0;
816 /* Cpu we are generating instructions for. */
817 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
819 /* CPU feature flags of cpu we are generating instructions for. */
820 static i386_cpu_flags cpu_arch_tune_flags
;
822 /* CPU instruction set architecture used. */
823 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
825 /* CPU feature flags of instruction set architecture used. */
826 i386_cpu_flags cpu_arch_isa_flags
;
828 /* If set, conditional jumps are not automatically promoted to handle
829 larger than a byte offset. */
830 static bool no_cond_jump_promotion
= false;
832 /* This will be set from an expression parser hook if there's any
833 applicable operator involved in an expression. */
836 expr_operator_present
,
840 /* Encode SSE instructions with VEX prefix. */
841 static unsigned int sse2avx
;
843 /* Encode aligned vector move as unaligned vector move. */
844 static unsigned int use_unaligned_vector_move
;
846 /* Maximum permitted vector size. */
847 #define VSZ_DEFAULT VSZ512
848 static unsigned int vector_size
= VSZ_DEFAULT
;
850 /* Encode scalar AVX instructions with specific vector length. */
857 /* Encode VEX WIG instructions with specific vex.w. */
864 /* Encode scalar EVEX LIG instructions with specific vector length. */
872 /* Encode EVEX WIG instructions with specific evex.w. */
879 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
880 static enum rc_type evexrcig
= rne
;
882 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
883 static symbolS
*GOT_symbol
;
885 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
886 unsigned int x86_dwarf2_return_column
;
888 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
889 int x86_cie_data_alignment
;
891 /* Interface to relax_segment.
892 There are 3 major relax states for 386 jump insns because the
893 different types of jumps add different sizes to frags when we're
894 figuring out what sort of jump to choose to reach a given label.
896 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
897 branches which are handled by md_estimate_size_before_relax() and
898 i386_generic_table_relax_frag(). */
901 #define UNCOND_JUMP 0
903 #define COND_JUMP86 2
904 #define BRANCH_PADDING 3
905 #define BRANCH_PREFIX 4
906 #define FUSED_JCC_PADDING 5
911 #define SMALL16 (SMALL | CODE16)
913 #define BIG16 (BIG | CODE16)
917 #define INLINE __inline__
923 #define ENCODE_RELAX_STATE(type, size) \
924 ((relax_substateT) (((type) << 2) | (size)))
925 #define TYPE_FROM_RELAX_STATE(s) \
927 #define DISP_SIZE_FROM_RELAX_STATE(s) \
928 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
930 /* This table is used by relax_frag to promote short jumps to long
931 ones where necessary. SMALL (short) jumps may be promoted to BIG
932 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
933 don't allow a short jump in a 32 bit code segment to be promoted to
934 a 16 bit offset jump because it's slower (requires data size
935 prefix), and doesn't work, unless the destination is in the bottom
936 64k of the code segment (The top 16 bits of eip are zeroed). */
938 const relax_typeS md_relax_table
[] =
941 1) most positive reach of this state,
942 2) most negative reach of this state,
943 3) how many bytes this mode will have in the variable part of the frag
944 4) which index into the table to try if we can't fit into this one. */
946 /* UNCOND_JUMP states. */
947 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
948 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
949 /* dword jmp adds 4 bytes to frag:
950 0 extra opcode bytes, 4 displacement bytes. */
952 /* word jmp adds 2 byte2 to frag:
953 0 extra opcode bytes, 2 displacement bytes. */
956 /* COND_JUMP states. */
957 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
958 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
959 /* dword conditionals adds 5 bytes to frag:
960 1 extra opcode byte, 4 displacement bytes. */
962 /* word conditionals add 3 bytes to frag:
963 1 extra opcode byte, 2 displacement bytes. */
966 /* COND_JUMP86 states. */
967 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
968 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
969 /* dword conditionals adds 5 bytes to frag:
970 1 extra opcode byte, 4 displacement bytes. */
972 /* word conditionals add 4 bytes to frag:
973 1 displacement byte and a 3 byte long branch insn. */
977 #define ARCH(n, t, f, s) \
978 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
980 #define SUBARCH(n, e, d, s) \
981 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
982 CPU_ ## d ## _FLAGS }
983 #define VECARCH(n, e, d, v) \
984 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
985 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
987 static const arch_entry cpu_arch
[] =
989 /* Do not replace the first two entries - i386_target_format() and
990 set_cpu_arch() rely on them being there in this order. */
991 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
992 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
993 ARCH (i8086
, UNKNOWN
, NONE
, false),
994 ARCH (i186
, UNKNOWN
, 186, false),
995 ARCH (i286
, UNKNOWN
, 286, false),
996 ARCH (i386
, I386
, 386, false),
997 ARCH (i486
, I486
, 486, false),
998 ARCH (i586
, PENTIUM
, 586, false),
999 ARCH (i686
, PENTIUMPRO
, 686, false),
1000 ARCH (pentium
, PENTIUM
, 586, false),
1001 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
1002 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
1003 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
1004 ARCH (pentium4
, PENTIUM4
, P4
, false),
1005 ARCH (prescott
, NOCONA
, CORE
, false),
1006 ARCH (nocona
, NOCONA
, NOCONA
, false),
1007 ARCH (yonah
, CORE
, CORE
, true),
1008 ARCH (core
, CORE
, CORE
, false),
1009 ARCH (merom
, CORE2
, CORE2
, true),
1010 ARCH (core2
, CORE2
, CORE2
, false),
1011 ARCH (corei7
, COREI7
, COREI7
, false),
1012 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1013 ARCH (k6
, K6
, K6
, false),
1014 ARCH (k6_2
, K6
, K6_2
, false),
1015 ARCH (athlon
, ATHLON
, ATHLON
, false),
1016 ARCH (sledgehammer
, K8
, K8
, true),
1017 ARCH (opteron
, K8
, K8
, false),
1018 ARCH (k8
, K8
, K8
, false),
1019 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1020 ARCH (bdver1
, BD
, BDVER1
, false),
1021 ARCH (bdver2
, BD
, BDVER2
, false),
1022 ARCH (bdver3
, BD
, BDVER3
, false),
1023 ARCH (bdver4
, BD
, BDVER4
, false),
1024 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1025 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1026 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1027 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1028 ARCH (btver1
, BT
, BTVER1
, false),
1029 ARCH (btver2
, BT
, BTVER2
, false),
1031 SUBARCH (8087, 8087, ANY_8087
, false),
1032 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1033 SUBARCH (287, 287, ANY_287
, false),
1034 SUBARCH (387, 387, ANY_387
, false),
1035 SUBARCH (687, 687, ANY_687
, false),
1036 SUBARCH (cmov
, CMOV
, CMOV
, false),
1037 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1038 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1039 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1040 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1041 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1042 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1043 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1044 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1045 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1046 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1047 VECARCH (avx
, AVX
, ANY_AVX
, reset
),
1048 VECARCH (avx2
, AVX2
, ANY_AVX2
, reset
),
1049 VECARCH (avx512f
, AVX512F
, ANY_AVX512F
, reset
),
1050 VECARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, reset
),
1051 VECARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, reset
),
1052 VECARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, reset
),
1053 VECARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, reset
),
1054 VECARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, reset
),
1055 VECARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, reset
),
1056 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1057 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1058 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1059 SUBARCH (smx
, SMX
, SMX
, false),
1060 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1061 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1062 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1063 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1064 SUBARCH (aes
, AES
, ANY_AES
, false),
1065 SUBARCH (pclmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, false),
1066 SUBARCH (clmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, true),
1067 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1068 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1069 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1070 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1071 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1072 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1073 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1074 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1075 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1076 SUBARCH (cx16
, CX16
, CX16
, false),
1077 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1078 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1079 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1080 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1081 SUBARCH (hle
, HLE
, HLE
, false),
1082 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1083 SUBARCH (tsx
, TSX
, TSX
, false),
1084 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1085 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1086 SUBARCH (nop
, NOP
, NOP
, false),
1087 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1088 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1089 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1090 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1091 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1092 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1093 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1094 SUBARCH (abm
, ABM
, ABM
, false),
1095 SUBARCH (bmi
, BMI
, BMI
, false),
1096 SUBARCH (tbm
, TBM
, TBM
, false),
1097 SUBARCH (adx
, ADX
, ADX
, false),
1098 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1099 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1100 SUBARCH (smap
, SMAP
, SMAP
, false),
1101 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1102 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1103 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1104 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1105 SUBARCH (se1
, SE1
, SE1
, false),
1106 SUBARCH (clwb
, CLWB
, CLWB
, false),
1107 VECARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, reset
),
1108 VECARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, reset
),
1109 VECARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, reset
),
1110 VECARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, reset
),
1111 VECARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, reset
),
1112 VECARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, reset
),
1113 VECARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, reset
),
1114 VECARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, reset
),
1115 VECARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, reset
),
1116 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1117 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1118 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1119 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1120 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1121 SUBARCH (ibt
, IBT
, IBT
, false),
1122 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1123 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1124 VECARCH (vaes
, VAES
, ANY_VAES
, reset
),
1125 VECARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, reset
),
1126 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1127 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1128 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1129 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1130 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1131 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1132 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1133 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1134 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1135 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1136 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1137 VECARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, reset
),
1138 VECARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1139 ANY_AVX512_VP2INTERSECT
, reset
),
1140 SUBARCH (tdx
, TDX
, TDX
, false),
1141 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1142 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1143 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1144 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1145 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1146 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1147 SUBARCH (kl
, KL
, ANY_KL
, false),
1148 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1149 SUBARCH (uintr
, UINTR
, UINTR
, false),
1150 SUBARCH (hreset
, HRESET
, HRESET
, false),
1151 VECARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, reset
),
1152 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1153 VECARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, reset
),
1154 VECARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, reset
),
1155 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1156 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1157 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1158 VECARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, reset
),
1159 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1160 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1161 SUBARCH (fred
, FRED
, ANY_FRED
, false),
1162 SUBARCH (lkgs
, LKGS
, ANY_LKGS
, false),
1163 VECARCH (avx_vnni_int16
, AVX_VNNI_INT16
, ANY_AVX_VNNI_INT16
, reset
),
1164 VECARCH (sha512
, SHA512
, ANY_SHA512
, reset
),
1165 VECARCH (sm3
, SM3
, ANY_SM3
, reset
),
1166 VECARCH (sm4
, SM4
, ANY_SM4
, reset
),
1167 SUBARCH (pbndkb
, PBNDKB
, PBNDKB
, false),
1168 VECARCH (avx10
.1
, AVX10_1
, ANY_AVX512F
, set
),
1175 /* Like s_lcomm_internal in gas/read.c but the alignment string
1176 is allowed to be optional. */
1179 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1186 && *input_line_pointer
== ',')
1188 align
= parse_align (needs_align
- 1);
1190 if (align
== (addressT
) -1)
1205 bss_alloc (symbolP
, size
, align
);
1210 pe_lcomm (int needs_align
)
1212 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1216 const pseudo_typeS md_pseudo_table
[] =
1218 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1219 {"align", s_align_bytes
, 0},
1221 {"align", s_align_ptwo
, 0},
1223 {"arch", set_cpu_arch
, 0},
1227 {"lcomm", pe_lcomm
, 1},
1229 {"ffloat", float_cons
, 'f'},
1230 {"dfloat", float_cons
, 'd'},
1231 {"tfloat", float_cons
, 'x'},
1232 {"hfloat", float_cons
, 'h'},
1233 {"bfloat16", float_cons
, 'b'},
1235 {"slong", signed_cons
, 4},
1236 {"insn", s_insn
, 0},
1237 {"noopt", s_ignore
, 0},
1238 {"optim", s_ignore
, 0},
1239 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1240 {"code16", set_code_flag
, CODE_16BIT
},
1241 {"code32", set_code_flag
, CODE_32BIT
},
1243 {"code64", set_code_flag
, CODE_64BIT
},
1245 {"intel_syntax", set_intel_syntax
, 1},
1246 {"att_syntax", set_intel_syntax
, 0},
1247 {"intel_mnemonic", set_intel_mnemonic
, 1},
1248 {"att_mnemonic", set_intel_mnemonic
, 0},
1249 {"allow_index_reg", set_allow_index_reg
, 1},
1250 {"disallow_index_reg", set_allow_index_reg
, 0},
1251 {"sse_check", set_check
, 0},
1252 {"operand_check", set_check
, 1},
1253 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1254 {"largecomm", handle_large_common
, 0},
1256 {"file", dwarf2_directive_file
, 0},
1257 {"loc", dwarf2_directive_loc
, 0},
1258 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1261 {"secrel32", pe_directive_secrel
, 0},
1262 {"secidx", pe_directive_secidx
, 0},
1267 /* For interface with expression (). */
1268 extern char *input_line_pointer
;
1270 /* Hash table for instruction mnemonic lookup. */
1271 static htab_t op_hash
;
1273 /* Hash table for register lookup. */
1274 static htab_t reg_hash
;
1276 /* Various efficient no-op patterns for aligning code labels.
1277 Note: Don't try to assemble the instructions in the comments.
1278 0L and 0w are not legal. */
1279 static const unsigned char f32_1
[] =
1281 static const unsigned char f32_2
[] =
1282 {0x66,0x90}; /* xchg %ax,%ax */
1283 static const unsigned char f32_3
[] =
1284 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1285 static const unsigned char f32_4
[] =
1286 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1287 static const unsigned char f32_6
[] =
1288 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1289 static const unsigned char f32_7
[] =
1290 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1291 static const unsigned char f16_3
[] =
1292 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1293 static const unsigned char f16_4
[] =
1294 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1295 static const unsigned char jump_disp8
[] =
1296 {0xeb}; /* jmp disp8 */
1297 static const unsigned char jump32_disp32
[] =
1298 {0xe9}; /* jmp disp32 */
1299 static const unsigned char jump16_disp32
[] =
1300 {0x66,0xe9}; /* jmp disp32 */
1301 /* 32-bit NOPs patterns. */
1302 static const unsigned char *const f32_patt
[] = {
1303 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1305 /* 16-bit NOPs patterns. */
1306 static const unsigned char *const f16_patt
[] = {
1307 f32_1
, f32_2
, f16_3
, f16_4
1309 /* nopl (%[re]ax) */
1310 static const unsigned char alt_3
[] =
1312 /* nopl 0(%[re]ax) */
1313 static const unsigned char alt_4
[] =
1314 {0x0f,0x1f,0x40,0x00};
1315 /* nopl 0(%[re]ax,%[re]ax,1) */
1316 static const unsigned char alt_5
[] =
1317 {0x0f,0x1f,0x44,0x00,0x00};
1318 /* nopw 0(%[re]ax,%[re]ax,1) */
1319 static const unsigned char alt_6
[] =
1320 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1321 /* nopl 0L(%[re]ax) */
1322 static const unsigned char alt_7
[] =
1323 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1324 /* nopl 0L(%[re]ax,%[re]ax,1) */
1325 static const unsigned char alt_8
[] =
1326 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1327 /* nopw 0L(%[re]ax,%[re]ax,1) */
1328 static const unsigned char alt_9
[] =
1329 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1330 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1331 static const unsigned char alt_10
[] =
1332 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1333 /* data16 nopw %cs:0L(%eax,%eax,1) */
1334 static const unsigned char alt_11
[] =
1335 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1336 /* 32-bit and 64-bit NOPs patterns. */
1337 static const unsigned char *const alt_patt
[] = {
1338 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1339 alt_9
, alt_10
, alt_11
1342 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1343 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1346 i386_output_nops (char *where
, const unsigned char *const *patt
,
1347 int count
, int max_single_nop_size
)
1350 /* Place the longer NOP first. */
1353 const unsigned char *nops
;
1355 if (max_single_nop_size
< 1)
1357 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1358 max_single_nop_size
);
1362 nops
= patt
[max_single_nop_size
- 1];
1364 /* Use the smaller one if the requsted one isn't available. */
1367 max_single_nop_size
--;
1368 nops
= patt
[max_single_nop_size
- 1];
1371 last
= count
% max_single_nop_size
;
1374 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1375 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1379 nops
= patt
[last
- 1];
1382 /* Use the smaller one plus one-byte NOP if the needed one
1385 nops
= patt
[last
- 1];
1386 memcpy (where
+ offset
, nops
, last
);
1387 where
[offset
+ last
] = *patt
[0];
1390 memcpy (where
+ offset
, nops
, last
);
1395 fits_in_imm7 (offsetT num
)
1397 return (num
& 0x7f) == num
;
1401 fits_in_imm31 (offsetT num
)
1403 return (num
& 0x7fffffff) == num
;
1406 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1407 single NOP instruction LIMIT. */
1410 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1412 const unsigned char *const *patt
= NULL
;
1413 int max_single_nop_size
;
1414 /* Maximum number of NOPs before switching to jump over NOPs. */
1415 int max_number_of_nops
;
1417 switch (fragP
->fr_type
)
1422 case rs_machine_dependent
:
1423 /* Allow NOP padding for jumps and calls. */
1424 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1425 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1432 /* We need to decide which NOP sequence to use for 32bit and
1433 64bit. When -mtune= is used:
1435 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1436 PROCESSOR_GENERIC32, f32_patt will be used.
1437 2. For the rest, alt_patt will be used.
1439 When -mtune= isn't used, alt_patt will be used if
1440 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1443 When -march= or .arch is used, we can't use anything beyond
1444 cpu_arch_isa_flags. */
1446 if (flag_code
== CODE_16BIT
)
1449 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1450 /* Limit number of NOPs to 2 in 16-bit mode. */
1451 max_number_of_nops
= 2;
1455 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1457 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1458 switch (cpu_arch_tune
)
1460 case PROCESSOR_UNKNOWN
:
1461 /* We use cpu_arch_isa_flags to check if we SHOULD
1462 optimize with nops. */
1463 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1468 case PROCESSOR_PENTIUM4
:
1469 case PROCESSOR_NOCONA
:
1470 case PROCESSOR_CORE
:
1471 case PROCESSOR_CORE2
:
1472 case PROCESSOR_COREI7
:
1473 case PROCESSOR_GENERIC64
:
1475 case PROCESSOR_ATHLON
:
1477 case PROCESSOR_AMDFAM10
:
1479 case PROCESSOR_ZNVER
:
1483 case PROCESSOR_I386
:
1484 case PROCESSOR_I486
:
1485 case PROCESSOR_PENTIUM
:
1486 case PROCESSOR_PENTIUMPRO
:
1487 case PROCESSOR_IAMCU
:
1488 case PROCESSOR_GENERIC32
:
1491 case PROCESSOR_NONE
:
1497 switch (fragP
->tc_frag_data
.tune
)
1499 case PROCESSOR_UNKNOWN
:
1500 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1501 PROCESSOR_UNKNOWN. */
1505 case PROCESSOR_I386
:
1506 case PROCESSOR_I486
:
1507 case PROCESSOR_PENTIUM
:
1508 case PROCESSOR_IAMCU
:
1510 case PROCESSOR_ATHLON
:
1512 case PROCESSOR_AMDFAM10
:
1514 case PROCESSOR_ZNVER
:
1516 case PROCESSOR_GENERIC32
:
1517 /* We use cpu_arch_isa_flags to check if we CAN optimize
1519 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1524 case PROCESSOR_PENTIUMPRO
:
1525 case PROCESSOR_PENTIUM4
:
1526 case PROCESSOR_NOCONA
:
1527 case PROCESSOR_CORE
:
1528 case PROCESSOR_CORE2
:
1529 case PROCESSOR_COREI7
:
1530 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1535 case PROCESSOR_GENERIC64
:
1538 case PROCESSOR_NONE
:
1543 if (patt
== f32_patt
)
1545 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1546 /* Limit number of NOPs to 2 for older processors. */
1547 max_number_of_nops
= 2;
1551 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1552 /* Limit number of NOPs to 7 for newer processors. */
1553 max_number_of_nops
= 7;
1558 limit
= max_single_nop_size
;
1560 if (fragP
->fr_type
== rs_fill_nop
)
1562 /* Output NOPs for .nop directive. */
1563 if (limit
> max_single_nop_size
)
1565 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1566 _("invalid single nop size: %d "
1567 "(expect within [0, %d])"),
1568 limit
, max_single_nop_size
);
1572 else if (fragP
->fr_type
!= rs_machine_dependent
)
1573 fragP
->fr_var
= count
;
1575 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1577 /* Generate jump over NOPs. */
1578 offsetT disp
= count
- 2;
1579 if (fits_in_imm7 (disp
))
1581 /* Use "jmp disp8" if possible. */
1583 where
[0] = jump_disp8
[0];
1589 unsigned int size_of_jump
;
1591 if (flag_code
== CODE_16BIT
)
1593 where
[0] = jump16_disp32
[0];
1594 where
[1] = jump16_disp32
[1];
1599 where
[0] = jump32_disp32
[0];
1603 count
-= size_of_jump
+ 4;
1604 if (!fits_in_imm31 (count
))
1606 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1607 _("jump over nop padding out of range"));
1611 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1612 where
+= size_of_jump
+ 4;
1616 /* Generate multiple NOPs. */
1617 i386_output_nops (where
, patt
, count
, limit
);
1621 operand_type_all_zero (const union i386_operand_type
*x
)
1623 switch (ARRAY_SIZE(x
->array
))
1634 return !x
->array
[0];
1641 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1643 switch (ARRAY_SIZE(x
->array
))
1659 x
->bitfield
.class = ClassNone
;
1660 x
->bitfield
.instance
= InstanceNone
;
1664 operand_type_equal (const union i386_operand_type
*x
,
1665 const union i386_operand_type
*y
)
1667 switch (ARRAY_SIZE(x
->array
))
1670 if (x
->array
[2] != y
->array
[2])
1674 if (x
->array
[1] != y
->array
[1])
1678 return x
->array
[0] == y
->array
[0];
1686 is_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1690 case Cpu287
: return t
->cpu
.bitfield
.cpu287
;
1691 case Cpu387
: return t
->cpu
.bitfield
.cpu387
;
1692 case Cpu3dnow
: return t
->cpu
.bitfield
.cpu3dnow
;
1693 case Cpu3dnowA
: return t
->cpu
.bitfield
.cpu3dnowa
;
1694 case CpuAVX
: return t
->cpu
.bitfield
.cpuavx
;
1695 case CpuHLE
: return t
->cpu
.bitfield
.cpuhle
;
1696 case CpuAVX512F
: return t
->cpu
.bitfield
.cpuavx512f
;
1697 case CpuAVX512VL
: return t
->cpu
.bitfield
.cpuavx512vl
;
1698 case Cpu64
: return t
->cpu
.bitfield
.cpu64
;
1699 case CpuNo64
: return t
->cpu
.bitfield
.cpuno64
;
1701 gas_assert (cpu
< CpuAttrEnums
);
1703 return t
->cpu
.bitfield
.isa
== cpu
+ 1u;
1706 static i386_cpu_flags
cpu_flags_from_attr (i386_cpu_attr a
)
1708 const unsigned int bps
= sizeof (a
.array
[0]) * CHAR_BIT
;
1709 i386_cpu_flags f
= { .array
[0] = 0 };
1711 switch (ARRAY_SIZE(a
.array
))
1714 f
.array
[CpuAttrEnums
/ bps
]
1715 |= (a
.array
[0] >> CpuIsaBits
) << (CpuAttrEnums
% bps
);
1716 if (CpuAttrEnums
% bps
> CpuIsaBits
)
1717 f
.array
[CpuAttrEnums
/ bps
+ 1]
1718 = (a
.array
[0] >> CpuIsaBits
) >> (bps
- CpuAttrEnums
% bps
);
1725 f
.array
[(a
.bitfield
.isa
- 1) / bps
] |= 1u << ((a
.bitfield
.isa
- 1) % bps
);
1731 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1733 switch (ARRAY_SIZE(x
->array
))
1752 return !x
->array
[0];
1759 cpu_flags_equal (const union i386_cpu_flags
*x
,
1760 const union i386_cpu_flags
*y
)
1762 switch (ARRAY_SIZE(x
->array
))
1765 if (x
->array
[4] != y
->array
[4])
1769 if (x
->array
[3] != y
->array
[3])
1773 if (x
->array
[2] != y
->array
[2])
1777 if (x
->array
[1] != y
->array
[1])
1781 return x
->array
[0] == y
->array
[0];
1789 cpu_flags_check_cpu64 (const insn_template
*t
)
1791 return flag_code
== CODE_64BIT
1792 ? !t
->cpu
.bitfield
.cpuno64
1793 : !t
->cpu
.bitfield
.cpu64
;
1796 static INLINE i386_cpu_flags
1797 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1799 switch (ARRAY_SIZE (x
.array
))
1802 x
.array
[4] &= y
.array
[4];
1805 x
.array
[3] &= y
.array
[3];
1808 x
.array
[2] &= y
.array
[2];
1811 x
.array
[1] &= y
.array
[1];
1814 x
.array
[0] &= y
.array
[0];
1822 static INLINE i386_cpu_flags
1823 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1825 switch (ARRAY_SIZE (x
.array
))
1828 x
.array
[4] |= y
.array
[4];
1831 x
.array
[3] |= y
.array
[3];
1834 x
.array
[2] |= y
.array
[2];
1837 x
.array
[1] |= y
.array
[1];
1840 x
.array
[0] |= y
.array
[0];
1848 static INLINE i386_cpu_flags
1849 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1851 switch (ARRAY_SIZE (x
.array
))
1854 x
.array
[4] &= ~y
.array
[4];
1857 x
.array
[3] &= ~y
.array
[3];
1860 x
.array
[2] &= ~y
.array
[2];
1863 x
.array
[1] &= ~y
.array
[1];
1866 x
.array
[0] &= ~y
.array
[0];
1874 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1876 static INLINE
bool need_evex_encoding (void)
1878 return i
.vec_encoding
== vex_encoding_evex
1879 || i
.vec_encoding
== vex_encoding_evex512
1883 #define CPU_FLAGS_ARCH_MATCH 0x1
1884 #define CPU_FLAGS_64BIT_MATCH 0x2
1886 #define CPU_FLAGS_PERFECT_MATCH \
1887 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1889 /* Return CPU flags match bits. */
1892 cpu_flags_match (const insn_template
*t
)
1894 i386_cpu_flags x
= cpu_flags_from_attr (t
->cpu
);
1895 int match
= cpu_flags_check_cpu64 (t
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1897 x
.bitfield
.cpu64
= 0;
1898 x
.bitfield
.cpuno64
= 0;
1900 if (cpu_flags_all_zero (&x
))
1902 /* This instruction is available on all archs. */
1903 match
|= CPU_FLAGS_ARCH_MATCH
;
1907 /* This instruction is available only on some archs. */
1908 i386_cpu_flags cpu
= cpu_arch_flags
;
1910 /* Dual VEX/EVEX templates may need stripping of one of the flags. */
1911 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
1913 /* Dual AVX/AVX512F templates need to retain AVX512F only if we already
1914 know that EVEX encoding will be needed. */
1915 if ((x
.bitfield
.cpuavx
|| x
.bitfield
.cpuavx2
)
1916 && x
.bitfield
.cpuavx512f
)
1918 if (need_evex_encoding ())
1920 x
.bitfield
.cpuavx
= 0;
1921 x
.bitfield
.cpuavx2
= 0;
1923 /* need_evex_encoding() isn't reliable before operands were
1925 else if (i
.operands
)
1927 x
.bitfield
.cpuavx512f
= 0;
1928 x
.bitfield
.cpuavx512vl
= 0;
1929 if (x
.bitfield
.cpufma
&& !cpu
.bitfield
.cpufma
)
1930 x
.bitfield
.cpuavx
= 0;
1935 /* AVX512VL is no standalone feature - match it and then strip it. */
1936 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1938 x
.bitfield
.cpuavx512vl
= 0;
1940 /* AVX and AVX2 present at the same time express an operand size
1941 dependency - strip AVX2 for the purposes here. The operand size
1942 dependent check occurs in check_vecOperands(). */
1943 if (x
.bitfield
.cpuavx
&& x
.bitfield
.cpuavx2
)
1944 x
.bitfield
.cpuavx2
= 0;
1946 cpu
= cpu_flags_and (x
, cpu
);
1947 if (!cpu_flags_all_zero (&cpu
))
1949 if (t
->cpu
.bitfield
.cpuavx
&& t
->cpu
.bitfield
.cpuavx512f
)
1951 if ((need_evex_encoding ()
1952 ? cpu
.bitfield
.cpuavx512f
1953 : cpu
.bitfield
.cpuavx
)
1954 && (!x
.bitfield
.cpufma
|| cpu
.bitfield
.cpufma
1955 || cpu_arch_flags
.bitfield
.cpuavx512f
)
1956 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1957 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1958 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1959 match
|= CPU_FLAGS_ARCH_MATCH
;
1961 else if (x
.bitfield
.cpuavx
)
1963 /* We need to check a few extra flags with AVX. */
1964 if (cpu
.bitfield
.cpuavx
1965 && (!t
->opcode_modifier
.sse2avx
1966 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1967 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1968 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1969 && (!x
.bitfield
.cpupclmulqdq
|| cpu
.bitfield
.cpupclmulqdq
))
1970 match
|= CPU_FLAGS_ARCH_MATCH
;
1972 else if (x
.bitfield
.cpuavx2
&& cpu
.bitfield
.cpuavx2
)
1973 match
|= CPU_FLAGS_ARCH_MATCH
;
1974 else if (x
.bitfield
.cpuavx512f
)
1976 /* We need to check a few extra flags with AVX512F. */
1977 if (cpu
.bitfield
.cpuavx512f
1978 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
))
1979 match
|= CPU_FLAGS_ARCH_MATCH
;
1982 match
|= CPU_FLAGS_ARCH_MATCH
;
1988 static INLINE i386_operand_type
1989 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1991 if (x
.bitfield
.class != y
.bitfield
.class)
1992 x
.bitfield
.class = ClassNone
;
1993 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1994 x
.bitfield
.instance
= InstanceNone
;
1996 switch (ARRAY_SIZE (x
.array
))
1999 x
.array
[2] &= y
.array
[2];
2002 x
.array
[1] &= y
.array
[1];
2005 x
.array
[0] &= y
.array
[0];
2013 static INLINE i386_operand_type
2014 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
2016 gas_assert (y
.bitfield
.class == ClassNone
);
2017 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2019 switch (ARRAY_SIZE (x
.array
))
2022 x
.array
[2] &= ~y
.array
[2];
2025 x
.array
[1] &= ~y
.array
[1];
2028 x
.array
[0] &= ~y
.array
[0];
2036 static INLINE i386_operand_type
2037 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2039 gas_assert (x
.bitfield
.class == ClassNone
||
2040 y
.bitfield
.class == ClassNone
||
2041 x
.bitfield
.class == y
.bitfield
.class);
2042 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2043 y
.bitfield
.instance
== InstanceNone
||
2044 x
.bitfield
.instance
== y
.bitfield
.instance
);
2046 switch (ARRAY_SIZE (x
.array
))
2049 x
.array
[2] |= y
.array
[2];
2052 x
.array
[1] |= y
.array
[1];
2055 x
.array
[0] |= y
.array
[0];
2063 static INLINE i386_operand_type
2064 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2066 gas_assert (y
.bitfield
.class == ClassNone
);
2067 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2069 switch (ARRAY_SIZE (x
.array
))
2072 x
.array
[2] ^= y
.array
[2];
2075 x
.array
[1] ^= y
.array
[1];
2078 x
.array
[0] ^= y
.array
[0];
2086 static const i386_operand_type anydisp
= {
2087 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
2099 operand_type_check (i386_operand_type t
, enum operand_type c
)
2104 return t
.bitfield
.class == Reg
;
2107 return (t
.bitfield
.imm8
2111 || t
.bitfield
.imm32s
2112 || t
.bitfield
.imm64
);
2115 return (t
.bitfield
.disp8
2116 || t
.bitfield
.disp16
2117 || t
.bitfield
.disp32
2118 || t
.bitfield
.disp64
);
2121 return (t
.bitfield
.disp8
2122 || t
.bitfield
.disp16
2123 || t
.bitfield
.disp32
2124 || t
.bitfield
.disp64
2125 || t
.bitfield
.baseindex
);
2134 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2135 between operand GIVEN and opeand WANTED for instruction template T. */
2138 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2141 return !((i
.types
[given
].bitfield
.byte
2142 && !t
->operand_types
[wanted
].bitfield
.byte
)
2143 || (i
.types
[given
].bitfield
.word
2144 && !t
->operand_types
[wanted
].bitfield
.word
)
2145 || (i
.types
[given
].bitfield
.dword
2146 && !t
->operand_types
[wanted
].bitfield
.dword
)
2147 || (i
.types
[given
].bitfield
.qword
2148 && (!t
->operand_types
[wanted
].bitfield
.qword
2149 /* Don't allow 64-bit (memory) operands outside of 64-bit
2150 mode, when they're used where a 64-bit GPR could also
2151 be used. Checking is needed for Intel Syntax only. */
2153 && flag_code
!= CODE_64BIT
2154 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2155 || t
->operand_types
[wanted
].bitfield
.class == Accum
2156 || t
->opcode_modifier
.isstring
))))
2157 || (i
.types
[given
].bitfield
.tbyte
2158 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2161 /* Return 1 if there is no conflict in SIMD register between operand
2162 GIVEN and opeand WANTED for instruction template T. */
2165 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2168 return !((i
.types
[given
].bitfield
.xmmword
2169 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2170 || (i
.types
[given
].bitfield
.ymmword
2171 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2172 || (i
.types
[given
].bitfield
.zmmword
2173 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2174 || (i
.types
[given
].bitfield
.tmmword
2175 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2178 /* Return 1 if there is no conflict in any size between operand GIVEN
2179 and opeand WANTED for instruction template T. */
2182 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2185 return (match_operand_size (t
, wanted
, given
)
2186 && !((i
.types
[given
].bitfield
.unspecified
2187 && !i
.broadcast
.type
2188 && !i
.broadcast
.bytes
2189 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2190 || (i
.types
[given
].bitfield
.fword
2191 && !t
->operand_types
[wanted
].bitfield
.fword
)
2192 /* For scalar opcode templates to allow register and memory
2193 operands at the same time, some special casing is needed
2194 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2195 down-conversion vpmov*. */
2196 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2197 && t
->operand_types
[wanted
].bitfield
.byte
2198 + t
->operand_types
[wanted
].bitfield
.word
2199 + t
->operand_types
[wanted
].bitfield
.dword
2200 + t
->operand_types
[wanted
].bitfield
.qword
2201 > !!t
->opcode_modifier
.broadcast
)
2202 ? (i
.types
[given
].bitfield
.xmmword
2203 || i
.types
[given
].bitfield
.ymmword
2204 || i
.types
[given
].bitfield
.zmmword
)
2205 : !match_simd_size(t
, wanted
, given
))));
2208 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2209 operands for instruction template T, and it has MATCH_REVERSE set if there
2210 is no size conflict on any operands for the template with operands reversed
2211 (and the template allows for reversing in the first place). */
2213 #define MATCH_STRAIGHT 1
2214 #define MATCH_REVERSE 2
2216 static INLINE
unsigned int
2217 operand_size_match (const insn_template
*t
)
2219 unsigned int j
, match
= MATCH_STRAIGHT
;
2221 /* Don't check non-absolute jump instructions. */
2222 if (t
->opcode_modifier
.jump
2223 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2226 /* Check memory and accumulator operand size. */
2227 for (j
= 0; j
< i
.operands
; j
++)
2229 if (i
.types
[j
].bitfield
.class != Reg
2230 && i
.types
[j
].bitfield
.class != RegSIMD
2231 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2234 if (t
->operand_types
[j
].bitfield
.class == Reg
2235 && !match_operand_size (t
, j
, j
))
2241 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2242 && !match_simd_size (t
, j
, j
))
2248 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2249 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2255 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2262 if (!t
->opcode_modifier
.d
)
2265 /* Check reverse. */
2266 gas_assert (i
.operands
>= 2);
2268 for (j
= 0; j
< i
.operands
; j
++)
2270 unsigned int given
= i
.operands
- j
- 1;
2272 /* For FMA4 and XOP insns VEX.W controls just the first two
2273 register operands. */
2274 if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
2275 given
= j
< 2 ? 1 - j
: j
;
2277 if (t
->operand_types
[j
].bitfield
.class == Reg
2278 && !match_operand_size (t
, j
, given
))
2281 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2282 && !match_simd_size (t
, j
, given
))
2285 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2286 && (!match_operand_size (t
, j
, given
)
2287 || !match_simd_size (t
, j
, given
)))
2290 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2294 return match
| MATCH_REVERSE
;
2298 operand_type_match (i386_operand_type overlap
,
2299 i386_operand_type given
)
2301 i386_operand_type temp
= overlap
;
2303 temp
.bitfield
.unspecified
= 0;
2304 temp
.bitfield
.byte
= 0;
2305 temp
.bitfield
.word
= 0;
2306 temp
.bitfield
.dword
= 0;
2307 temp
.bitfield
.fword
= 0;
2308 temp
.bitfield
.qword
= 0;
2309 temp
.bitfield
.tbyte
= 0;
2310 temp
.bitfield
.xmmword
= 0;
2311 temp
.bitfield
.ymmword
= 0;
2312 temp
.bitfield
.zmmword
= 0;
2313 temp
.bitfield
.tmmword
= 0;
2314 if (operand_type_all_zero (&temp
))
2317 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2321 i
.error
= operand_type_mismatch
;
2325 /* If given types g0 and g1 are registers they must be of the same type
2326 unless the expected operand type register overlap is null.
2327 Intel syntax sized memory operands are also checked here. */
2330 operand_type_register_match (i386_operand_type g0
,
2331 i386_operand_type t0
,
2332 i386_operand_type g1
,
2333 i386_operand_type t1
)
2335 if (g0
.bitfield
.class != Reg
2336 && g0
.bitfield
.class != RegSIMD
2337 && (g0
.bitfield
.unspecified
2338 || !operand_type_check (g0
, anymem
)))
2341 if (g1
.bitfield
.class != Reg
2342 && g1
.bitfield
.class != RegSIMD
2343 && (g1
.bitfield
.unspecified
2344 || !operand_type_check (g1
, anymem
)))
2347 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2348 && g0
.bitfield
.word
== g1
.bitfield
.word
2349 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2350 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2351 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2352 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2353 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2356 /* If expectations overlap in no more than a single size, all is fine. */
2357 g0
= operand_type_and (t0
, t1
);
2358 if (g0
.bitfield
.byte
2362 + g0
.bitfield
.xmmword
2363 + g0
.bitfield
.ymmword
2364 + g0
.bitfield
.zmmword
<= 1)
2367 i
.error
= register_type_mismatch
;
2372 static INLINE
unsigned int
2373 register_number (const reg_entry
*r
)
2375 unsigned int nr
= r
->reg_num
;
2377 if (r
->reg_flags
& RegRex
)
2380 if (r
->reg_flags
& RegVRex
)
2386 static INLINE
unsigned int
2387 mode_from_disp_size (i386_operand_type t
)
2389 if (t
.bitfield
.disp8
)
2391 else if (t
.bitfield
.disp16
2392 || t
.bitfield
.disp32
)
2399 fits_in_signed_byte (addressT num
)
2401 return num
+ 0x80 <= 0xff;
2405 fits_in_unsigned_byte (addressT num
)
2411 fits_in_unsigned_word (addressT num
)
2413 return num
<= 0xffff;
2417 fits_in_signed_word (addressT num
)
2419 return num
+ 0x8000 <= 0xffff;
2423 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2428 return num
+ 0x80000000 <= 0xffffffff;
2430 } /* fits_in_signed_long() */
2433 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2438 return num
<= 0xffffffff;
2440 } /* fits_in_unsigned_long() */
2442 static INLINE valueT
extend_to_32bit_address (addressT num
)
2445 if (fits_in_unsigned_long(num
))
2446 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2448 if (!fits_in_signed_long (num
))
2449 return num
& 0xffffffff;
2456 fits_in_disp8 (offsetT num
)
2458 int shift
= i
.memshift
;
2464 mask
= (1 << shift
) - 1;
2466 /* Return 0 if NUM isn't properly aligned. */
2470 /* Check if NUM will fit in 8bit after shift. */
2471 return fits_in_signed_byte (num
>> shift
);
2475 fits_in_imm4 (offsetT num
)
2477 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2478 return (num
& (i
.vec_encoding
!= vex_encoding_evex
? 0xf : 7)) == num
;
2481 static i386_operand_type
2482 smallest_imm_type (offsetT num
)
2484 i386_operand_type t
;
2486 operand_type_set (&t
, 0);
2487 t
.bitfield
.imm64
= 1;
2489 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2491 /* This code is disabled on the 486 because all the Imm1 forms
2492 in the opcode table are slower on the i486. They're the
2493 versions with the implicitly specified single-position
2494 displacement, which has another syntax if you really want to
2496 t
.bitfield
.imm1
= 1;
2497 t
.bitfield
.imm8
= 1;
2498 t
.bitfield
.imm8s
= 1;
2499 t
.bitfield
.imm16
= 1;
2500 t
.bitfield
.imm32
= 1;
2501 t
.bitfield
.imm32s
= 1;
2503 else if (fits_in_signed_byte (num
))
2505 if (fits_in_unsigned_byte (num
))
2506 t
.bitfield
.imm8
= 1;
2507 t
.bitfield
.imm8s
= 1;
2508 t
.bitfield
.imm16
= 1;
2509 t
.bitfield
.imm32
= 1;
2510 t
.bitfield
.imm32s
= 1;
2512 else if (fits_in_unsigned_byte (num
))
2514 t
.bitfield
.imm8
= 1;
2515 t
.bitfield
.imm16
= 1;
2516 t
.bitfield
.imm32
= 1;
2517 t
.bitfield
.imm32s
= 1;
2519 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2521 t
.bitfield
.imm16
= 1;
2522 t
.bitfield
.imm32
= 1;
2523 t
.bitfield
.imm32s
= 1;
2525 else if (fits_in_signed_long (num
))
2527 t
.bitfield
.imm32
= 1;
2528 t
.bitfield
.imm32s
= 1;
2530 else if (fits_in_unsigned_long (num
))
2531 t
.bitfield
.imm32
= 1;
2537 offset_in_range (offsetT val
, int size
)
2543 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2544 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2546 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2548 case sizeof (val
): return val
;
2552 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2553 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2554 (uint64_t) val
, (uint64_t) (val
& mask
));
2559 static INLINE
const char *insn_name (const insn_template
*t
)
2561 return &i386_mnemonics
[t
->mnem_off
];
2574 a. PREFIX_EXIST if attempting to add a prefix where one from the
2575 same class already exists.
2576 b. PREFIX_LOCK if lock prefix is added.
2577 c. PREFIX_REP if rep/repne prefix is added.
2578 d. PREFIX_DS if ds prefix is added.
2579 e. PREFIX_OTHER if other prefix is added.
2582 static enum PREFIX_GROUP
2583 add_prefix (unsigned int prefix
)
2585 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2588 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2589 && flag_code
== CODE_64BIT
)
2591 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2592 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2593 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2594 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2605 case DS_PREFIX_OPCODE
:
2608 case CS_PREFIX_OPCODE
:
2609 case ES_PREFIX_OPCODE
:
2610 case FS_PREFIX_OPCODE
:
2611 case GS_PREFIX_OPCODE
:
2612 case SS_PREFIX_OPCODE
:
2616 case REPNE_PREFIX_OPCODE
:
2617 case REPE_PREFIX_OPCODE
:
2622 case LOCK_PREFIX_OPCODE
:
2631 case ADDR_PREFIX_OPCODE
:
2635 case DATA_PREFIX_OPCODE
:
2639 if (i
.prefix
[q
] != 0)
2647 i
.prefix
[q
] |= prefix
;
2650 as_bad (_("same type of prefix used twice"));
2656 update_code_flag (int value
, int check
)
2658 PRINTF_LIKE ((*as_error
)) = check
? as_fatal
: as_bad
;
2660 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpu64
)
2662 as_error (_("64bit mode not supported on `%s'."),
2663 cpu_arch_name
? cpu_arch_name
: default_arch
);
2667 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2669 as_error (_("32bit mode not supported on `%s'."),
2670 cpu_arch_name
? cpu_arch_name
: default_arch
);
2674 flag_code
= (enum flag_code
) value
;
2676 stackop_size
= '\0';
2680 set_code_flag (int value
)
2682 update_code_flag (value
, 0);
2686 set_16bit_gcc_code_flag (int new_code_flag
)
2688 flag_code
= (enum flag_code
) new_code_flag
;
2689 if (flag_code
!= CODE_16BIT
)
2691 stackop_size
= LONG_MNEM_SUFFIX
;
2695 set_intel_syntax (int syntax_flag
)
2697 /* Find out if register prefixing is specified. */
2698 int ask_naked_reg
= 0;
2701 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2704 int e
= get_symbol_name (&string
);
2706 if (strcmp (string
, "prefix") == 0)
2708 else if (strcmp (string
, "noprefix") == 0)
2711 as_bad (_("bad argument to syntax directive."));
2712 (void) restore_line_pointer (e
);
2714 demand_empty_rest_of_line ();
2716 intel_syntax
= syntax_flag
;
2718 if (ask_naked_reg
== 0)
2719 allow_naked_reg
= (intel_syntax
2720 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2722 allow_naked_reg
= (ask_naked_reg
< 0);
2724 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2726 register_prefix
= allow_naked_reg
? "" : "%";
2730 set_intel_mnemonic (int mnemonic_flag
)
2732 intel_mnemonic
= mnemonic_flag
;
2736 set_allow_index_reg (int flag
)
2738 allow_index_reg
= flag
;
2742 set_check (int what
)
2744 enum check_kind
*kind
;
2749 kind
= &operand_check
;
2760 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2763 int e
= get_symbol_name (&string
);
2765 if (strcmp (string
, "none") == 0)
2767 else if (strcmp (string
, "warning") == 0)
2768 *kind
= check_warning
;
2769 else if (strcmp (string
, "error") == 0)
2770 *kind
= check_error
;
2772 as_bad (_("bad argument to %s_check directive."), str
);
2773 (void) restore_line_pointer (e
);
2776 as_bad (_("missing argument for %s_check directive"), str
);
2778 demand_empty_rest_of_line ();
2782 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2783 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2785 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2786 static const char *arch
;
2788 /* Intel MCU is only supported on ELF. */
2794 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2795 use default_arch. */
2796 arch
= cpu_arch_name
;
2798 arch
= default_arch
;
2801 /* If we are targeting Intel MCU, we must enable it. */
2802 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2803 == new_flag
.bitfield
.cpuiamcu
)
2806 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2811 extend_cpu_sub_arch_name (const char *name
)
2813 if (cpu_sub_arch_name
)
2814 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2815 ".", name
, (const char *) NULL
);
2817 cpu_sub_arch_name
= concat (".", name
, (const char *) NULL
);
2821 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2823 typedef struct arch_stack_entry
2825 const struct arch_stack_entry
*prev
;
2828 i386_cpu_flags flags
;
2829 i386_cpu_flags isa_flags
;
2830 enum processor_type isa
;
2831 enum flag_code flag_code
;
2832 unsigned int vector_size
;
2834 bool no_cond_jump_promotion
;
2836 static const arch_stack_entry
*arch_stack_top
;
2841 i386_cpu_flags flags
;
2845 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
2847 as_bad (_("missing cpu architecture"));
2848 input_line_pointer
++;
2852 e
= get_symbol_name (&s
);
2855 if (strcmp (string
, "push") == 0)
2857 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2859 top
->name
= cpu_arch_name
;
2860 if (cpu_sub_arch_name
)
2861 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2863 top
->sub_name
= NULL
;
2864 top
->flags
= cpu_arch_flags
;
2865 top
->isa
= cpu_arch_isa
;
2866 top
->isa_flags
= cpu_arch_isa_flags
;
2867 top
->flag_code
= flag_code
;
2868 top
->vector_size
= vector_size
;
2869 top
->stackop_size
= stackop_size
;
2870 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2872 top
->prev
= arch_stack_top
;
2873 arch_stack_top
= top
;
2875 (void) restore_line_pointer (e
);
2876 demand_empty_rest_of_line ();
2880 if (strcmp (string
, "pop") == 0)
2882 const arch_stack_entry
*top
= arch_stack_top
;
2885 as_bad (_(".arch stack is empty"));
2886 else if (top
->flag_code
!= flag_code
2887 || top
->stackop_size
!= stackop_size
)
2889 static const unsigned int bits
[] = {
2895 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2896 bits
[top
->flag_code
],
2897 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2901 arch_stack_top
= top
->prev
;
2903 cpu_arch_name
= top
->name
;
2904 free (cpu_sub_arch_name
);
2905 cpu_sub_arch_name
= top
->sub_name
;
2906 cpu_arch_flags
= top
->flags
;
2907 cpu_arch_isa
= top
->isa
;
2908 cpu_arch_isa_flags
= top
->isa_flags
;
2909 vector_size
= top
->vector_size
;
2910 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2915 (void) restore_line_pointer (e
);
2916 demand_empty_rest_of_line ();
2920 if (strcmp (string
, "default") == 0)
2922 if (strcmp (default_arch
, "iamcu") == 0)
2923 string
= default_arch
;
2926 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2928 cpu_arch_name
= NULL
;
2929 free (cpu_sub_arch_name
);
2930 cpu_sub_arch_name
= NULL
;
2931 cpu_arch_flags
= cpu_unknown_flags
;
2932 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2933 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2934 if (!cpu_arch_tune_set
)
2936 cpu_arch_tune
= cpu_arch_isa
;
2937 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2940 vector_size
= VSZ_DEFAULT
;
2942 j
= ARRAY_SIZE (cpu_arch
) + 1;
2946 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2948 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2949 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2953 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2955 if (flag_code
== CODE_64BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpu64
)
2957 as_bad (_("64bit mode not supported on `%s'."),
2959 (void) restore_line_pointer (e
);
2960 ignore_rest_of_line ();
2964 if (flag_code
== CODE_32BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpui386
)
2966 as_bad (_("32bit mode not supported on `%s'."),
2968 (void) restore_line_pointer (e
);
2969 ignore_rest_of_line ();
2973 cpu_arch_name
= cpu_arch
[j
].name
;
2974 free (cpu_sub_arch_name
);
2975 cpu_sub_arch_name
= NULL
;
2976 cpu_arch_flags
= cpu_arch
[j
].enable
;
2977 cpu_arch_isa
= cpu_arch
[j
].type
;
2978 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2979 if (!cpu_arch_tune_set
)
2981 cpu_arch_tune
= cpu_arch_isa
;
2982 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2985 vector_size
= VSZ_DEFAULT
;
2987 pre_386_16bit_warned
= false;
2991 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
2994 flags
= cpu_flags_or (cpu_arch_flags
, cpu_arch
[j
].enable
);
2996 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2998 extend_cpu_sub_arch_name (string
+ 1);
2999 cpu_arch_flags
= flags
;
3000 cpu_arch_isa_flags
= flags
;
3004 = cpu_flags_or (cpu_arch_isa_flags
, cpu_arch
[j
].enable
);
3006 (void) restore_line_pointer (e
);
3008 switch (cpu_arch
[j
].vsz
)
3014 #ifdef SVR4_COMMENT_CHARS
3015 if (*input_line_pointer
== ':' || *input_line_pointer
== '/')
3017 if (*input_line_pointer
== '/')
3020 ++input_line_pointer
;
3021 switch (get_absolute_expression ())
3023 case 512: vector_size
= VSZ512
; break;
3024 case 256: vector_size
= VSZ256
; break;
3025 case 128: vector_size
= VSZ128
; break;
3027 as_bad (_("Unrecognized vector size specifier"));
3028 ignore_rest_of_line ();
3035 vector_size
= VSZ_DEFAULT
;
3039 demand_empty_rest_of_line ();
3044 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
3046 /* Disable an ISA extension. */
3047 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
3048 if (cpu_arch
[j
].type
== PROCESSOR_NONE
3049 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
3051 flags
= cpu_flags_and_not (cpu_arch_flags
, cpu_arch
[j
].disable
);
3052 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
3054 extend_cpu_sub_arch_name (string
+ 1);
3055 cpu_arch_flags
= flags
;
3056 cpu_arch_isa_flags
= flags
;
3059 if (cpu_arch
[j
].vsz
== vsz_set
)
3060 vector_size
= VSZ_DEFAULT
;
3062 (void) restore_line_pointer (e
);
3063 demand_empty_rest_of_line ();
3068 if (j
== ARRAY_SIZE (cpu_arch
))
3069 as_bad (_("no such architecture: `%s'"), string
);
3071 *input_line_pointer
= e
;
3073 no_cond_jump_promotion
= 0;
3074 if (*input_line_pointer
== ','
3075 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
3077 ++input_line_pointer
;
3078 e
= get_symbol_name (&s
);
3081 if (strcmp (string
, "nojumps") == 0)
3082 no_cond_jump_promotion
= 1;
3083 else if (strcmp (string
, "jumps") == 0)
3086 as_bad (_("no such architecture modifier: `%s'"), string
);
3088 (void) restore_line_pointer (e
);
3091 demand_empty_rest_of_line ();
3094 enum bfd_architecture
3097 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3099 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3100 || flag_code
== CODE_64BIT
)
3101 as_fatal (_("Intel MCU is 32bit ELF only"));
3102 return bfd_arch_iamcu
;
3105 return bfd_arch_i386
;
3111 if (startswith (default_arch
, "x86_64"))
3113 if (default_arch
[6] == '\0')
3114 return bfd_mach_x86_64
;
3116 return bfd_mach_x64_32
;
3118 else if (!strcmp (default_arch
, "i386")
3119 || !strcmp (default_arch
, "iamcu"))
3121 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3123 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3124 as_fatal (_("Intel MCU is 32bit ELF only"));
3125 return bfd_mach_i386_iamcu
;
3128 return bfd_mach_i386_i386
;
3131 as_fatal (_("unknown architecture"));
3134 #include "opcodes/i386-tbl.h"
3139 /* Support pseudo prefixes like {disp32}. */
3140 lex_type
['{'] = LEX_BEGIN_NAME
;
3142 /* Initialize op_hash hash table. */
3143 op_hash
= str_htab_create ();
3146 const insn_template
*const *sets
= i386_op_sets
;
3147 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
3149 /* Type checks to compensate for the conversion through void * which
3150 occurs during hash table insertion / lookup. */
3151 (void) sizeof (sets
== ¤t_templates
->start
);
3152 (void) sizeof (end
== ¤t_templates
->end
);
3153 for (; sets
< end
; ++sets
)
3154 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3155 as_fatal (_("duplicate %s"), insn_name (*sets
));
3158 /* Initialize reg_hash hash table. */
3159 reg_hash
= str_htab_create ();
3161 const reg_entry
*regtab
;
3162 unsigned int regtab_size
= i386_regtab_size
;
3164 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3166 switch (regtab
->reg_type
.bitfield
.class)
3169 if (regtab
->reg_type
.bitfield
.dword
)
3171 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3174 else if (regtab
->reg_type
.bitfield
.tbyte
)
3176 /* There's no point inserting st(<N>) in the hash table, as
3177 parentheses aren't included in register_chars[] anyway. */
3178 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3185 switch (regtab
->reg_num
)
3187 case 0: reg_es
= regtab
; break;
3188 case 2: reg_ss
= regtab
; break;
3189 case 3: reg_ds
= regtab
; break;
3194 if (!regtab
->reg_num
)
3199 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3200 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3204 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3209 for (c
= 0; c
< 256; c
++)
3211 if (ISDIGIT (c
) || ISLOWER (c
))
3213 mnemonic_chars
[c
] = c
;
3214 register_chars
[c
] = c
;
3215 operand_chars
[c
] = c
;
3217 else if (ISUPPER (c
))
3219 mnemonic_chars
[c
] = TOLOWER (c
);
3220 register_chars
[c
] = mnemonic_chars
[c
];
3221 operand_chars
[c
] = c
;
3223 #ifdef SVR4_COMMENT_CHARS
3224 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3225 operand_chars
[c
] = c
;
3229 operand_chars
[c
] = c
;
3232 mnemonic_chars
['_'] = '_';
3233 mnemonic_chars
['-'] = '-';
3234 mnemonic_chars
['.'] = '.';
3236 for (p
= extra_symbol_chars
; *p
!= '\0'; p
++)
3237 operand_chars
[(unsigned char) *p
] = *p
;
3238 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3239 operand_chars
[(unsigned char) *p
] = *p
;
3242 if (flag_code
== CODE_64BIT
)
3244 #if defined (OBJ_COFF) && defined (TE_PE)
3245 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3248 x86_dwarf2_return_column
= 16;
3250 x86_cie_data_alignment
= -8;
3251 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3252 x86_sframe_cfa_sp_reg
= 7;
3253 x86_sframe_cfa_fp_reg
= 6;
3258 x86_dwarf2_return_column
= 8;
3259 x86_cie_data_alignment
= -4;
3262 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3263 can be turned into BRANCH_PREFIX frag. */
3264 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3269 i386_print_statistics (FILE *file
)
3271 htab_print_statistics (file
, "i386 opcode", op_hash
);
3272 htab_print_statistics (file
, "i386 register", reg_hash
);
3278 htab_delete (op_hash
);
3279 htab_delete (reg_hash
);
3284 /* Debugging routines for md_assemble. */
3285 static void pte (insn_template
*);
3286 static void pt (i386_operand_type
);
3287 static void pe (expressionS
*);
3288 static void ps (symbolS
*);
3291 pi (const char *line
, i386_insn
*x
)
3295 fprintf (stdout
, "%s: template ", line
);
3297 fprintf (stdout
, " address: base %s index %s scale %x\n",
3298 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3299 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3300 x
->log2_scale_factor
);
3301 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3302 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3303 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3304 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3305 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3306 (x
->rex
& REX_W
) != 0,
3307 (x
->rex
& REX_R
) != 0,
3308 (x
->rex
& REX_X
) != 0,
3309 (x
->rex
& REX_B
) != 0);
3310 for (j
= 0; j
< x
->operands
; j
++)
3312 fprintf (stdout
, " #%d: ", j
+ 1);
3314 fprintf (stdout
, "\n");
3315 if (x
->types
[j
].bitfield
.class == Reg
3316 || x
->types
[j
].bitfield
.class == RegMMX
3317 || x
->types
[j
].bitfield
.class == RegSIMD
3318 || x
->types
[j
].bitfield
.class == RegMask
3319 || x
->types
[j
].bitfield
.class == SReg
3320 || x
->types
[j
].bitfield
.class == RegCR
3321 || x
->types
[j
].bitfield
.class == RegDR
3322 || x
->types
[j
].bitfield
.class == RegTR
3323 || x
->types
[j
].bitfield
.class == RegBND
)
3324 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3325 if (operand_type_check (x
->types
[j
], imm
))
3327 if (operand_type_check (x
->types
[j
], disp
))
3328 pe (x
->op
[j
].disps
);
3333 pte (insn_template
*t
)
3335 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3336 static const char *const opc_spc
[] = {
3337 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3338 "XOP08", "XOP09", "XOP0A",
3342 fprintf (stdout
, " %d operands ", t
->operands
);
3343 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3344 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3345 if (opc_spc
[t
->opcode_space
])
3346 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3347 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3348 if (t
->extension_opcode
!= None
)
3349 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3350 if (t
->opcode_modifier
.d
)
3351 fprintf (stdout
, "D");
3352 if (t
->opcode_modifier
.w
)
3353 fprintf (stdout
, "W");
3354 fprintf (stdout
, "\n");
3355 for (j
= 0; j
< t
->operands
; j
++)
3357 fprintf (stdout
, " #%d type ", j
+ 1);
3358 pt (t
->operand_types
[j
]);
3359 fprintf (stdout
, "\n");
3366 fprintf (stdout
, " operation %d\n", e
->X_op
);
3367 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3368 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3369 if (e
->X_add_symbol
)
3371 fprintf (stdout
, " add_symbol ");
3372 ps (e
->X_add_symbol
);
3373 fprintf (stdout
, "\n");
3377 fprintf (stdout
, " op_symbol ");
3378 ps (e
->X_op_symbol
);
3379 fprintf (stdout
, "\n");
3386 fprintf (stdout
, "%s type %s%s",
3388 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3389 segment_name (S_GET_SEGMENT (s
)));
3392 static struct type_name
3394 i386_operand_type mask
;
3397 const type_names
[] =
3399 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3400 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3401 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3402 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3403 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3404 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3405 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3406 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3407 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3408 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3409 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3410 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3411 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3412 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3413 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3414 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3415 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3416 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3417 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3418 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3419 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3420 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3421 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3422 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3423 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3424 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3425 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3426 { { .bitfield
= { .class = SReg
} }, "SReg" },
3427 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3428 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3429 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3430 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3431 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3432 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3436 pt (i386_operand_type t
)
3439 i386_operand_type a
;
3441 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3443 a
= operand_type_and (t
, type_names
[j
].mask
);
3444 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3445 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3450 #endif /* DEBUG386 */
3452 static bfd_reloc_code_real_type
3453 reloc (unsigned int size
,
3456 bfd_reloc_code_real_type other
)
3458 if (other
!= NO_RELOC
)
3460 reloc_howto_type
*rel
;
3465 case BFD_RELOC_X86_64_GOT32
:
3466 return BFD_RELOC_X86_64_GOT64
;
3468 case BFD_RELOC_X86_64_GOTPLT64
:
3469 return BFD_RELOC_X86_64_GOTPLT64
;
3471 case BFD_RELOC_X86_64_PLTOFF64
:
3472 return BFD_RELOC_X86_64_PLTOFF64
;
3474 case BFD_RELOC_X86_64_GOTPC32
:
3475 other
= BFD_RELOC_X86_64_GOTPC64
;
3477 case BFD_RELOC_X86_64_GOTPCREL
:
3478 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3480 case BFD_RELOC_X86_64_TPOFF32
:
3481 other
= BFD_RELOC_X86_64_TPOFF64
;
3483 case BFD_RELOC_X86_64_DTPOFF32
:
3484 other
= BFD_RELOC_X86_64_DTPOFF64
;
3490 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3491 if (other
== BFD_RELOC_SIZE32
)
3494 other
= BFD_RELOC_SIZE64
;
3497 as_bad (_("there are no pc-relative size relocations"));
3503 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3504 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3507 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3509 as_bad (_("unknown relocation (%u)"), other
);
3510 else if (size
!= bfd_get_reloc_size (rel
))
3511 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3512 bfd_get_reloc_size (rel
),
3514 else if (pcrel
&& !rel
->pc_relative
)
3515 as_bad (_("non-pc-relative relocation for pc-relative field"));
3516 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3518 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3520 as_bad (_("relocated field and relocation type differ in signedness"));
3529 as_bad (_("there are no unsigned pc-relative relocations"));
3532 case 1: return BFD_RELOC_8_PCREL
;
3533 case 2: return BFD_RELOC_16_PCREL
;
3534 case 4: return BFD_RELOC_32_PCREL
;
3535 case 8: return BFD_RELOC_64_PCREL
;
3537 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3544 case 4: return BFD_RELOC_X86_64_32S
;
3549 case 1: return BFD_RELOC_8
;
3550 case 2: return BFD_RELOC_16
;
3551 case 4: return BFD_RELOC_32
;
3552 case 8: return BFD_RELOC_64
;
3554 as_bad (_("cannot do %s %u byte relocation"),
3555 sign
> 0 ? "signed" : "unsigned", size
);
3561 /* Here we decide which fixups can be adjusted to make them relative to
3562 the beginning of the section instead of the symbol. Basically we need
3563 to make sure that the dynamic relocations are done correctly, so in
3564 some cases we force the original symbol to be used. */
3567 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3569 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3573 /* Don't adjust pc-relative references to merge sections in 64-bit
3575 if (use_rela_relocations
3576 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3580 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3581 and changed later by validate_fix. */
3582 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3583 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3586 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3587 for size relocations. */
3588 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3589 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3590 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3591 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3592 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3593 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3594 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3595 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3596 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3597 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3598 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3599 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3600 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3601 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3602 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3603 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3604 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3605 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3606 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3607 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3608 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3609 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3610 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3611 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3612 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3613 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3614 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3615 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3616 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3617 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3618 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3625 want_disp32 (const insn_template
*t
)
3627 return flag_code
!= CODE_64BIT
3628 || i
.prefix
[ADDR_PREFIX
]
3629 || (t
->mnem_off
== MN_lea
3630 && (!i
.types
[1].bitfield
.qword
3631 || t
->opcode_modifier
.size
== SIZE32
));
3635 intel_float_operand (const char *mnemonic
)
3637 /* Note that the value returned is meaningful only for opcodes with (memory)
3638 operands, hence the code here is free to improperly handle opcodes that
3639 have no operands (for better performance and smaller code). */
3641 if (mnemonic
[0] != 'f')
3642 return 0; /* non-math */
3644 switch (mnemonic
[1])
3646 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3647 the fs segment override prefix not currently handled because no
3648 call path can make opcodes without operands get here */
3650 return 2 /* integer op */;
3652 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3653 return 3; /* fldcw/fldenv */
3656 if (mnemonic
[2] != 'o' /* fnop */)
3657 return 3; /* non-waiting control op */
3660 if (mnemonic
[2] == 's')
3661 return 3; /* frstor/frstpm */
3664 if (mnemonic
[2] == 'a')
3665 return 3; /* fsave */
3666 if (mnemonic
[2] == 't')
3668 switch (mnemonic
[3])
3670 case 'c': /* fstcw */
3671 case 'd': /* fstdw */
3672 case 'e': /* fstenv */
3673 case 's': /* fsts[gw] */
3679 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3680 return 0; /* fxsave/fxrstor are not really math ops */
3688 install_template (const insn_template
*t
)
3694 /* Dual VEX/EVEX templates need stripping one of the possible variants. */
3695 if (t
->opcode_modifier
.vex
&& t
->opcode_modifier
.evex
)
3697 if ((is_cpu (t
, CpuAVX
) || is_cpu (t
, CpuAVX2
))
3698 && is_cpu (t
, CpuAVX512F
))
3700 if (need_evex_encoding ())
3702 i
.tm
.opcode_modifier
.vex
= 0;
3703 i
.tm
.cpu
.bitfield
.cpuavx
= 0;
3704 if (is_cpu (&i
.tm
, CpuAVX2
))
3705 i
.tm
.cpu
.bitfield
.isa
= 0;
3709 i
.tm
.opcode_modifier
.evex
= 0;
3710 i
.tm
.cpu
.bitfield
.cpuavx512f
= 0;
3715 /* Note that for pseudo prefixes this produces a length of 1. But for them
3716 the length isn't interesting at all. */
3717 for (l
= 1; l
< 4; ++l
)
3718 if (!(t
->base_opcode
>> (8 * l
)))
3721 i
.opcode_length
= l
;
3724 /* Build the VEX prefix. */
3727 build_vex_prefix (const insn_template
*t
)
3729 unsigned int register_specifier
;
3730 unsigned int vector_length
;
3733 /* Check register specifier. */
3734 if (i
.vex
.register_specifier
)
3736 register_specifier
=
3737 ~register_number (i
.vex
.register_specifier
) & 0xf;
3738 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3741 register_specifier
= 0xf;
3743 /* Use 2-byte VEX prefix by swapping destination and source operand
3744 if there are more than 1 register operand. */
3745 if (i
.reg_operands
> 1
3746 && i
.vec_encoding
!= vex_encoding_vex3
3747 && i
.dir_encoding
== dir_encoding_default
3748 && i
.operands
== i
.reg_operands
3749 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3750 && i
.tm
.opcode_space
== SPACE_0F
3751 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3756 swap_2_operands (0, i
.operands
- 1);
3758 gas_assert (i
.rm
.mode
== 3);
3762 i
.rm
.regmem
= i
.rm
.reg
;
3765 if (i
.tm
.opcode_modifier
.d
)
3766 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3767 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3768 else /* Use the next insn. */
3769 install_template (&t
[1]);
3772 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3773 are no memory operands and at least 3 register ones. */
3774 if (i
.reg_operands
>= 3
3775 && i
.vec_encoding
!= vex_encoding_vex3
3776 && i
.reg_operands
== i
.operands
- i
.imm_operands
3777 && i
.tm
.opcode_modifier
.vex
3778 && i
.tm
.opcode_modifier
.commutative
3779 && (i
.tm
.opcode_modifier
.sse2avx
3780 || (optimize
> 1 && !i
.no_optimize
))
3782 && i
.vex
.register_specifier
3783 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3785 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3787 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3788 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3789 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3790 &i
.types
[i
.operands
- 3]));
3791 gas_assert (i
.rm
.mode
== 3);
3793 swap_2_operands (xchg
, xchg
+ 1);
3796 xchg
= i
.rm
.regmem
| 8;
3797 i
.rm
.regmem
= ~register_specifier
& 0xf;
3798 gas_assert (!(i
.rm
.regmem
& 8));
3799 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3800 register_specifier
= ~xchg
& 0xf;
3803 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3804 vector_length
= avxscalar
;
3805 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3807 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3813 /* Determine vector length from the last multi-length vector
3816 for (op
= t
->operands
; op
--;)
3817 if (t
->operand_types
[op
].bitfield
.xmmword
3818 && t
->operand_types
[op
].bitfield
.ymmword
3819 && i
.types
[op
].bitfield
.ymmword
)
3826 /* Check the REX.W bit and VEXW. */
3827 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3828 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3829 else if (i
.tm
.opcode_modifier
.vexw
)
3830 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3832 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3834 /* Use 2-byte VEX prefix if possible. */
3836 && i
.vec_encoding
!= vex_encoding_vex3
3837 && i
.tm
.opcode_space
== SPACE_0F
3838 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3840 /* 2-byte VEX prefix. */
3844 i
.vex
.bytes
[0] = 0xc5;
3846 /* Check the REX.R bit. */
3847 r
= (i
.rex
& REX_R
) ? 0 : 1;
3848 i
.vex
.bytes
[1] = (r
<< 7
3849 | register_specifier
<< 3
3850 | vector_length
<< 2
3851 | i
.tm
.opcode_modifier
.opcodeprefix
);
3855 /* 3-byte VEX prefix. */
3858 switch (i
.tm
.opcode_space
)
3863 i
.vex
.bytes
[0] = 0xc4;
3868 i
.vex
.bytes
[0] = 0x8f;
3874 /* The high 3 bits of the second VEX byte are 1's compliment
3875 of RXB bits from REX. */
3876 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3877 | (!dot_insn () ? i
.tm
.opcode_space
3878 : i
.insn_opcode_space
);
3880 i
.vex
.bytes
[2] = (w
<< 7
3881 | register_specifier
<< 3
3882 | vector_length
<< 2
3883 | i
.tm
.opcode_modifier
.opcodeprefix
);
3888 is_evex_encoding (const insn_template
*t
)
3890 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3891 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3892 || t
->opcode_modifier
.sae
;
3896 is_any_vex_encoding (const insn_template
*t
)
3898 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3902 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3904 unsigned int op
, bytes
;
3905 const i386_operand_type
*types
;
3907 if (i
.broadcast
.type
)
3908 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3910 gas_assert (intel_syntax
);
3912 for (op
= 0; op
< t
->operands
; ++op
)
3913 if (t
->operand_types
[op
].bitfield
.baseindex
)
3916 gas_assert (op
< t
->operands
);
3918 if (t
->opcode_modifier
.evex
3919 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3920 switch (i
.broadcast
.bytes
)
3923 if (t
->operand_types
[op
].bitfield
.word
)
3927 if (t
->operand_types
[op
].bitfield
.dword
)
3931 if (t
->operand_types
[op
].bitfield
.qword
)
3935 if (t
->operand_types
[op
].bitfield
.xmmword
)
3937 if (t
->operand_types
[op
].bitfield
.ymmword
)
3939 if (t
->operand_types
[op
].bitfield
.zmmword
)
3946 gas_assert (op
+ 1 < t
->operands
);
3948 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3949 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3950 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3952 types
= &i
.types
[op
+ 1];
3955 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3956 types
= &t
->operand_types
[op
];
3958 if (types
->bitfield
.zmmword
)
3960 else if (types
->bitfield
.ymmword
)
3966 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3967 insn_name (t
), bytes
* 8);
3972 /* Build the EVEX prefix. */
3975 build_evex_prefix (void)
3977 unsigned int register_specifier
, w
;
3978 rex_byte vrex_used
= 0;
3980 /* Check register specifier. */
3981 if (i
.vex
.register_specifier
)
3983 gas_assert ((i
.vrex
& REX_X
) == 0);
3985 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3986 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3987 register_specifier
+= 8;
3988 /* The upper 16 registers are encoded in the fourth byte of the
3990 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3991 i
.vex
.bytes
[3] = 0x8;
3992 register_specifier
= ~register_specifier
& 0xf;
3996 register_specifier
= 0xf;
3998 /* Encode upper 16 vector index register in the fourth byte of
4000 if (!(i
.vrex
& REX_X
))
4001 i
.vex
.bytes
[3] = 0x8;
4006 /* 4 byte EVEX prefix. */
4008 i
.vex
.bytes
[0] = 0x62;
4010 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
4012 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
4013 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
4014 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
4015 | (!dot_insn () ? i
.tm
.opcode_space
4016 : i
.insn_opcode_space
);
4018 /* The fifth bit of the second EVEX byte is 1's compliment of the
4019 REX_R bit in VREX. */
4020 if (!(i
.vrex
& REX_R
))
4021 i
.vex
.bytes
[1] |= 0x10;
4025 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
4027 /* When all operands are registers, the REX_X bit in REX is not
4028 used. We reuse it to encode the upper 16 registers, which is
4029 indicated by the REX_B bit in VREX. The REX_X bit is encoded
4030 as 1's compliment. */
4031 if ((i
.vrex
& REX_B
))
4034 i
.vex
.bytes
[1] &= ~0x40;
4038 /* EVEX instructions shouldn't need the REX prefix. */
4039 i
.vrex
&= ~vrex_used
;
4040 gas_assert (i
.vrex
== 0);
4042 /* Check the REX.W bit and VEXW. */
4043 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
4044 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
4045 else if (i
.tm
.opcode_modifier
.vexw
)
4046 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
4048 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
4050 /* The third byte of the EVEX prefix. */
4051 i
.vex
.bytes
[2] = ((w
<< 7)
4052 | (register_specifier
<< 3)
4053 | 4 /* Encode the U bit. */
4054 | i
.tm
.opcode_modifier
.opcodeprefix
);
4056 /* The fourth byte of the EVEX prefix. */
4057 /* The zeroing-masking bit. */
4058 if (i
.mask
.reg
&& i
.mask
.zeroing
)
4059 i
.vex
.bytes
[3] |= 0x80;
4061 /* Don't always set the broadcast bit if there is no RC. */
4062 if (i
.rounding
.type
== rc_none
)
4064 /* Encode the vector length. */
4065 unsigned int vec_length
;
4067 if (!i
.tm
.opcode_modifier
.evex
4068 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
4072 /* Determine vector length from the last multi-length vector
4074 for (op
= i
.operands
; op
--;)
4075 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
4076 + i
.tm
.operand_types
[op
].bitfield
.ymmword
4077 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
4079 if (i
.types
[op
].bitfield
.zmmword
)
4081 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4084 else if (i
.types
[op
].bitfield
.ymmword
)
4086 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4089 else if (i
.types
[op
].bitfield
.xmmword
)
4091 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4094 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
4095 && op
== i
.broadcast
.operand
)
4097 switch (get_broadcast_bytes (&i
.tm
, true))
4100 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4103 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4106 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4115 if (op
>= MAX_OPERANDS
)
4119 switch (i
.tm
.opcode_modifier
.evex
)
4121 case EVEXLIG
: /* LL' is ignored */
4122 vec_length
= evexlig
<< 5;
4125 vec_length
= 0 << 5;
4128 vec_length
= 1 << 5;
4131 vec_length
= 2 << 5;
4136 vec_length
= 3 << 5;
4144 i
.vex
.bytes
[3] |= vec_length
;
4145 /* Encode the broadcast bit. */
4146 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
4147 i
.vex
.bytes
[3] |= 0x10;
4149 else if (i
.rounding
.type
!= saeonly
)
4150 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4152 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4155 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4159 process_immext (void)
4163 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4164 which is coded in the same place as an 8-bit immediate field
4165 would be. Here we fake an 8-bit immediate operand from the
4166 opcode suffix stored in tm.extension_opcode.
4168 AVX instructions also use this encoding, for some of
4169 3 argument instructions. */
4171 gas_assert (i
.imm_operands
<= 1
4173 || (is_any_vex_encoding (&i
.tm
)
4174 && i
.operands
<= 4)));
4176 exp
= &im_expressions
[i
.imm_operands
++];
4177 i
.op
[i
.operands
].imms
= exp
;
4178 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4180 exp
->X_op
= O_constant
;
4181 exp
->X_add_number
= i
.tm
.extension_opcode
;
4182 i
.tm
.extension_opcode
= None
;
4189 switch (i
.tm
.opcode_modifier
.prefixok
)
4197 as_bad (_("invalid instruction `%s' after `%s'"),
4198 insn_name (&i
.tm
), i
.hle_prefix
);
4201 if (i
.prefix
[LOCK_PREFIX
])
4203 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4207 case PrefixHLERelease
:
4208 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4210 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4214 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4216 as_bad (_("memory destination needed for instruction `%s'"
4217 " after `xrelease'"), insn_name (&i
.tm
));
4224 /* Encode aligned vector move as unaligned vector move. */
4227 encode_with_unaligned_vector_move (void)
4229 switch (i
.tm
.base_opcode
)
4231 case 0x28: /* Load instructions. */
4232 case 0x29: /* Store instructions. */
4233 /* movaps/movapd/vmovaps/vmovapd. */
4234 if (i
.tm
.opcode_space
== SPACE_0F
4235 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4236 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4238 case 0x6f: /* Load instructions. */
4239 case 0x7f: /* Store instructions. */
4240 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4241 if (i
.tm
.opcode_space
== SPACE_0F
4242 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4243 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4250 /* Try the shortest encoding by shortening operand size. */
4253 optimize_encoding (void)
4257 if (i
.tm
.mnem_off
== MN_lea
)
4260 lea symbol, %rN -> mov $symbol, %rN
4261 lea (%rM), %rN -> mov %rM, %rN
4262 lea (,%rM,1), %rN -> mov %rM, %rN
4264 and in 32-bit mode for 16-bit addressing
4266 lea (%rM), %rN -> movzx %rM, %rN
4268 and in 64-bit mode zap 32-bit addressing in favor of using a
4269 32-bit (or less) destination.
4271 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4273 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4274 i
.tm
.opcode_modifier
.size
= SIZE32
;
4275 i
.prefix
[ADDR_PREFIX
] = 0;
4278 if (!i
.index_reg
&& !i
.base_reg
)
4281 lea symbol, %rN -> mov $symbol, %rN
4283 if (flag_code
== CODE_64BIT
)
4285 /* Don't transform a relocation to a 16-bit one. */
4287 && i
.op
[0].disps
->X_op
!= O_constant
4288 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4291 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4292 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4294 i
.tm
.base_opcode
= 0xb8;
4295 i
.tm
.opcode_modifier
.modrm
= 0;
4296 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4297 i
.types
[0].bitfield
.imm32
= 1;
4300 i
.tm
.opcode_modifier
.size
= SIZE16
;
4301 i
.types
[0].bitfield
.imm16
= 1;
4306 /* Subject to further optimization below. */
4307 i
.tm
.base_opcode
= 0xc7;
4308 i
.tm
.extension_opcode
= 0;
4309 i
.types
[0].bitfield
.imm32s
= 1;
4310 i
.types
[0].bitfield
.baseindex
= 0;
4313 /* Outside of 64-bit mode address and operand sizes have to match if
4314 a relocation is involved, as otherwise we wouldn't (currently) or
4315 even couldn't express the relocation correctly. */
4316 else if (i
.op
[0].disps
4317 && i
.op
[0].disps
->X_op
!= O_constant
4318 && ((!i
.prefix
[ADDR_PREFIX
])
4319 != (flag_code
== CODE_32BIT
4320 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4321 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4323 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4324 destination is going to grow encoding size. */
4325 else if (flag_code
== CODE_16BIT
4326 && (optimize
<= 1 || optimize_for_space
)
4327 && !i
.prefix
[ADDR_PREFIX
]
4328 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4332 i
.tm
.base_opcode
= 0xb8;
4333 i
.tm
.opcode_modifier
.modrm
= 0;
4334 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4335 i
.types
[0].bitfield
.imm32
= 1;
4337 i
.types
[0].bitfield
.imm16
= 1;
4340 && i
.op
[0].disps
->X_op
== O_constant
4341 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4342 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4344 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4345 i
.op
[0].disps
->X_add_number
&= 0xffff;
4348 i
.tm
.operand_types
[0] = i
.types
[0];
4352 i
.op
[0].imms
= &im_expressions
[0];
4353 i
.op
[0].imms
->X_op
= O_absent
;
4356 else if (i
.op
[0].disps
4357 && (i
.op
[0].disps
->X_op
!= O_constant
4358 || i
.op
[0].disps
->X_add_number
))
4363 lea (%rM), %rN -> mov %rM, %rN
4364 lea (,%rM,1), %rN -> mov %rM, %rN
4365 lea (%rM), %rN -> movzx %rM, %rN
4367 const reg_entry
*addr_reg
;
4369 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4370 addr_reg
= i
.base_reg
;
4371 else if (!i
.base_reg
4372 && i
.index_reg
->reg_num
!= RegIZ
4373 && !i
.log2_scale_factor
)
4374 addr_reg
= i
.index_reg
;
4378 if (addr_reg
->reg_type
.bitfield
.word
4379 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4381 if (flag_code
!= CODE_32BIT
)
4383 i
.tm
.opcode_space
= SPACE_0F
;
4384 i
.tm
.base_opcode
= 0xb7;
4387 i
.tm
.base_opcode
= 0x8b;
4389 if (addr_reg
->reg_type
.bitfield
.dword
4390 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4391 i
.tm
.opcode_modifier
.size
= SIZE32
;
4393 i
.op
[0].regs
= addr_reg
;
4398 i
.disp_operands
= 0;
4399 i
.prefix
[ADDR_PREFIX
] = 0;
4400 i
.prefix
[SEG_PREFIX
] = 0;
4404 if (optimize_for_space
4405 && i
.tm
.mnem_off
== MN_test
4406 && i
.reg_operands
== 1
4407 && i
.imm_operands
== 1
4408 && !i
.types
[1].bitfield
.byte
4409 && i
.op
[0].imms
->X_op
== O_constant
4410 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4413 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4415 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4416 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4418 i
.types
[1].bitfield
.byte
= 1;
4419 /* Ignore the suffix. */
4421 /* Convert to byte registers. */
4422 if (i
.types
[1].bitfield
.word
)
4424 else if (i
.types
[1].bitfield
.dword
)
4428 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4433 else if (flag_code
== CODE_64BIT
4434 && i
.tm
.opcode_space
== SPACE_BASE
4435 && ((i
.types
[1].bitfield
.qword
4436 && i
.reg_operands
== 1
4437 && i
.imm_operands
== 1
4438 && i
.op
[0].imms
->X_op
== O_constant
4439 && ((i
.tm
.base_opcode
== 0xb8
4440 && i
.tm
.extension_opcode
== None
4441 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4442 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4443 && (i
.tm
.base_opcode
== 0x24
4444 || (i
.tm
.base_opcode
== 0x80
4445 && i
.tm
.extension_opcode
== 0x4)
4446 || i
.tm
.mnem_off
== MN_test
4447 || ((i
.tm
.base_opcode
| 1) == 0xc7
4448 && i
.tm
.extension_opcode
== 0x0)))
4449 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4450 && i
.tm
.base_opcode
== 0x83
4451 && i
.tm
.extension_opcode
== 0x4)))
4452 || (i
.types
[0].bitfield
.qword
4453 && ((i
.reg_operands
== 2
4454 && i
.op
[0].regs
== i
.op
[1].regs
4455 && (i
.tm
.mnem_off
== MN_xor
4456 || i
.tm
.mnem_off
== MN_sub
))
4457 || i
.tm
.mnem_off
== MN_clr
))))
4460 andq $imm31, %r64 -> andl $imm31, %r32
4461 andq $imm7, %r64 -> andl $imm7, %r32
4462 testq $imm31, %r64 -> testl $imm31, %r32
4463 xorq %r64, %r64 -> xorl %r32, %r32
4464 subq %r64, %r64 -> subl %r32, %r32
4465 movq $imm31, %r64 -> movl $imm31, %r32
4466 movq $imm32, %r64 -> movl $imm32, %r32
4468 i
.tm
.opcode_modifier
.size
= SIZE32
;
4471 i
.types
[0].bitfield
.imm32
= 1;
4472 i
.types
[0].bitfield
.imm32s
= 0;
4473 i
.types
[0].bitfield
.imm64
= 0;
4477 i
.types
[0].bitfield
.dword
= 1;
4478 i
.types
[0].bitfield
.qword
= 0;
4480 i
.types
[1].bitfield
.dword
= 1;
4481 i
.types
[1].bitfield
.qword
= 0;
4482 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4485 movq $imm31, %r64 -> movl $imm31, %r32
4486 movq $imm32, %r64 -> movl $imm32, %r32
4488 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4489 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4490 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4491 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4494 movq $imm31, %r64 -> movl $imm31, %r32
4496 i
.tm
.base_opcode
= 0xb8;
4497 i
.tm
.extension_opcode
= None
;
4498 i
.tm
.opcode_modifier
.w
= 0;
4499 i
.tm
.opcode_modifier
.modrm
= 0;
4503 else if (optimize
> 1
4504 && !optimize_for_space
4505 && i
.reg_operands
== 2
4506 && i
.op
[0].regs
== i
.op
[1].regs
4507 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4508 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4511 andb %rN, %rN -> testb %rN, %rN
4512 andw %rN, %rN -> testw %rN, %rN
4513 andq %rN, %rN -> testq %rN, %rN
4514 orb %rN, %rN -> testb %rN, %rN
4515 orw %rN, %rN -> testw %rN, %rN
4516 orq %rN, %rN -> testq %rN, %rN
4518 and outside of 64-bit mode
4520 andl %rN, %rN -> testl %rN, %rN
4521 orl %rN, %rN -> testl %rN, %rN
4523 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4525 else if (i
.tm
.base_opcode
== 0xba
4526 && i
.tm
.opcode_space
== SPACE_0F
4527 && i
.reg_operands
== 1
4528 && i
.op
[0].imms
->X_op
== O_constant
4529 && i
.op
[0].imms
->X_add_number
>= 0)
4532 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4533 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4534 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4536 With <BT> one of bts, btr, and bts also:
4537 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4538 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4543 if (i
.tm
.extension_opcode
!= 4)
4545 if (i
.types
[1].bitfield
.qword
4546 && i
.op
[0].imms
->X_add_number
< 32
4547 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4548 i
.tm
.opcode_modifier
.size
= SIZE32
;
4551 if (i
.types
[1].bitfield
.word
4552 && i
.op
[0].imms
->X_add_number
< 16)
4553 i
.tm
.opcode_modifier
.size
= SIZE32
;
4556 if (i
.op
[0].imms
->X_add_number
< 16)
4557 i
.tm
.opcode_modifier
.size
= SIZE16
;
4561 else if (i
.reg_operands
== 3
4562 && i
.op
[0].regs
== i
.op
[1].regs
4563 && !i
.types
[2].bitfield
.xmmword
4564 && (i
.tm
.opcode_modifier
.vex
4565 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4566 && is_evex_encoding (&i
.tm
)
4567 && (i
.vec_encoding
!= vex_encoding_evex
4568 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4569 || is_cpu (&i
.tm
, CpuAVX512VL
)
4570 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4571 && i
.types
[2].bitfield
.ymmword
))))
4572 && i
.tm
.opcode_space
== SPACE_0F
4573 && ((i
.tm
.base_opcode
| 2) == 0x57
4574 || i
.tm
.base_opcode
== 0xdf
4575 || i
.tm
.base_opcode
== 0xef
4576 || (i
.tm
.base_opcode
| 3) == 0xfb
4577 || i
.tm
.base_opcode
== 0x42
4578 || i
.tm
.base_opcode
== 0x47))
4581 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4583 EVEX VOP %zmmM, %zmmM, %zmmN
4584 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4585 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4586 EVEX VOP %ymmM, %ymmM, %ymmN
4587 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4588 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4589 VEX VOP %ymmM, %ymmM, %ymmN
4590 -> VEX VOP %xmmM, %xmmM, %xmmN
4591 VOP, one of vpandn and vpxor:
4592 VEX VOP %ymmM, %ymmM, %ymmN
4593 -> VEX VOP %xmmM, %xmmM, %xmmN
4594 VOP, one of vpandnd and vpandnq:
4595 EVEX VOP %zmmM, %zmmM, %zmmN
4596 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4597 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4598 EVEX VOP %ymmM, %ymmM, %ymmN
4599 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4600 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4601 VOP, one of vpxord and vpxorq:
4602 EVEX VOP %zmmM, %zmmM, %zmmN
4603 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4604 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4605 EVEX VOP %ymmM, %ymmM, %ymmN
4606 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4607 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4608 VOP, one of kxord and kxorq:
4609 VEX VOP %kM, %kM, %kN
4610 -> VEX kxorw %kM, %kM, %kN
4611 VOP, one of kandnd and kandnq:
4612 VEX VOP %kM, %kM, %kN
4613 -> VEX kandnw %kM, %kM, %kN
4615 if (is_evex_encoding (&i
.tm
))
4617 if (i
.vec_encoding
!= vex_encoding_evex
)
4619 i
.tm
.opcode_modifier
.vex
= VEX128
;
4620 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4621 i
.tm
.opcode_modifier
.evex
= 0;
4622 i
.vec_encoding
= vex_encoding_vex
;
4625 else if (optimize
> 1)
4626 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4630 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4632 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4633 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4636 i
.tm
.opcode_modifier
.vex
= VEX128
;
4638 if (i
.tm
.opcode_modifier
.vex
)
4639 for (j
= 0; j
< 3; j
++)
4641 i
.types
[j
].bitfield
.xmmword
= 1;
4642 i
.types
[j
].bitfield
.ymmword
= 0;
4645 else if (i
.vec_encoding
!= vex_encoding_evex
4646 && !i
.types
[0].bitfield
.zmmword
4647 && !i
.types
[1].bitfield
.zmmword
4649 && !i
.broadcast
.type
4650 && !i
.broadcast
.bytes
4651 && is_evex_encoding (&i
.tm
)
4652 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4653 || (i
.tm
.base_opcode
& ~4) == 0xdb
4654 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4655 && i
.tm
.extension_opcode
== None
)
4658 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4659 vmovdqu32 and vmovdqu64:
4660 EVEX VOP %xmmM, %xmmN
4661 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4662 EVEX VOP %ymmM, %ymmN
4663 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4665 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4667 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4669 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4671 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4672 VOP, one of vpand, vpandn, vpor, vpxor:
4673 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4674 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4675 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4676 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4677 EVEX VOP{d,q} mem, %xmmM, %xmmN
4678 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4679 EVEX VOP{d,q} mem, %ymmM, %ymmN
4680 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4682 for (j
= 0; j
< i
.operands
; j
++)
4683 if (operand_type_check (i
.types
[j
], disp
)
4684 && i
.op
[j
].disps
->X_op
== O_constant
)
4686 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4687 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4688 bytes, we choose EVEX Disp8 over VEX Disp32. */
4689 int evex_disp8
, vex_disp8
;
4690 unsigned int memshift
= i
.memshift
;
4691 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4693 evex_disp8
= fits_in_disp8 (n
);
4695 vex_disp8
= fits_in_disp8 (n
);
4696 if (evex_disp8
!= vex_disp8
)
4698 i
.memshift
= memshift
;
4702 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4705 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4706 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4707 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4708 i
.tm
.opcode_modifier
.vex
4709 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4710 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4711 /* VPAND, VPOR, and VPXOR are commutative. */
4712 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4713 i
.tm
.opcode_modifier
.commutative
= 1;
4714 i
.tm
.opcode_modifier
.evex
= 0;
4715 i
.tm
.opcode_modifier
.masking
= 0;
4716 i
.tm
.opcode_modifier
.broadcast
= 0;
4717 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4720 i
.types
[j
].bitfield
.disp8
4721 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4723 else if (optimize_for_space
4724 && i
.tm
.base_opcode
== 0x29
4725 && i
.tm
.opcode_space
== SPACE_0F38
4726 && i
.operands
== i
.reg_operands
4727 && i
.op
[0].regs
== i
.op
[1].regs
4728 && (!i
.tm
.opcode_modifier
.vex
4729 || !(i
.op
[0].regs
->reg_flags
& RegRex
))
4730 && !is_evex_encoding (&i
.tm
))
4733 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4734 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4735 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4737 i
.tm
.opcode_space
= SPACE_0F
;
4738 i
.tm
.base_opcode
= 0x76;
4740 else if (((i
.tm
.base_opcode
>= 0x64
4741 && i
.tm
.base_opcode
<= 0x66
4742 && i
.tm
.opcode_space
== SPACE_0F
)
4743 || (i
.tm
.base_opcode
== 0x37
4744 && i
.tm
.opcode_space
== SPACE_0F38
))
4745 && i
.operands
== i
.reg_operands
4746 && i
.op
[0].regs
== i
.op
[1].regs
4747 && !is_evex_encoding (&i
.tm
))
4750 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4751 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4752 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4753 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4754 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4755 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4757 i
.tm
.opcode_space
= SPACE_0F
;
4758 i
.tm
.base_opcode
= 0xef;
4759 if (i
.tm
.opcode_modifier
.vex
&& (i
.op
[0].regs
->reg_flags
& RegRex
))
4761 if (i
.operands
== 2)
4763 gas_assert (i
.tm
.opcode_modifier
.sse2avx
);
4769 i
.op
[2].regs
= i
.op
[0].regs
;
4770 i
.types
[2] = i
.types
[0];
4771 i
.flags
[2] = i
.flags
[0];
4772 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4774 i
.tm
.opcode_modifier
.sse2avx
= 0;
4776 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
+ 8;
4777 i
.op
[1].regs
= i
.op
[0].regs
;
4780 else if (optimize_for_space
4781 && i
.tm
.base_opcode
== 0x59
4782 && i
.tm
.opcode_space
== SPACE_0F38
4783 && i
.operands
== i
.reg_operands
4784 && i
.tm
.opcode_modifier
.vex
4785 && !(i
.op
[0].regs
->reg_flags
& RegRex
)
4786 && i
.op
[0].regs
->reg_type
.bitfield
.xmmword
4787 && i
.vec_encoding
!= vex_encoding_vex3
)
4790 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
4792 i
.tm
.opcode_space
= SPACE_0F
;
4793 i
.tm
.base_opcode
= 0x6c;
4794 i
.tm
.opcode_modifier
.vexvvvv
= 1;
4800 i
.op
[2].regs
= i
.op
[0].regs
;
4801 i
.types
[2] = i
.types
[0];
4802 i
.flags
[2] = i
.flags
[0];
4803 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4805 swap_2_operands (1, 2);
4809 /* Return non-zero for load instruction. */
4815 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4816 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4820 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4821 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4822 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4826 if (i
.tm
.mnem_off
== MN_pop
)
4830 if (i
.tm
.opcode_space
== SPACE_BASE
)
4833 if (i
.tm
.base_opcode
== 0x9d
4834 || i
.tm
.base_opcode
== 0x61)
4837 /* movs, cmps, lods, scas. */
4838 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4842 if (base_opcode
== 0x6f
4843 || i
.tm
.base_opcode
== 0xd7)
4845 /* NB: For AMD-specific insns with implicit memory operands,
4846 they're intentionally not covered. */
4849 /* No memory operand. */
4850 if (!i
.mem_operands
)
4855 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4858 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4860 /* test, not, neg, mul, imul, div, idiv. */
4861 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4865 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4868 /* add, or, adc, sbb, and, sub, xor, cmp. */
4869 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4872 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4873 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4874 && i
.tm
.extension_opcode
!= 6)
4877 /* Check for x87 instructions. */
4878 if ((base_opcode
| 6) == 0xdf)
4880 /* Skip fst, fstp, fstenv, fstcw. */
4881 if (i
.tm
.base_opcode
== 0xd9
4882 && (i
.tm
.extension_opcode
== 2
4883 || i
.tm
.extension_opcode
== 3
4884 || i
.tm
.extension_opcode
== 6
4885 || i
.tm
.extension_opcode
== 7))
4888 /* Skip fisttp, fist, fistp, fstp. */
4889 if (i
.tm
.base_opcode
== 0xdb
4890 && (i
.tm
.extension_opcode
== 1
4891 || i
.tm
.extension_opcode
== 2
4892 || i
.tm
.extension_opcode
== 3
4893 || i
.tm
.extension_opcode
== 7))
4896 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4897 if (i
.tm
.base_opcode
== 0xdd
4898 && (i
.tm
.extension_opcode
== 1
4899 || i
.tm
.extension_opcode
== 2
4900 || i
.tm
.extension_opcode
== 3
4901 || i
.tm
.extension_opcode
== 6
4902 || i
.tm
.extension_opcode
== 7))
4905 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4906 if (i
.tm
.base_opcode
== 0xdf
4907 && (i
.tm
.extension_opcode
== 1
4908 || i
.tm
.extension_opcode
== 2
4909 || i
.tm
.extension_opcode
== 3
4910 || i
.tm
.extension_opcode
== 6
4911 || i
.tm
.extension_opcode
== 7))
4917 else if (i
.tm
.opcode_space
== SPACE_0F
)
4919 /* bt, bts, btr, btc. */
4920 if (i
.tm
.base_opcode
== 0xba
4921 && (i
.tm
.extension_opcode
| 3) == 7)
4924 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4925 if (i
.tm
.base_opcode
== 0xc7
4926 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4927 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4928 || i
.tm
.extension_opcode
== 6))
4931 /* fxrstor, ldmxcsr, xrstor. */
4932 if (i
.tm
.base_opcode
== 0xae
4933 && (i
.tm
.extension_opcode
== 1
4934 || i
.tm
.extension_opcode
== 2
4935 || i
.tm
.extension_opcode
== 5))
4938 /* lgdt, lidt, lmsw. */
4939 if (i
.tm
.base_opcode
== 0x01
4940 && (i
.tm
.extension_opcode
== 2
4941 || i
.tm
.extension_opcode
== 3
4942 || i
.tm
.extension_opcode
== 6))
4946 dest
= i
.operands
- 1;
4948 /* Check fake imm8 operand and 3 source operands. */
4949 if ((i
.tm
.opcode_modifier
.immext
4950 || i
.reg_operands
+ i
.mem_operands
== 4)
4951 && i
.types
[dest
].bitfield
.imm8
)
4954 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4955 if (i
.tm
.opcode_space
== SPACE_BASE
4956 && ((base_opcode
| 0x38) == 0x39
4957 || (base_opcode
| 2) == 0x87))
4960 if (i
.tm
.mnem_off
== MN_xadd
)
4963 /* Check for load instruction. */
4964 return (i
.types
[dest
].bitfield
.class != ClassNone
4965 || i
.types
[dest
].bitfield
.instance
== Accum
);
4968 /* Output lfence, 0xfaee8, after instruction. */
4971 insert_lfence_after (void)
4973 if (lfence_after_load
&& load_insn_p ())
4975 /* There are also two REP string instructions that require
4976 special treatment. Specifically, the compare string (CMPS)
4977 and scan string (SCAS) instructions set EFLAGS in a manner
4978 that depends on the data being compared/scanned. When used
4979 with a REP prefix, the number of iterations may therefore
4980 vary depending on this data. If the data is a program secret
4981 chosen by the adversary using an LVI method,
4982 then this data-dependent behavior may leak some aspect
4984 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4985 && i
.prefix
[REP_PREFIX
])
4987 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4990 char *p
= frag_more (3);
4997 /* Output lfence, 0xfaee8, before instruction. */
5000 insert_lfence_before (void)
5004 if (i
.tm
.opcode_space
!= SPACE_BASE
)
5007 if (i
.tm
.base_opcode
== 0xff
5008 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
5010 /* Insert lfence before indirect branch if needed. */
5012 if (lfence_before_indirect_branch
== lfence_branch_none
)
5015 if (i
.operands
!= 1)
5018 if (i
.reg_operands
== 1)
5020 /* Indirect branch via register. Don't insert lfence with
5021 -mlfence-after-load=yes. */
5022 if (lfence_after_load
5023 || lfence_before_indirect_branch
== lfence_branch_memory
)
5026 else if (i
.mem_operands
== 1
5027 && lfence_before_indirect_branch
!= lfence_branch_register
)
5029 as_warn (_("indirect `%s` with memory operand should be avoided"),
5036 if (last_insn
.kind
!= last_insn_other
5037 && last_insn
.seg
== now_seg
)
5039 as_warn_where (last_insn
.file
, last_insn
.line
,
5040 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
5041 last_insn
.name
, insn_name (&i
.tm
));
5052 /* Output or/not/shl and lfence before near ret. */
5053 if (lfence_before_ret
!= lfence_before_ret_none
5054 && (i
.tm
.base_opcode
| 1) == 0xc3)
5056 if (last_insn
.kind
!= last_insn_other
5057 && last_insn
.seg
== now_seg
)
5059 as_warn_where (last_insn
.file
, last_insn
.line
,
5060 _("`%s` skips -mlfence-before-ret on `%s`"),
5061 last_insn
.name
, insn_name (&i
.tm
));
5065 /* Near ret ingore operand size override under CPU64. */
5066 char prefix
= flag_code
== CODE_64BIT
5068 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
5070 if (lfence_before_ret
== lfence_before_ret_not
)
5072 /* not: 0xf71424, may add prefix
5073 for operand size override or 64-bit code. */
5074 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
5088 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
5091 if (lfence_before_ret
== lfence_before_ret_or
)
5093 /* or: 0x830c2400, may add prefix
5094 for operand size override or 64-bit code. */
5100 /* shl: 0xc1242400, may add prefix
5101 for operand size override or 64-bit code. */
5116 /* Shared helper for md_assemble() and s_insn(). */
5117 static void init_globals (void)
5121 memset (&i
, '\0', sizeof (i
));
5122 i
.rounding
.type
= rc_none
;
5123 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5124 i
.reloc
[j
] = NO_RELOC
;
5125 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
5126 memset (im_expressions
, '\0', sizeof (im_expressions
));
5127 save_stack_p
= save_stack
;
5130 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5131 parsing pass. Instead of introducing a rarely use new insn attribute this
5132 utilizes a common pattern between affected templates. It is deemed
5133 acceptable that this will lead to unnecessary pass 2 preparations in a
5134 limited set of cases. */
5135 static INLINE
bool may_need_pass2 (const insn_template
*t
)
5137 return t
->opcode_modifier
.sse2avx
5138 /* Note that all SSE2AVX templates have at least one operand. */
5139 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
5140 : (t
->opcode_space
== SPACE_0F
5141 && (t
->base_opcode
| 1) == 0xbf)
5142 || (t
->opcode_space
== SPACE_BASE
5143 && t
->base_opcode
== 0x63);
5146 /* This is the guts of the machine-dependent assembler. LINE points to a
5147 machine dependent instruction. This function is supposed to emit
5148 the frags/bytes it assembles to. */
5151 md_assemble (char *line
)
5154 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
5155 const char *end
, *pass1_mnem
= NULL
;
5156 enum i386_error pass1_err
= 0;
5157 const insn_template
*t
;
5159 /* Initialize globals. */
5160 current_templates
= NULL
;
5164 /* First parse an instruction mnemonic & call i386_operand for the operands.
5165 We assume that the scrubber has arranged it so that line[0] is the valid
5166 start of a (possibly prefixed) mnemonic. */
5168 end
= parse_insn (line
, mnemonic
, false);
5171 if (pass1_mnem
!= NULL
)
5173 if (i
.error
!= no_error
)
5175 gas_assert (current_templates
!= NULL
);
5176 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
5178 /* No point in trying a 2nd pass - it'll only find the same suffix
5180 mnem_suffix
= i
.suffix
;
5185 t
= current_templates
->start
;
5186 if (may_need_pass2 (t
))
5188 /* Make a copy of the full line in case we need to retry. */
5189 copy
= xstrdup (line
);
5192 mnem_suffix
= i
.suffix
;
5194 line
= parse_operands (line
, mnemonic
);
5202 /* Now we've parsed the mnemonic into a set of templates, and have the
5203 operands at hand. */
5205 /* All Intel opcodes have reversed operands except for "bound", "enter",
5206 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
5207 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
5208 intersegment "jmp" and "call" instructions with 2 immediate operands so
5209 that the immediate segment precedes the offset consistently in Intel and
5213 && (t
->mnem_off
!= MN_bound
)
5214 && !startswith (mnemonic
, "invlpg")
5215 && !startswith (mnemonic
, "monitor")
5216 && !startswith (mnemonic
, "mwait")
5217 && (t
->mnem_off
!= MN_pvalidate
)
5218 && !startswith (mnemonic
, "rmp")
5219 && (t
->mnem_off
!= MN_tpause
)
5220 && (t
->mnem_off
!= MN_umwait
)
5221 && !(i
.operands
== 2
5222 && operand_type_check (i
.types
[0], imm
)
5223 && operand_type_check (i
.types
[1], imm
)))
5226 /* The order of the immediates should be reversed
5227 for 2 immediates extrq and insertq instructions */
5228 if (i
.imm_operands
== 2
5229 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
5230 swap_2_operands (0, 1);
5235 if (i
.disp_operands
&& !optimize_disp (t
))
5238 /* Next, we find a template that matches the given insn,
5239 making sure the overlap of the given operands types is consistent
5240 with the template operand types. */
5242 if (!(t
= match_template (mnem_suffix
)))
5244 const char *err_msg
;
5246 if (copy
&& !mnem_suffix
)
5251 pass1_err
= i
.error
;
5252 pass1_mnem
= insn_name (current_templates
->start
);
5256 /* If a non-/only-64bit template (group) was found in pass 1, and if
5257 _some_ template (group) was found in pass 2, squash pass 1's
5259 if (pass1_err
== unsupported_64bit
)
5265 switch (pass1_mnem
? pass1_err
: i
.error
)
5269 case operand_size_mismatch
:
5270 err_msg
= _("operand size mismatch");
5272 case operand_type_mismatch
:
5273 err_msg
= _("operand type mismatch");
5275 case register_type_mismatch
:
5276 err_msg
= _("register type mismatch");
5278 case number_of_operands_mismatch
:
5279 err_msg
= _("number of operands mismatch");
5281 case invalid_instruction_suffix
:
5282 err_msg
= _("invalid instruction suffix");
5285 err_msg
= _("constant doesn't fit in 4 bits");
5287 case unsupported_with_intel_mnemonic
:
5288 err_msg
= _("unsupported with Intel mnemonic");
5290 case unsupported_syntax
:
5291 err_msg
= _("unsupported syntax");
5294 as_bad (_("unsupported instruction `%s'"),
5295 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5297 case unsupported_on_arch
:
5298 as_bad (_("`%s' is not supported on `%s%s'"),
5299 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5300 cpu_arch_name
? cpu_arch_name
: default_arch
,
5301 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5303 case unsupported_64bit
:
5304 if (ISLOWER (mnem_suffix
))
5306 if (flag_code
== CODE_64BIT
)
5307 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5308 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5311 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5312 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5317 if (flag_code
== CODE_64BIT
)
5318 as_bad (_("`%s' is not supported in 64-bit mode"),
5319 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5321 as_bad (_("`%s' is only supported in 64-bit mode"),
5322 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5325 case invalid_sib_address
:
5326 err_msg
= _("invalid SIB address");
5328 case invalid_vsib_address
:
5329 err_msg
= _("invalid VSIB address");
5331 case invalid_vector_register_set
:
5332 err_msg
= _("mask, index, and destination registers must be distinct");
5334 case invalid_tmm_register_set
:
5335 err_msg
= _("all tmm registers must be distinct");
5337 case invalid_dest_and_src_register_set
:
5338 err_msg
= _("destination and source registers must be distinct");
5340 case unsupported_vector_index_register
:
5341 err_msg
= _("unsupported vector index register");
5343 case unsupported_broadcast
:
5344 err_msg
= _("unsupported broadcast");
5346 case broadcast_needed
:
5347 err_msg
= _("broadcast is needed for operand of such type");
5349 case unsupported_masking
:
5350 err_msg
= _("unsupported masking");
5352 case mask_not_on_destination
:
5353 err_msg
= _("mask not on destination operand");
5355 case no_default_mask
:
5356 err_msg
= _("default mask isn't allowed");
5358 case unsupported_rc_sae
:
5359 err_msg
= _("unsupported static rounding/sae");
5361 case invalid_register_operand
:
5362 err_msg
= _("invalid register operand");
5365 as_bad (_("%s for `%s'"), err_msg
,
5366 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5372 if (sse_check
!= check_none
5373 /* The opcode space check isn't strictly needed; it's there only to
5374 bypass the logic below when easily possible. */
5375 && t
->opcode_space
>= SPACE_0F
5376 && t
->opcode_space
<= SPACE_0F3A
5377 && !is_cpu (&i
.tm
, CpuSSE4a
)
5378 && !is_any_vex_encoding (t
))
5382 for (j
= 0; j
< t
->operands
; ++j
)
5384 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5386 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5390 if (j
>= t
->operands
&& simd
)
5391 (sse_check
== check_warning
5393 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5396 if (i
.tm
.opcode_modifier
.fwait
)
5397 if (!add_prefix (FWAIT_OPCODE
))
5400 /* Check if REP prefix is OK. */
5401 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5403 as_bad (_("invalid instruction `%s' after `%s'"),
5404 insn_name (&i
.tm
), i
.rep_prefix
);
5408 /* Check for lock without a lockable instruction. Destination operand
5409 must be memory unless it is xchg (0x86). */
5410 if (i
.prefix
[LOCK_PREFIX
])
5412 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5413 || i
.mem_operands
== 0
5414 || (i
.tm
.base_opcode
!= 0x86
5415 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5417 as_bad (_("expecting lockable instruction after `lock'"));
5421 /* Zap the redundant prefix from XCHG when optimizing. */
5422 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5423 i
.prefix
[LOCK_PREFIX
] = 0;
5426 if (is_any_vex_encoding (&i
.tm
)
5427 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5428 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5430 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5431 if (i
.prefix
[DATA_PREFIX
])
5433 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5437 /* Don't allow e.g. KMOV in TLS code sequences. */
5438 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5441 case BFD_RELOC_386_TLS_GOTIE
:
5442 case BFD_RELOC_386_TLS_LE_32
:
5443 case BFD_RELOC_X86_64_GOTTPOFF
:
5444 case BFD_RELOC_X86_64_TLSLD
:
5445 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5452 /* Check if HLE prefix is OK. */
5453 if (i
.hle_prefix
&& !check_hle ())
5456 /* Check BND prefix. */
5457 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5458 as_bad (_("expecting valid branch instruction after `bnd'"));
5460 /* Check NOTRACK prefix. */
5461 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5462 as_bad (_("expecting indirect branch instruction after `notrack'"));
5464 if (is_cpu (&i
.tm
, CpuMPX
))
5466 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5467 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5468 else if (flag_code
!= CODE_16BIT
5469 ? i
.prefix
[ADDR_PREFIX
]
5470 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5471 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5474 /* Insert BND prefix. */
5475 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5477 if (!i
.prefix
[BND_PREFIX
])
5478 add_prefix (BND_PREFIX_OPCODE
);
5479 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5481 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5482 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5486 /* Check string instruction segment overrides. */
5487 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5489 gas_assert (i
.mem_operands
);
5490 if (!check_string ())
5492 i
.disp_operands
= 0;
5495 /* The memory operand of (%dx) should be only used with input/output
5496 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5497 if (i
.input_output_operand
5498 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5499 || i
.tm
.opcode_space
!= SPACE_BASE
))
5501 as_bad (_("input/output port address isn't allowed with `%s'"),
5506 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5507 optimize_encoding ();
5509 /* Past optimization there's no need to distinguish vex_encoding_evex and
5510 vex_encoding_evex512 anymore. */
5511 if (i
.vec_encoding
== vex_encoding_evex512
)
5512 i
.vec_encoding
= vex_encoding_evex
;
5514 if (use_unaligned_vector_move
)
5515 encode_with_unaligned_vector_move ();
5517 if (!process_suffix ())
5520 /* Check if IP-relative addressing requirements can be satisfied. */
5521 if (is_cpu (&i
.tm
, CpuPREFETCHI
)
5522 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5523 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5525 /* Update operand types and check extended states. */
5526 for (j
= 0; j
< i
.operands
; j
++)
5528 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5529 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5534 i
.xstate
|= xstate_mmx
;
5537 i
.xstate
|= xstate_mask
;
5540 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5541 i
.xstate
|= xstate_tmm
;
5542 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
5543 && !i
.tm
.opcode_modifier
.vex
5544 && vector_size
>= VSZ512
)
5545 i
.xstate
|= xstate_zmm
;
5546 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
5547 && vector_size
>= VSZ256
)
5548 i
.xstate
|= xstate_ymm
;
5549 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5550 i
.xstate
|= xstate_xmm
;
5555 /* Make still unresolved immediate matches conform to size of immediate
5556 given in i.suffix. */
5557 if (!finalize_imm ())
5560 if (i
.types
[0].bitfield
.imm1
)
5561 i
.imm_operands
= 0; /* kludge for shift insns. */
5563 /* For insns with operands there are more diddles to do to the opcode. */
5566 if (!process_operands ())
5569 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5571 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5572 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5575 if (is_any_vex_encoding (&i
.tm
))
5577 if (!cpu_arch_flags
.bitfield
.cpui286
)
5579 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5584 /* Check for explicit REX prefix. */
5585 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5587 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5591 if (i
.tm
.opcode_modifier
.vex
)
5592 build_vex_prefix (t
);
5594 build_evex_prefix ();
5596 /* The individual REX.RXBW bits got consumed. */
5597 i
.rex
&= REX_OPCODE
;
5600 /* Handle conversion of 'int $3' --> special int3 insn. */
5601 if (i
.tm
.mnem_off
== MN_int
5602 && i
.op
[0].imms
->X_add_number
== 3)
5604 i
.tm
.base_opcode
= INT3_OPCODE
;
5608 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5609 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5610 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5611 && i
.op
[0].disps
->X_op
== O_constant
)
5613 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5614 the absolute address given by the constant. Since ix86 jumps and
5615 calls are pc relative, we need to generate a reloc. */
5616 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5617 i
.op
[0].disps
->X_op
= O_symbol
;
5620 /* For 8 bit registers we need an empty rex prefix. Also if the
5621 instruction already has a prefix, we need to convert old
5622 registers to new ones. */
5624 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5625 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5626 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5627 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5628 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5629 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5634 i
.rex
|= REX_OPCODE
;
5635 for (x
= 0; x
< 2; x
++)
5637 /* Look for 8 bit operand that uses old registers. */
5638 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5639 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5641 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5642 /* In case it is "hi" register, give up. */
5643 if (i
.op
[x
].regs
->reg_num
> 3)
5644 as_bad (_("can't encode register '%s%s' in an "
5645 "instruction requiring REX prefix."),
5646 register_prefix
, i
.op
[x
].regs
->reg_name
);
5648 /* Otherwise it is equivalent to the extended register.
5649 Since the encoding doesn't change this is merely
5650 cosmetic cleanup for debug output. */
5652 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5657 if (i
.rex
== 0 && i
.rex_encoding
)
5659 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5660 that uses legacy register. If it is "hi" register, don't add
5661 the REX_OPCODE byte. */
5663 for (x
= 0; x
< 2; x
++)
5664 if (i
.types
[x
].bitfield
.class == Reg
5665 && i
.types
[x
].bitfield
.byte
5666 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5667 && i
.op
[x
].regs
->reg_num
> 3)
5669 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5670 i
.rex_encoding
= false;
5679 add_prefix (REX_OPCODE
| i
.rex
);
5681 insert_lfence_before ();
5683 /* We are ready to output the insn. */
5686 insert_lfence_after ();
5688 last_insn
.seg
= now_seg
;
5690 if (i
.tm
.opcode_modifier
.isprefix
)
5692 last_insn
.kind
= last_insn_prefix
;
5693 last_insn
.name
= insn_name (&i
.tm
);
5694 last_insn
.file
= as_where (&last_insn
.line
);
5697 last_insn
.kind
= last_insn_other
;
5700 /* The Q suffix is generally valid only in 64-bit mode, with very few
5701 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5702 and fisttp only one of their two templates is matched below: That's
5703 sufficient since other relevant attributes are the same between both
5704 respective templates. */
5705 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5707 return flag_code
== CODE_64BIT
5708 || (t
->opcode_space
== SPACE_BASE
5709 && t
->base_opcode
== 0xdf
5710 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5711 || t
->mnem_off
== MN_cmpxchg8b
;
5715 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5717 const char *l
= line
, *token_start
= l
;
5719 bool pass1
= !current_templates
;
5721 const insn_template
*t
;
5727 /* Pseudo-prefixes start with an opening figure brace. */
5728 if ((*mnem_p
= *l
) == '{')
5733 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5738 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5741 as_bad (_("no such instruction: `%s'"), token_start
);
5746 /* Pseudo-prefixes end with a closing figure brace. */
5747 if (*mnemonic
== '{' && *l
== '}')
5750 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5754 /* Point l at the closing brace if there's no other separator. */
5755 if (*l
!= END_OF_INSN
&& !is_space_char (*l
)
5756 && *l
!= PREFIX_SEPARATOR
)
5759 else if (!is_space_char (*l
)
5760 && *l
!= END_OF_INSN
5762 || (*l
!= PREFIX_SEPARATOR
&& *l
!= ',')))
5766 as_bad (_("invalid character %s in mnemonic"),
5767 output_invalid (*l
));
5770 if (token_start
== l
)
5772 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5773 as_bad (_("expecting prefix; got nothing"));
5775 as_bad (_("expecting mnemonic; got nothing"));
5779 /* Look up instruction (or prefix) via hash table. */
5780 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5782 if (*l
!= END_OF_INSN
5783 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5784 && current_templates
5785 && current_templates
->start
->opcode_modifier
.isprefix
)
5787 if (!cpu_flags_check_cpu64 (current_templates
->start
))
5789 as_bad ((flag_code
!= CODE_64BIT
5790 ? _("`%s' is only supported in 64-bit mode")
5791 : _("`%s' is not supported in 64-bit mode")),
5792 insn_name (current_templates
->start
));
5795 /* If we are in 16-bit mode, do not allow addr16 or data16.
5796 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5797 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5798 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5799 && flag_code
!= CODE_64BIT
5800 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5801 ^ (flag_code
== CODE_16BIT
)))
5803 as_bad (_("redundant %s prefix"),
5804 insn_name (current_templates
->start
));
5808 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5810 /* Handle pseudo prefixes. */
5811 switch (current_templates
->start
->extension_opcode
)
5815 i
.disp_encoding
= disp_encoding_8bit
;
5819 i
.disp_encoding
= disp_encoding_16bit
;
5823 i
.disp_encoding
= disp_encoding_32bit
;
5827 i
.dir_encoding
= dir_encoding_load
;
5831 i
.dir_encoding
= dir_encoding_store
;
5835 i
.vec_encoding
= vex_encoding_vex
;
5839 i
.vec_encoding
= vex_encoding_vex3
;
5843 i
.vec_encoding
= vex_encoding_evex
;
5847 i
.rex_encoding
= true;
5849 case Prefix_NoOptimize
:
5851 i
.no_optimize
= true;
5859 /* Add prefix, checking for repeated prefixes. */
5860 switch (add_prefix (current_templates
->start
->base_opcode
))
5865 if (is_cpu (current_templates
->start
, CpuIBT
))
5866 i
.notrack_prefix
= insn_name (current_templates
->start
);
5869 if (is_cpu (current_templates
->start
, CpuHLE
))
5870 i
.hle_prefix
= insn_name (current_templates
->start
);
5871 else if (is_cpu (current_templates
->start
, CpuMPX
))
5872 i
.bnd_prefix
= insn_name (current_templates
->start
);
5874 i
.rep_prefix
= insn_name (current_templates
->start
);
5880 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5890 if (!current_templates
)
5892 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5893 Check if we should swap operand or force 32bit displacement in
5895 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5896 i
.dir_encoding
= dir_encoding_swap
;
5897 else if (mnem_p
- 3 == dot_p
5900 i
.disp_encoding
= disp_encoding_8bit
;
5901 else if (mnem_p
- 4 == dot_p
5905 i
.disp_encoding
= disp_encoding_32bit
;
5910 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5913 if (!current_templates
|| !pass1
)
5915 current_templates
= NULL
;
5918 if (mnem_p
> mnemonic
)
5920 /* See if we can get a match by trimming off a suffix. */
5923 case WORD_MNEM_SUFFIX
:
5924 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5925 i
.suffix
= SHORT_MNEM_SUFFIX
;
5928 case BYTE_MNEM_SUFFIX
:
5929 case QWORD_MNEM_SUFFIX
:
5930 i
.suffix
= mnem_p
[-1];
5933 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5935 case SHORT_MNEM_SUFFIX
:
5936 case LONG_MNEM_SUFFIX
:
5939 i
.suffix
= mnem_p
[-1];
5942 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5950 if (intel_float_operand (mnemonic
) == 1)
5951 i
.suffix
= SHORT_MNEM_SUFFIX
;
5953 i
.suffix
= LONG_MNEM_SUFFIX
;
5956 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5958 /* For compatibility reasons accept MOVSD and CMPSD without
5959 operands even in AT&T mode. */
5960 else if (*l
== END_OF_INSN
5961 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5965 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5966 if (current_templates
!= NULL
5968 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5969 && current_templates
->start
->opcode_space
5971 && mnem_p
[-2] == 's')
5973 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5974 mnemonic
, mnemonic
);
5975 i
.suffix
= LONG_MNEM_SUFFIX
;
5979 current_templates
= NULL
;
5987 if (!current_templates
)
5990 as_bad (_("no such instruction: `%s'"), token_start
);
5995 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5996 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5998 /* Check for a branch hint. We allow ",pt" and ",pn" for
5999 predict taken and predict not taken respectively.
6000 I'm not sure that branch hints actually do anything on loop
6001 and jcxz insns (JumpByte) for current Pentium4 chips. They
6002 may work in the future and it doesn't hurt to accept them
6004 if (l
[0] == ',' && l
[1] == 'p')
6008 if (!add_prefix (DS_PREFIX_OPCODE
))
6012 else if (l
[2] == 'n')
6014 if (!add_prefix (CS_PREFIX_OPCODE
))
6020 /* Any other comma loses. */
6023 as_bad (_("invalid character %s in mnemonic"),
6024 output_invalid (*l
));
6028 /* Check if instruction is supported on specified architecture. */
6030 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
6032 supported
|= cpu_flags_match (t
);
6034 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
6035 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
6037 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
6043 if (supported
& CPU_FLAGS_64BIT_MATCH
)
6044 i
.error
= unsupported_on_arch
;
6046 i
.error
= unsupported_64bit
;
6053 parse_operands (char *l
, const char *mnemonic
)
6057 /* 1 if operand is pending after ','. */
6058 unsigned int expecting_operand
= 0;
6060 while (*l
!= END_OF_INSN
)
6062 /* Non-zero if operand parens not balanced. */
6063 unsigned int paren_not_balanced
= 0;
6064 /* True if inside double quotes. */
6065 bool in_quotes
= false;
6067 /* Skip optional white space before operand. */
6068 if (is_space_char (*l
))
6070 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
6072 as_bad (_("invalid character %s before operand %d"),
6073 output_invalid (*l
),
6077 token_start
= l
; /* After white space. */
6078 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
6080 if (*l
== END_OF_INSN
)
6084 as_bad (_("unbalanced double quotes in operand %d."),
6088 if (paren_not_balanced
)
6090 know (!intel_syntax
);
6091 as_bad (_("unbalanced parenthesis in operand %d."),
6096 break; /* we are done */
6098 else if (*l
== '\\' && l
[1] == '"')
6101 in_quotes
= !in_quotes
;
6102 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
6104 as_bad (_("invalid character %s in operand %d"),
6105 output_invalid (*l
),
6109 if (!intel_syntax
&& !in_quotes
)
6112 ++paren_not_balanced
;
6114 --paren_not_balanced
;
6118 if (l
!= token_start
)
6119 { /* Yes, we've read in another operand. */
6120 unsigned int operand_ok
;
6121 this_operand
= i
.operands
++;
6122 if (i
.operands
> MAX_OPERANDS
)
6124 as_bad (_("spurious operands; (%d operands/instruction max)"),
6128 i
.types
[this_operand
].bitfield
.unspecified
= 1;
6129 /* Now parse operand adding info to 'i' as we go along. */
6130 END_STRING_AND_SAVE (l
);
6132 if (i
.mem_operands
> 1)
6134 as_bad (_("too many memory references for `%s'"),
6141 i386_intel_operand (token_start
,
6142 intel_float_operand (mnemonic
));
6144 operand_ok
= i386_att_operand (token_start
);
6146 RESTORE_END_STRING (l
);
6152 if (expecting_operand
)
6154 expecting_operand_after_comma
:
6155 as_bad (_("expecting operand after ','; got nothing"));
6160 as_bad (_("expecting operand before ','; got nothing"));
6165 /* Now *l must be either ',' or END_OF_INSN. */
6168 if (*++l
== END_OF_INSN
)
6170 /* Just skip it, if it's \n complain. */
6171 goto expecting_operand_after_comma
;
6173 expecting_operand
= 1;
6180 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
6182 union i386_op temp_op
;
6183 i386_operand_type temp_type
;
6184 unsigned int temp_flags
;
6185 enum bfd_reloc_code_real temp_reloc
;
6187 temp_type
= i
.types
[xchg2
];
6188 i
.types
[xchg2
] = i
.types
[xchg1
];
6189 i
.types
[xchg1
] = temp_type
;
6191 temp_flags
= i
.flags
[xchg2
];
6192 i
.flags
[xchg2
] = i
.flags
[xchg1
];
6193 i
.flags
[xchg1
] = temp_flags
;
6195 temp_op
= i
.op
[xchg2
];
6196 i
.op
[xchg2
] = i
.op
[xchg1
];
6197 i
.op
[xchg1
] = temp_op
;
6199 temp_reloc
= i
.reloc
[xchg2
];
6200 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
6201 i
.reloc
[xchg1
] = temp_reloc
;
6203 temp_flags
= i
.imm_bits
[xchg2
];
6204 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
6205 i
.imm_bits
[xchg1
] = temp_flags
;
6209 if (i
.mask
.operand
== xchg1
)
6210 i
.mask
.operand
= xchg2
;
6211 else if (i
.mask
.operand
== xchg2
)
6212 i
.mask
.operand
= xchg1
;
6214 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6216 if (i
.broadcast
.operand
== xchg1
)
6217 i
.broadcast
.operand
= xchg2
;
6218 else if (i
.broadcast
.operand
== xchg2
)
6219 i
.broadcast
.operand
= xchg1
;
6224 swap_operands (void)
6230 swap_2_operands (1, i
.operands
- 2);
6234 swap_2_operands (0, i
.operands
- 1);
6240 if (i
.mem_operands
== 2)
6242 const reg_entry
*temp_seg
;
6243 temp_seg
= i
.seg
[0];
6244 i
.seg
[0] = i
.seg
[1];
6245 i
.seg
[1] = temp_seg
;
6249 /* Try to ensure constant immediates are represented in the smallest
6254 char guess_suffix
= 0;
6258 guess_suffix
= i
.suffix
;
6259 else if (i
.reg_operands
)
6261 /* Figure out a suffix from the last register operand specified.
6262 We can't do this properly yet, i.e. excluding special register
6263 instances, but the following works for instructions with
6264 immediates. In any case, we can't set i.suffix yet. */
6265 for (op
= i
.operands
; --op
>= 0;)
6266 if (i
.types
[op
].bitfield
.class != Reg
)
6268 else if (i
.types
[op
].bitfield
.byte
)
6270 guess_suffix
= BYTE_MNEM_SUFFIX
;
6273 else if (i
.types
[op
].bitfield
.word
)
6275 guess_suffix
= WORD_MNEM_SUFFIX
;
6278 else if (i
.types
[op
].bitfield
.dword
)
6280 guess_suffix
= LONG_MNEM_SUFFIX
;
6283 else if (i
.types
[op
].bitfield
.qword
)
6285 guess_suffix
= QWORD_MNEM_SUFFIX
;
6289 else if ((flag_code
== CODE_16BIT
)
6290 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
6291 guess_suffix
= WORD_MNEM_SUFFIX
;
6292 else if (flag_code
!= CODE_64BIT
6293 || (!(i
.prefix
[REX_PREFIX
] & REX_W
)
6294 /* A more generic (but also more involved) way of dealing
6295 with the special case(s) would be to go look for
6296 DefaultSize attributes on any of the templates. */
6297 && current_templates
->start
->mnem_off
!= MN_push
))
6298 guess_suffix
= LONG_MNEM_SUFFIX
;
6300 for (op
= i
.operands
; --op
>= 0;)
6301 if (operand_type_check (i
.types
[op
], imm
))
6303 switch (i
.op
[op
].imms
->X_op
)
6306 /* If a suffix is given, this operand may be shortened. */
6307 switch (guess_suffix
)
6309 case LONG_MNEM_SUFFIX
:
6310 i
.types
[op
].bitfield
.imm32
= 1;
6311 i
.types
[op
].bitfield
.imm64
= 1;
6313 case WORD_MNEM_SUFFIX
:
6314 i
.types
[op
].bitfield
.imm16
= 1;
6315 i
.types
[op
].bitfield
.imm32
= 1;
6316 i
.types
[op
].bitfield
.imm32s
= 1;
6317 i
.types
[op
].bitfield
.imm64
= 1;
6319 case BYTE_MNEM_SUFFIX
:
6320 i
.types
[op
].bitfield
.imm8
= 1;
6321 i
.types
[op
].bitfield
.imm8s
= 1;
6322 i
.types
[op
].bitfield
.imm16
= 1;
6323 i
.types
[op
].bitfield
.imm32
= 1;
6324 i
.types
[op
].bitfield
.imm32s
= 1;
6325 i
.types
[op
].bitfield
.imm64
= 1;
6329 /* If this operand is at most 16 bits, convert it
6330 to a signed 16 bit number before trying to see
6331 whether it will fit in an even smaller size.
6332 This allows a 16-bit operand such as $0xffe0 to
6333 be recognised as within Imm8S range. */
6334 if ((i
.types
[op
].bitfield
.imm16
)
6335 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6337 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6338 ^ 0x8000) - 0x8000);
6341 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6342 if ((i
.types
[op
].bitfield
.imm32
)
6343 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6345 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6346 ^ ((offsetT
) 1 << 31))
6347 - ((offsetT
) 1 << 31));
6351 = operand_type_or (i
.types
[op
],
6352 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6354 /* We must avoid matching of Imm32 templates when 64bit
6355 only immediate is available. */
6356 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6357 i
.types
[op
].bitfield
.imm32
= 0;
6364 /* Symbols and expressions. */
6366 /* Convert symbolic operand to proper sizes for matching, but don't
6367 prevent matching a set of insns that only supports sizes other
6368 than those matching the insn suffix. */
6370 i386_operand_type mask
, allowed
;
6371 const insn_template
*t
= current_templates
->start
;
6373 operand_type_set (&mask
, 0);
6374 switch (guess_suffix
)
6376 case QWORD_MNEM_SUFFIX
:
6377 mask
.bitfield
.imm64
= 1;
6378 mask
.bitfield
.imm32s
= 1;
6380 case LONG_MNEM_SUFFIX
:
6381 mask
.bitfield
.imm32
= 1;
6383 case WORD_MNEM_SUFFIX
:
6384 mask
.bitfield
.imm16
= 1;
6386 case BYTE_MNEM_SUFFIX
:
6387 mask
.bitfield
.imm8
= 1;
6393 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6394 while (++t
< current_templates
->end
)
6396 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6397 allowed
= operand_type_and (allowed
, mask
);
6400 if (!operand_type_all_zero (&allowed
))
6401 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6408 /* Try to use the smallest displacement type too. */
6410 optimize_disp (const insn_template
*t
)
6414 if (!want_disp32 (t
)
6415 && (!t
->opcode_modifier
.jump
6416 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6418 for (op
= 0; op
< i
.operands
; ++op
)
6420 const expressionS
*exp
= i
.op
[op
].disps
;
6422 if (!operand_type_check (i
.types
[op
], disp
))
6425 if (exp
->X_op
!= O_constant
)
6428 /* Since displacement is signed extended to 64bit, don't allow
6429 disp32 if it is out of range. */
6430 if (fits_in_signed_long (exp
->X_add_number
))
6433 i
.types
[op
].bitfield
.disp32
= 0;
6434 if (i
.types
[op
].bitfield
.baseindex
)
6436 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6437 (uint64_t) exp
->X_add_number
);
6443 /* Don't optimize displacement for movabs since it only takes 64bit
6445 if (i
.disp_encoding
> disp_encoding_8bit
6446 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6449 for (op
= i
.operands
; op
-- > 0;)
6450 if (operand_type_check (i
.types
[op
], disp
))
6452 if (i
.op
[op
].disps
->X_op
== O_constant
)
6454 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6456 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6458 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6459 i
.op
[op
].disps
= NULL
;
6464 if (i
.types
[op
].bitfield
.disp16
6465 && fits_in_unsigned_word (op_disp
))
6467 /* If this operand is at most 16 bits, convert
6468 to a signed 16 bit number and don't use 64bit
6470 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6471 i
.types
[op
].bitfield
.disp64
= 0;
6475 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6476 if ((flag_code
!= CODE_64BIT
6477 ? i
.types
[op
].bitfield
.disp32
6479 && (!t
->opcode_modifier
.jump
6480 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6481 && fits_in_unsigned_long (op_disp
))
6483 /* If this operand is at most 32 bits, convert
6484 to a signed 32 bit number and don't use 64bit
6486 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6487 i
.types
[op
].bitfield
.disp64
= 0;
6488 i
.types
[op
].bitfield
.disp32
= 1;
6491 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6493 i
.types
[op
].bitfield
.disp64
= 0;
6494 i
.types
[op
].bitfield
.disp32
= 1;
6497 if ((i
.types
[op
].bitfield
.disp32
6498 || i
.types
[op
].bitfield
.disp16
)
6499 && fits_in_disp8 (op_disp
))
6500 i
.types
[op
].bitfield
.disp8
= 1;
6502 i
.op
[op
].disps
->X_add_number
= op_disp
;
6504 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6505 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6507 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6508 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6509 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6512 /* We only support 64bit displacement on constants. */
6513 i
.types
[op
].bitfield
.disp64
= 0;
6519 /* Return 1 if there is a match in broadcast bytes between operand
6520 GIVEN and instruction template T. */
6523 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6525 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6526 && i
.types
[given
].bitfield
.byte
)
6527 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6528 && i
.types
[given
].bitfield
.word
)
6529 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6530 && i
.types
[given
].bitfield
.dword
)
6531 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6532 && i
.types
[given
].bitfield
.qword
));
6535 /* Check if operands are valid for the instruction. */
6538 check_VecOperands (const insn_template
*t
)
6543 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6544 any one operand are implicity requiring AVX512VL support if the actual
6545 operand size is YMMword or XMMword. Since this function runs after
6546 template matching, there's no need to check for YMMword/XMMword in
6548 cpu
= cpu_flags_and (cpu_flags_from_attr (t
->cpu
), avx512
);
6549 if (!cpu_flags_all_zero (&cpu
)
6550 && !is_cpu (t
, CpuAVX512VL
)
6551 && !cpu_arch_flags
.bitfield
.cpuavx512vl
6552 && (!t
->opcode_modifier
.vex
|| need_evex_encoding ()))
6554 for (op
= 0; op
< t
->operands
; ++op
)
6556 if (t
->operand_types
[op
].bitfield
.zmmword
6557 && (i
.types
[op
].bitfield
.ymmword
6558 || i
.types
[op
].bitfield
.xmmword
))
6560 i
.error
= unsupported
;
6566 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6567 requiring AVX2 support if the actual operand size is YMMword. */
6568 if (is_cpu (t
, CpuAVX
) && is_cpu (t
, CpuAVX2
)
6569 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6571 for (op
= 0; op
< t
->operands
; ++op
)
6573 if (t
->operand_types
[op
].bitfield
.xmmword
6574 && i
.types
[op
].bitfield
.ymmword
)
6576 i
.error
= unsupported
;
6582 /* Without VSIB byte, we can't have a vector register for index. */
6583 if (!t
->opcode_modifier
.sib
6585 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6586 || i
.index_reg
->reg_type
.bitfield
.ymmword
6587 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6589 i
.error
= unsupported_vector_index_register
;
6593 /* Check if default mask is allowed. */
6594 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6595 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6597 i
.error
= no_default_mask
;
6601 /* For VSIB byte, we need a vector register for index, and all vector
6602 registers must be distinct. */
6603 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6606 || !((t
->opcode_modifier
.sib
== VECSIB128
6607 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6608 || (t
->opcode_modifier
.sib
== VECSIB256
6609 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6610 || (t
->opcode_modifier
.sib
== VECSIB512
6611 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6613 i
.error
= invalid_vsib_address
;
6617 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6618 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6620 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6621 gas_assert (i
.types
[0].bitfield
.xmmword
6622 || i
.types
[0].bitfield
.ymmword
);
6623 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6624 gas_assert (i
.types
[2].bitfield
.xmmword
6625 || i
.types
[2].bitfield
.ymmword
);
6626 if (operand_check
== check_none
)
6628 if (register_number (i
.op
[0].regs
)
6629 != register_number (i
.index_reg
)
6630 && register_number (i
.op
[2].regs
)
6631 != register_number (i
.index_reg
)
6632 && register_number (i
.op
[0].regs
)
6633 != register_number (i
.op
[2].regs
))
6635 if (operand_check
== check_error
)
6637 i
.error
= invalid_vector_register_set
;
6640 as_warn (_("mask, index, and destination registers should be distinct"));
6642 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6644 if (i
.types
[1].bitfield
.class == RegSIMD
6645 && (i
.types
[1].bitfield
.xmmword
6646 || i
.types
[1].bitfield
.ymmword
6647 || i
.types
[1].bitfield
.zmmword
)
6648 && (register_number (i
.op
[1].regs
)
6649 == register_number (i
.index_reg
)))
6651 if (operand_check
== check_error
)
6653 i
.error
= invalid_vector_register_set
;
6656 if (operand_check
!= check_none
)
6657 as_warn (_("index and destination registers should be distinct"));
6662 /* For AMX instructions with 3 TMM register operands, all operands
6663 must be distinct. */
6664 if (i
.reg_operands
== 3
6665 && t
->operand_types
[0].bitfield
.tmmword
6666 && (i
.op
[0].regs
== i
.op
[1].regs
6667 || i
.op
[0].regs
== i
.op
[2].regs
6668 || i
.op
[1].regs
== i
.op
[2].regs
))
6670 i
.error
= invalid_tmm_register_set
;
6674 /* For some special instructions require that destination must be distinct
6675 from source registers. */
6676 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6678 unsigned int dest_reg
= i
.operands
- 1;
6680 know (i
.operands
>= 3);
6682 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6683 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6684 || (i
.reg_operands
> 2
6685 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6687 i
.error
= invalid_dest_and_src_register_set
;
6692 /* Check if broadcast is supported by the instruction and is applied
6693 to the memory operand. */
6694 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6696 i386_operand_type type
, overlap
;
6698 /* Check if specified broadcast is supported in this instruction,
6699 and its broadcast bytes match the memory operand. */
6700 op
= i
.broadcast
.operand
;
6701 if (!t
->opcode_modifier
.broadcast
6702 || !(i
.flags
[op
] & Operand_Mem
)
6703 || (!i
.types
[op
].bitfield
.unspecified
6704 && !match_broadcast_size (t
, op
)))
6707 i
.error
= unsupported_broadcast
;
6711 operand_type_set (&type
, 0);
6712 switch (get_broadcast_bytes (t
, false))
6715 type
.bitfield
.word
= 1;
6718 type
.bitfield
.dword
= 1;
6721 type
.bitfield
.qword
= 1;
6724 type
.bitfield
.xmmword
= 1;
6727 if (vector_size
< VSZ256
)
6729 type
.bitfield
.ymmword
= 1;
6732 if (vector_size
< VSZ512
)
6734 type
.bitfield
.zmmword
= 1;
6740 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6741 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6742 && t
->operand_types
[op
].bitfield
.byte
6743 + t
->operand_types
[op
].bitfield
.word
6744 + t
->operand_types
[op
].bitfield
.dword
6745 + t
->operand_types
[op
].bitfield
.qword
> 1)
6747 overlap
.bitfield
.xmmword
= 0;
6748 overlap
.bitfield
.ymmword
= 0;
6749 overlap
.bitfield
.zmmword
= 0;
6751 if (operand_type_all_zero (&overlap
))
6754 if (t
->opcode_modifier
.checkoperandsize
)
6758 type
.bitfield
.baseindex
= 1;
6759 for (j
= 0; j
< i
.operands
; ++j
)
6762 && !operand_type_register_match(i
.types
[j
],
6763 t
->operand_types
[j
],
6765 t
->operand_types
[op
]))
6770 /* If broadcast is supported in this instruction, we need to check if
6771 operand of one-element size isn't specified without broadcast. */
6772 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6774 /* Find memory operand. */
6775 for (op
= 0; op
< i
.operands
; op
++)
6776 if (i
.flags
[op
] & Operand_Mem
)
6778 gas_assert (op
< i
.operands
);
6779 /* Check size of the memory operand. */
6780 if (match_broadcast_size (t
, op
))
6782 i
.error
= broadcast_needed
;
6787 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6789 /* Check if requested masking is supported. */
6792 if (!t
->opcode_modifier
.masking
)
6794 i
.error
= unsupported_masking
;
6798 /* Common rules for masking:
6799 - mask register destinations permit only zeroing-masking, without
6800 that actually being expressed by a {z} operand suffix or EVEX.z,
6801 - memory destinations allow only merging-masking,
6802 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
6805 && (t
->operand_types
[t
->operands
- 1].bitfield
.class == RegMask
6806 || (i
.flags
[t
->operands
- 1] & Operand_Mem
)
6807 || t
->opcode_modifier
.sib
))
6809 i
.error
= unsupported_masking
;
6814 /* Check if masking is applied to dest operand. */
6815 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6817 i
.error
= mask_not_on_destination
;
6822 if (i
.rounding
.type
!= rc_none
)
6824 if (!t
->opcode_modifier
.sae
6825 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6828 i
.error
= unsupported_rc_sae
;
6832 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6834 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6836 for (op
= 0; op
< t
->operands
; ++op
)
6837 if (i
.types
[op
].bitfield
.zmmword
)
6839 if (op
>= t
->operands
)
6841 i
.error
= operand_size_mismatch
;
6847 /* Check the special Imm4 cases; must be the first operand. */
6848 if (is_cpu (t
, CpuXOP
) && t
->operands
== 5)
6850 if (i
.op
[0].imms
->X_op
!= O_constant
6851 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6857 /* Turn off Imm<N> so that update_imm won't complain. */
6858 operand_type_set (&i
.types
[0], 0);
6861 /* Check vector Disp8 operand. */
6862 if (t
->opcode_modifier
.disp8memshift
6863 && (!t
->opcode_modifier
.vex
6864 || need_evex_encoding ())
6865 && i
.disp_encoding
<= disp_encoding_8bit
)
6867 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6868 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6869 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6870 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6873 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6876 for (op
= 0; op
< i
.operands
; op
++)
6877 if (i
.flags
[op
] & Operand_Mem
)
6879 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6880 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6881 else if (t
->operand_types
[op
].bitfield
.xmmword
6882 + t
->operand_types
[op
].bitfield
.ymmword
6883 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6884 type
= &t
->operand_types
[op
];
6885 else if (!i
.types
[op
].bitfield
.unspecified
)
6886 type
= &i
.types
[op
];
6887 else /* Ambiguities get resolved elsewhere. */
6888 fallback
= &t
->operand_types
[op
];
6890 else if (i
.types
[op
].bitfield
.class == RegSIMD
6891 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6893 if (i
.types
[op
].bitfield
.zmmword
)
6895 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6897 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6901 if (!type
&& !i
.memshift
)
6905 if (type
->bitfield
.zmmword
)
6907 else if (type
->bitfield
.ymmword
)
6909 else if (type
->bitfield
.xmmword
)
6913 /* For the check in fits_in_disp8(). */
6914 if (i
.memshift
== 0)
6918 for (op
= 0; op
< i
.operands
; op
++)
6919 if (operand_type_check (i
.types
[op
], disp
)
6920 && i
.op
[op
].disps
->X_op
== O_constant
)
6922 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6924 i
.types
[op
].bitfield
.disp8
= 1;
6927 i
.types
[op
].bitfield
.disp8
= 0;
6936 /* Check if encoding requirements are met by the instruction. */
6939 VEX_check_encoding (const insn_template
*t
)
6941 if (i
.vec_encoding
== vex_encoding_error
)
6943 i
.error
= unsupported
;
6947 /* Vector size restrictions. */
6948 if ((vector_size
< VSZ512
6949 && (t
->opcode_modifier
.evex
== EVEX512
6950 || t
->opcode_modifier
.vsz
>= VSZ512
))
6951 || (vector_size
< VSZ256
6952 && (t
->opcode_modifier
.evex
== EVEX256
6953 || t
->opcode_modifier
.vex
== VEX256
6954 || t
->opcode_modifier
.vsz
>= VSZ256
)))
6956 i
.error
= unsupported
;
6960 if (i
.vec_encoding
== vex_encoding_evex
6961 || i
.vec_encoding
== vex_encoding_evex512
)
6963 /* This instruction must be encoded with EVEX prefix. */
6964 if (!is_evex_encoding (t
))
6966 i
.error
= unsupported
;
6972 if (!t
->opcode_modifier
.vex
)
6974 /* This instruction template doesn't have VEX prefix. */
6975 if (i
.vec_encoding
!= vex_encoding_default
)
6977 i
.error
= unsupported
;
6986 /* Helper function for the progress() macro in match_template(). */
6987 static INLINE
enum i386_error
progress (enum i386_error
new,
6988 enum i386_error last
,
6989 unsigned int line
, unsigned int *line_p
)
6991 if (line
<= *line_p
)
6997 static const insn_template
*
6998 match_template (char mnem_suffix
)
7000 /* Points to template once we've found it. */
7001 const insn_template
*t
;
7002 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
7003 i386_operand_type overlap4
;
7004 unsigned int found_reverse_match
;
7005 i386_operand_type operand_types
[MAX_OPERANDS
];
7006 int addr_prefix_disp
;
7007 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
7008 enum i386_error specific_error
= number_of_operands_mismatch
;
7009 #define progress(err) progress (err, specific_error, __LINE__, &errline)
7011 #if MAX_OPERANDS != 5
7012 # error "MAX_OPERANDS must be 5."
7015 found_reverse_match
= 0;
7016 addr_prefix_disp
= -1;
7018 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
7020 addr_prefix_disp
= -1;
7021 found_reverse_match
= 0;
7023 /* Must have right number of operands. */
7024 if (i
.operands
!= t
->operands
)
7027 /* Check processor support. */
7028 specific_error
= progress (unsupported
);
7029 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
7032 /* Check AT&T mnemonic. */
7033 specific_error
= progress (unsupported_with_intel_mnemonic
);
7034 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
7037 /* Check AT&T/Intel syntax. */
7038 specific_error
= progress (unsupported_syntax
);
7039 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
7040 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
7043 /* Check Intel64/AMD64 ISA. */
7047 /* Default: Don't accept Intel64. */
7048 if (t
->opcode_modifier
.isa64
== INTEL64
)
7052 /* -mamd64: Don't accept Intel64 and Intel64 only. */
7053 if (t
->opcode_modifier
.isa64
>= INTEL64
)
7057 /* -mintel64: Don't accept AMD64. */
7058 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
7063 /* Check the suffix. */
7064 specific_error
= progress (invalid_instruction_suffix
);
7065 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
7066 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
7067 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
7068 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
7069 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
7072 specific_error
= progress (operand_size_mismatch
);
7073 size_match
= operand_size_match (t
);
7077 /* This is intentionally not
7079 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
7081 as the case of a missing * on the operand is accepted (perhaps with
7082 a warning, issued further down). */
7083 specific_error
= progress (operand_type_mismatch
);
7084 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
7087 /* In Intel syntax, normally we can check for memory operand size when
7088 there is no mnemonic suffix. But jmp and call have 2 different
7089 encodings with Dword memory operand size. Skip the "near" one
7090 (permitting a register operand) when "far" was requested. */
7092 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
7093 && t
->operand_types
[0].bitfield
.class == Reg
)
7096 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7097 operand_types
[j
] = t
->operand_types
[j
];
7099 /* In general, don't allow 32-bit operands on pre-386. */
7100 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
7101 : operand_size_mismatch
);
7102 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
7103 if (i
.suffix
== LONG_MNEM_SUFFIX
7104 && !cpu_arch_flags
.bitfield
.cpui386
7106 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
7107 && !intel_float_operand (insn_name (t
)))
7108 : intel_float_operand (insn_name (t
)) != 2)
7109 && (t
->operands
== i
.imm_operands
7110 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
7111 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
7112 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
7113 || (operand_types
[j
].bitfield
.class != RegMMX
7114 && operand_types
[j
].bitfield
.class != RegSIMD
7115 && operand_types
[j
].bitfield
.class != RegMask
))
7116 && !t
->opcode_modifier
.sib
)
7119 /* Do not verify operands when there are none. */
7122 if (VEX_check_encoding (t
))
7124 specific_error
= progress (i
.error
);
7128 /* We've found a match; break out of loop. */
7132 if (!t
->opcode_modifier
.jump
7133 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
7135 /* There should be only one Disp operand. */
7136 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7137 if (operand_type_check (operand_types
[j
], disp
))
7139 if (j
< MAX_OPERANDS
)
7141 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7143 addr_prefix_disp
= j
;
7145 /* Address size prefix will turn Disp64 operand into Disp32 and
7146 Disp32/Disp16 one into Disp16/Disp32 respectively. */
7150 override
= !override
;
7153 if (operand_types
[j
].bitfield
.disp32
7154 && operand_types
[j
].bitfield
.disp16
)
7156 operand_types
[j
].bitfield
.disp16
= override
;
7157 operand_types
[j
].bitfield
.disp32
= !override
;
7159 gas_assert (!operand_types
[j
].bitfield
.disp64
);
7163 if (operand_types
[j
].bitfield
.disp64
)
7165 gas_assert (!operand_types
[j
].bitfield
.disp32
);
7166 operand_types
[j
].bitfield
.disp32
= override
;
7167 operand_types
[j
].bitfield
.disp64
= !override
;
7169 operand_types
[j
].bitfield
.disp16
= 0;
7175 /* We check register size if needed. */
7176 if (t
->opcode_modifier
.checkoperandsize
)
7178 check_register
= (1 << t
->operands
) - 1;
7179 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
7180 check_register
&= ~(1 << i
.broadcast
.operand
);
7185 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
7186 switch (t
->operands
)
7189 if (!operand_type_match (overlap0
, i
.types
[0]))
7192 /* Allow the ModR/M encoding to be requested by using the {load} or
7193 {store} pseudo prefix on an applicable insn. */
7194 if (!t
->opcode_modifier
.modrm
7195 && i
.reg_operands
== 1
7196 && ((i
.dir_encoding
== dir_encoding_load
7197 && t
->mnem_off
!= MN_pop
)
7198 || (i
.dir_encoding
== dir_encoding_store
7199 && t
->mnem_off
!= MN_push
))
7201 && t
->mnem_off
!= MN_bswap
)
7206 /* xchg %eax, %eax is a special case. It is an alias for nop
7207 only in 32bit mode and we can use opcode 0x90. In 64bit
7208 mode, we can't use 0x90 for xchg %eax, %eax since it should
7209 zero-extend %eax to %rax. */
7210 if (t
->base_opcode
== 0x90
7211 && t
->opcode_space
== SPACE_BASE
)
7213 if (flag_code
== CODE_64BIT
7214 && i
.types
[0].bitfield
.instance
== Accum
7215 && i
.types
[0].bitfield
.dword
7216 && i
.types
[1].bitfield
.instance
== Accum
)
7219 /* Allow the ModR/M encoding to be requested by using the
7220 {load} or {store} pseudo prefix. */
7221 if (i
.dir_encoding
== dir_encoding_load
7222 || i
.dir_encoding
== dir_encoding_store
)
7226 if (t
->base_opcode
== MOV_AX_DISP32
7227 && t
->opcode_space
== SPACE_BASE
7228 && t
->mnem_off
!= MN_movabs
)
7230 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
7231 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
7234 /* xrelease mov %eax, <disp> is another special case. It must not
7235 match the accumulator-only encoding of mov. */
7239 /* Allow the ModR/M encoding to be requested by using a suitable
7240 {load} or {store} pseudo prefix. */
7241 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
7242 ? dir_encoding_store
7243 : dir_encoding_load
)
7244 && !i
.types
[0].bitfield
.disp64
7245 && !i
.types
[1].bitfield
.disp64
)
7249 /* Allow the ModR/M encoding to be requested by using the {load} or
7250 {store} pseudo prefix on an applicable insn. */
7251 if (!t
->opcode_modifier
.modrm
7252 && i
.reg_operands
== 1
7253 && i
.imm_operands
== 1
7254 && (i
.dir_encoding
== dir_encoding_load
7255 || i
.dir_encoding
== dir_encoding_store
)
7256 && t
->opcode_space
== SPACE_BASE
)
7258 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
7259 && i
.dir_encoding
== dir_encoding_store
)
7262 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
7263 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
7264 || i
.dir_encoding
== dir_encoding_load
))
7267 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
7268 && i
.dir_encoding
== dir_encoding_load
)
7274 if (!(size_match
& MATCH_STRAIGHT
))
7276 /* Reverse direction of operands if swapping is possible in the first
7277 place (operands need to be symmetric) and
7278 - the load form is requested, and the template is a store form,
7279 - the store form is requested, and the template is a load form,
7280 - the non-default (swapped) form is requested. */
7281 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
7282 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
7283 && !operand_type_all_zero (&overlap1
))
7284 switch (i
.dir_encoding
)
7286 case dir_encoding_load
:
7287 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7288 || t
->opcode_modifier
.regmem
)
7292 case dir_encoding_store
:
7293 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7294 && !t
->opcode_modifier
.regmem
)
7298 case dir_encoding_swap
:
7301 case dir_encoding_default
:
7304 /* If we want store form, we skip the current load. */
7305 if ((i
.dir_encoding
== dir_encoding_store
7306 || i
.dir_encoding
== dir_encoding_swap
)
7307 && i
.mem_operands
== 0
7308 && t
->opcode_modifier
.load
)
7313 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7314 if (!operand_type_match (overlap0
, i
.types
[0])
7315 || !operand_type_match (overlap1
, i
.types
[1])
7316 || ((check_register
& 3) == 3
7317 && !operand_type_register_match (i
.types
[0],
7322 specific_error
= progress (i
.error
);
7324 /* Check if other direction is valid ... */
7325 if (!t
->opcode_modifier
.d
)
7329 if (!(size_match
& MATCH_REVERSE
))
7331 /* Try reversing direction of operands. */
7332 j
= is_cpu (t
, CpuFMA4
)
7333 || is_cpu (t
, CpuXOP
) ? 1 : i
.operands
- 1;
7334 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7335 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7336 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7337 gas_assert (t
->operands
!= 3 || !check_register
);
7338 if (!operand_type_match (overlap0
, i
.types
[0])
7339 || !operand_type_match (overlap1
, i
.types
[j
])
7340 || (t
->operands
== 3
7341 && !operand_type_match (overlap2
, i
.types
[1]))
7343 && !operand_type_register_match (i
.types
[0],
7348 /* Does not match either direction. */
7349 specific_error
= progress (i
.error
);
7352 /* found_reverse_match holds which variant of D
7354 if (!t
->opcode_modifier
.d
)
7355 found_reverse_match
= 0;
7356 else if (operand_types
[0].bitfield
.tbyte
)
7358 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7359 found_reverse_match
= Opcode_FloatD
;
7361 found_reverse_match
= ~0;
7362 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7363 if ((t
->extension_opcode
& 4)
7364 && (intel_syntax
|| intel_mnemonic
))
7365 found_reverse_match
|= Opcode_FloatR
;
7367 else if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
7369 found_reverse_match
= Opcode_VexW
;
7370 goto check_operands_345
;
7372 else if (t
->opcode_space
!= SPACE_BASE
7373 && (t
->opcode_space
!= SPACE_0F
7374 /* MOV to/from CR/DR/TR, as an exception, follow
7375 the base opcode space encoding model. */
7376 || (t
->base_opcode
| 7) != 0x27))
7377 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7378 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7379 else if (!t
->opcode_modifier
.commutative
)
7380 found_reverse_match
= Opcode_D
;
7382 found_reverse_match
= ~0;
7386 /* Found a forward 2 operand match here. */
7388 switch (t
->operands
)
7391 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7392 if (!operand_type_match (overlap4
, i
.types
[4])
7393 || !operand_type_register_match (i
.types
[3],
7398 specific_error
= progress (i
.error
);
7403 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7404 if (!operand_type_match (overlap3
, i
.types
[3])
7405 || ((check_register
& 0xa) == 0xa
7406 && !operand_type_register_match (i
.types
[1],
7410 || ((check_register
& 0xc) == 0xc
7411 && !operand_type_register_match (i
.types
[2],
7416 specific_error
= progress (i
.error
);
7421 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7422 if (!operand_type_match (overlap2
, i
.types
[2])
7423 || ((check_register
& 5) == 5
7424 && !operand_type_register_match (i
.types
[0],
7428 || ((check_register
& 6) == 6
7429 && !operand_type_register_match (i
.types
[1],
7434 specific_error
= progress (i
.error
);
7440 /* Found either forward/reverse 2, 3 or 4 operand match here:
7441 slip through to break. */
7444 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7445 if (VEX_check_encoding (t
))
7447 specific_error
= progress (i
.error
);
7451 /* Check if vector operands are valid. */
7452 if (check_VecOperands (t
))
7454 specific_error
= progress (i
.error
);
7458 /* We've found a match; break out of loop. */
7464 if (t
== current_templates
->end
)
7466 /* We found no match. */
7467 i
.error
= specific_error
;
7471 if (!quiet_warnings
)
7474 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7475 as_warn (_("indirect %s without `*'"), insn_name (t
));
7477 if (t
->opcode_modifier
.isprefix
7478 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7480 /* Warn them that a data or address size prefix doesn't
7481 affect assembly of the next line of code. */
7482 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7486 /* Copy the template we found. */
7487 install_template (t
);
7489 if (addr_prefix_disp
!= -1)
7490 i
.tm
.operand_types
[addr_prefix_disp
]
7491 = operand_types
[addr_prefix_disp
];
7493 switch (found_reverse_match
)
7499 case Opcode_FloatR
| Opcode_FloatD
:
7500 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7501 found_reverse_match
&= Opcode_FloatD
;
7505 /* If we found a reverse match we must alter the opcode direction
7506 bit and clear/flip the regmem modifier one. found_reverse_match
7507 holds bits to change (different for int & float insns). */
7509 i
.tm
.base_opcode
^= found_reverse_match
;
7511 /* Certain SIMD insns have their load forms specified in the opcode
7512 table, and hence we need to _set_ RegMem instead of clearing it.
7513 We need to avoid setting the bit though on insns like KMOVW. */
7514 i
.tm
.opcode_modifier
.regmem
7515 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7516 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7517 && !i
.tm
.opcode_modifier
.regmem
;
7521 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7522 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7526 /* Only the first two register operands need reversing, alongside
7528 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7530 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7531 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7532 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7542 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7543 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7545 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7547 as_bad (_("`%s' operand %u must use `%ses' segment"),
7549 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7554 /* There's only ever one segment override allowed per instruction.
7555 This instruction possibly has a legal segment override on the
7556 second operand, so copy the segment to where non-string
7557 instructions store it, allowing common code. */
7558 i
.seg
[op
] = i
.seg
[1];
7564 process_suffix (void)
7566 bool is_movx
= false;
7568 /* If matched instruction specifies an explicit instruction mnemonic
7570 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7571 i
.suffix
= WORD_MNEM_SUFFIX
;
7572 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7573 i
.suffix
= LONG_MNEM_SUFFIX
;
7574 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7575 i
.suffix
= QWORD_MNEM_SUFFIX
;
7576 else if (i
.reg_operands
7577 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7578 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7580 unsigned int numop
= i
.operands
;
7583 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7584 && (i
.tm
.base_opcode
| 8) == 0xbe)
7585 || (i
.tm
.opcode_space
== SPACE_BASE
7586 && i
.tm
.base_opcode
== 0x63
7587 && is_cpu (&i
.tm
, Cpu64
));
7589 /* movsx/movzx want only their source operand considered here, for the
7590 ambiguity checking below. The suffix will be replaced afterwards
7591 to represent the destination (register). */
7592 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7595 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7596 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7599 /* If there's no instruction mnemonic suffix we try to invent one
7600 based on GPR operands. */
7603 /* We take i.suffix from the last register operand specified,
7604 Destination register type is more significant than source
7605 register type. crc32 in SSE4.2 prefers source register
7607 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7610 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7611 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7613 if (i
.types
[op
].bitfield
.class != Reg
)
7615 if (i
.types
[op
].bitfield
.byte
)
7616 i
.suffix
= BYTE_MNEM_SUFFIX
;
7617 else if (i
.types
[op
].bitfield
.word
)
7618 i
.suffix
= WORD_MNEM_SUFFIX
;
7619 else if (i
.types
[op
].bitfield
.dword
)
7620 i
.suffix
= LONG_MNEM_SUFFIX
;
7621 else if (i
.types
[op
].bitfield
.qword
)
7622 i
.suffix
= QWORD_MNEM_SUFFIX
;
7628 /* As an exception, movsx/movzx silently default to a byte source
7630 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7631 i
.suffix
= BYTE_MNEM_SUFFIX
;
7633 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7635 if (!check_byte_reg ())
7638 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7640 if (!check_long_reg ())
7643 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7645 if (!check_qword_reg ())
7648 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7650 if (!check_word_reg ())
7653 else if (intel_syntax
7654 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7655 /* Do nothing if the instruction is going to ignore the prefix. */
7660 /* Undo the movsx/movzx change done above. */
7663 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7666 i
.suffix
= stackop_size
;
7667 if (stackop_size
== LONG_MNEM_SUFFIX
)
7669 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7670 .code16gcc directive to support 16-bit mode with
7671 32-bit address. For IRET without a suffix, generate
7672 16-bit IRET (opcode 0xcf) to return from an interrupt
7674 if (i
.tm
.base_opcode
== 0xcf)
7676 i
.suffix
= WORD_MNEM_SUFFIX
;
7677 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7679 /* Warn about changed behavior for segment register push/pop. */
7680 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7681 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7686 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7687 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7688 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7689 || (i
.tm
.opcode_space
== SPACE_0F
7690 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7691 && i
.tm
.extension_opcode
<= 3)))
7696 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7698 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7699 || i
.tm
.opcode_modifier
.no_lsuf
)
7700 i
.suffix
= QWORD_MNEM_SUFFIX
;
7705 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7706 i
.suffix
= LONG_MNEM_SUFFIX
;
7709 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7710 i
.suffix
= WORD_MNEM_SUFFIX
;
7716 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7717 /* Also cover lret/retf/iret in 64-bit mode. */
7718 || (flag_code
== CODE_64BIT
7719 && !i
.tm
.opcode_modifier
.no_lsuf
7720 && !i
.tm
.opcode_modifier
.no_qsuf
))
7721 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7722 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7723 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7724 /* Accept FLDENV et al without suffix. */
7725 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7727 unsigned int suffixes
, evex
= 0;
7729 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7730 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7732 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7734 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7736 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7739 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7740 also suitable for AT&T syntax mode, it was requested that this be
7741 restricted to just Intel syntax. */
7742 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7743 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7747 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7749 if (vector_size
< VSZ512
)
7751 i
.tm
.operand_types
[op
].bitfield
.zmmword
= 0;
7752 if (vector_size
< VSZ256
)
7754 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7755 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7756 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7757 || (!i
.tm
.opcode_modifier
.evex
7758 && is_evex_encoding (&i
.tm
))))
7759 i
.tm
.opcode_modifier
.evex
= EVEX128
;
7761 else if (i
.tm
.operand_types
[op
].bitfield
.ymmword
7762 && !i
.tm
.operand_types
[op
].bitfield
.xmmword
7763 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7764 || (!i
.tm
.opcode_modifier
.evex
7765 && is_evex_encoding (&i
.tm
))))
7766 i
.tm
.opcode_modifier
.evex
= EVEX256
;
7768 else if (is_evex_encoding (&i
.tm
)
7769 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7771 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7772 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7773 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7774 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7775 if (!i
.tm
.opcode_modifier
.evex
7776 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7777 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7780 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7781 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7782 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7785 /* Any properly sized operand disambiguates the insn. */
7786 if (i
.types
[op
].bitfield
.xmmword
7787 || i
.types
[op
].bitfield
.ymmword
7788 || i
.types
[op
].bitfield
.zmmword
)
7790 suffixes
&= ~(7 << 6);
7795 if ((i
.flags
[op
] & Operand_Mem
)
7796 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7798 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7800 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7802 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7804 if (is_evex_encoding (&i
.tm
))
7810 /* Are multiple suffixes / operand sizes allowed? */
7811 if (suffixes
& (suffixes
- 1))
7814 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7815 || operand_check
== check_error
))
7817 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7820 if (operand_check
== check_error
)
7822 as_bad (_("no instruction mnemonic suffix given and "
7823 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7826 if (operand_check
== check_warning
)
7827 as_warn (_("%s; using default for `%s'"),
7829 ? _("ambiguous operand size")
7830 : _("no instruction mnemonic suffix given and "
7831 "no register operands"),
7834 if (i
.tm
.opcode_modifier
.floatmf
)
7835 i
.suffix
= SHORT_MNEM_SUFFIX
;
7837 /* handled below */;
7839 i
.tm
.opcode_modifier
.evex
= evex
;
7840 else if (flag_code
== CODE_16BIT
)
7841 i
.suffix
= WORD_MNEM_SUFFIX
;
7842 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7843 i
.suffix
= LONG_MNEM_SUFFIX
;
7845 i
.suffix
= QWORD_MNEM_SUFFIX
;
7851 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7852 In AT&T syntax, if there is no suffix (warned about above), the default
7853 will be byte extension. */
7854 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7855 i
.tm
.base_opcode
|= 1;
7857 /* For further processing, the suffix should represent the destination
7858 (register). This is already the case when one was used with
7859 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7860 no suffix to begin with. */
7861 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7863 if (i
.types
[1].bitfield
.word
)
7864 i
.suffix
= WORD_MNEM_SUFFIX
;
7865 else if (i
.types
[1].bitfield
.qword
)
7866 i
.suffix
= QWORD_MNEM_SUFFIX
;
7868 i
.suffix
= LONG_MNEM_SUFFIX
;
7870 i
.tm
.opcode_modifier
.w
= 0;
7874 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7875 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7876 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7878 /* Change the opcode based on the operand size given by i.suffix. */
7881 /* Size floating point instruction. */
7882 case LONG_MNEM_SUFFIX
:
7883 if (i
.tm
.opcode_modifier
.floatmf
)
7885 i
.tm
.base_opcode
^= 4;
7889 case WORD_MNEM_SUFFIX
:
7890 case QWORD_MNEM_SUFFIX
:
7891 /* It's not a byte, select word/dword operation. */
7892 if (i
.tm
.opcode_modifier
.w
)
7895 i
.tm
.base_opcode
|= 8;
7897 i
.tm
.base_opcode
|= 1;
7900 case SHORT_MNEM_SUFFIX
:
7901 /* Now select between word & dword operations via the operand
7902 size prefix, except for instructions that will ignore this
7904 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7905 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7906 && !i
.tm
.opcode_modifier
.floatmf
7907 && !is_any_vex_encoding (&i
.tm
)
7908 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7909 || (flag_code
== CODE_64BIT
7910 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7912 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7914 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7915 prefix
= ADDR_PREFIX_OPCODE
;
7917 if (!add_prefix (prefix
))
7921 /* Set mode64 for an operand. */
7922 if (i
.suffix
== QWORD_MNEM_SUFFIX
7923 && flag_code
== CODE_64BIT
7924 && !i
.tm
.opcode_modifier
.norex64
7925 && !i
.tm
.opcode_modifier
.vexw
7926 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7928 && ! (i
.operands
== 2
7929 && i
.tm
.base_opcode
== 0x90
7930 && i
.tm
.opcode_space
== SPACE_BASE
7931 && i
.types
[0].bitfield
.instance
== Accum
7932 && i
.types
[0].bitfield
.qword
7933 && i
.types
[1].bitfield
.instance
== Accum
))
7939 /* Select word/dword/qword operation with explicit data sizing prefix
7940 when there are no suitable register operands. */
7941 if (i
.tm
.opcode_modifier
.w
7942 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7944 || (i
.reg_operands
== 1
7946 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7948 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7949 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7950 || i
.tm
.mnem_off
== MN_crc32
))))
7951 i
.tm
.base_opcode
|= 1;
7955 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7957 gas_assert (!i
.suffix
);
7958 gas_assert (i
.reg_operands
);
7960 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7963 /* The address size override prefix changes the size of the
7965 if (flag_code
== CODE_64BIT
7966 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7968 as_bad (_("16-bit addressing unavailable for `%s'"),
7973 if ((flag_code
== CODE_32BIT
7974 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7975 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7976 && !add_prefix (ADDR_PREFIX_OPCODE
))
7981 /* Check invalid register operand when the address size override
7982 prefix changes the size of register operands. */
7984 enum { need_word
, need_dword
, need_qword
} need
;
7986 /* Check the register operand for the address size prefix if
7987 the memory operand has no real registers, like symbol, DISP
7988 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7989 if (i
.mem_operands
== 1
7990 && i
.reg_operands
== 1
7992 && i
.types
[1].bitfield
.class == Reg
7993 && (flag_code
== CODE_32BIT
7994 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7995 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7996 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7997 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7998 || (x86_elf_abi
== X86_64_X32_ABI
8000 && i
.base_reg
->reg_num
== RegIP
8001 && i
.base_reg
->reg_type
.bitfield
.qword
))
8005 && !add_prefix (ADDR_PREFIX_OPCODE
))
8008 if (flag_code
== CODE_32BIT
)
8009 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
8010 else if (i
.prefix
[ADDR_PREFIX
])
8013 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
8015 for (op
= 0; op
< i
.operands
; op
++)
8017 if (i
.types
[op
].bitfield
.class != Reg
)
8023 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
8027 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
8031 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
8036 as_bad (_("invalid register operand size for `%s'"),
8047 check_byte_reg (void)
8051 for (op
= i
.operands
; --op
>= 0;)
8053 /* Skip non-register operands. */
8054 if (i
.types
[op
].bitfield
.class != Reg
)
8057 /* If this is an eight bit register, it's OK. If it's the 16 or
8058 32 bit version of an eight bit register, we will just use the
8059 low portion, and that's OK too. */
8060 if (i
.types
[op
].bitfield
.byte
)
8063 /* I/O port address operands are OK too. */
8064 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
8065 && i
.tm
.operand_types
[op
].bitfield
.word
)
8068 /* crc32 only wants its source operand checked here. */
8069 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
8072 /* Any other register is bad. */
8073 as_bad (_("`%s%s' not allowed with `%s%c'"),
8074 register_prefix
, i
.op
[op
].regs
->reg_name
,
8075 insn_name (&i
.tm
), i
.suffix
);
8082 check_long_reg (void)
8086 for (op
= i
.operands
; --op
>= 0;)
8087 /* Skip non-register operands. */
8088 if (i
.types
[op
].bitfield
.class != Reg
)
8090 /* Reject eight bit registers, except where the template requires
8091 them. (eg. movzb) */
8092 else if (i
.types
[op
].bitfield
.byte
8093 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8094 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8095 && (i
.tm
.operand_types
[op
].bitfield
.word
8096 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8098 as_bad (_("`%s%s' not allowed with `%s%c'"),
8100 i
.op
[op
].regs
->reg_name
,
8105 /* Error if the e prefix on a general reg is missing. */
8106 else if (i
.types
[op
].bitfield
.word
8107 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8108 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8109 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8111 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8112 register_prefix
, i
.op
[op
].regs
->reg_name
,
8116 /* Warn if the r prefix on a general reg is present. */
8117 else if (i
.types
[op
].bitfield
.qword
8118 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8119 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8120 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8122 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8123 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8130 check_qword_reg (void)
8134 for (op
= i
.operands
; --op
>= 0; )
8135 /* Skip non-register operands. */
8136 if (i
.types
[op
].bitfield
.class != Reg
)
8138 /* Reject eight bit registers, except where the template requires
8139 them. (eg. movzb) */
8140 else if (i
.types
[op
].bitfield
.byte
8141 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8142 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8143 && (i
.tm
.operand_types
[op
].bitfield
.word
8144 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8146 as_bad (_("`%s%s' not allowed with `%s%c'"),
8148 i
.op
[op
].regs
->reg_name
,
8153 /* Warn if the r prefix on a general reg is missing. */
8154 else if ((i
.types
[op
].bitfield
.word
8155 || i
.types
[op
].bitfield
.dword
)
8156 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8157 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8158 && i
.tm
.operand_types
[op
].bitfield
.qword
)
8160 /* Prohibit these changes in the 64bit mode, since the
8161 lowering is more complicated. */
8162 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8163 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8170 check_word_reg (void)
8173 for (op
= i
.operands
; --op
>= 0;)
8174 /* Skip non-register operands. */
8175 if (i
.types
[op
].bitfield
.class != Reg
)
8177 /* Reject eight bit registers, except where the template requires
8178 them. (eg. movzb) */
8179 else if (i
.types
[op
].bitfield
.byte
8180 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8181 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8182 && (i
.tm
.operand_types
[op
].bitfield
.word
8183 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8185 as_bad (_("`%s%s' not allowed with `%s%c'"),
8187 i
.op
[op
].regs
->reg_name
,
8192 /* Error if the e or r prefix on a general reg is present. */
8193 else if ((i
.types
[op
].bitfield
.dword
8194 || i
.types
[op
].bitfield
.qword
)
8195 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8196 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8197 && i
.tm
.operand_types
[op
].bitfield
.word
)
8199 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8200 register_prefix
, i
.op
[op
].regs
->reg_name
,
8208 update_imm (unsigned int j
)
8210 i386_operand_type overlap
= i
.types
[j
];
8212 if (i
.tm
.operand_types
[j
].bitfield
.imm8
8213 && i
.tm
.operand_types
[j
].bitfield
.imm8s
8214 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
8216 /* This combination is used on 8-bit immediates where e.g. $~0 is
8217 desirable to permit. We're past operand type matching, so simply
8218 put things back in the shape they were before introducing the
8219 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
8220 overlap
.bitfield
.imm8s
= 0;
8223 if (overlap
.bitfield
.imm8
8224 + overlap
.bitfield
.imm8s
8225 + overlap
.bitfield
.imm16
8226 + overlap
.bitfield
.imm32
8227 + overlap
.bitfield
.imm32s
8228 + overlap
.bitfield
.imm64
> 1)
8230 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
8231 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
8232 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
8233 static const i386_operand_type imm16_32
= { .bitfield
=
8234 { .imm16
= 1, .imm32
= 1 }
8236 static const i386_operand_type imm16_32s
= { .bitfield
=
8237 { .imm16
= 1, .imm32s
= 1 }
8239 static const i386_operand_type imm16_32_32s
= { .bitfield
=
8240 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
8245 i386_operand_type temp
;
8247 operand_type_set (&temp
, 0);
8248 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
8250 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
8251 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
8253 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
8254 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
8255 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
8257 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
8258 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
8261 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
8264 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
8265 || operand_type_equal (&overlap
, &imm16_32
)
8266 || operand_type_equal (&overlap
, &imm16_32s
))
8268 if ((flag_code
== CODE_16BIT
)
8269 ^ (i
.prefix
[DATA_PREFIX
] != 0 && !(i
.prefix
[REX_PREFIX
] & REX_W
)))
8274 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
8275 overlap
= operand_type_and (overlap
, imm32s
);
8276 else if (i
.prefix
[DATA_PREFIX
])
8277 overlap
= operand_type_and (overlap
,
8278 flag_code
!= CODE_16BIT
? imm16
: imm32
);
8279 if (overlap
.bitfield
.imm8
8280 + overlap
.bitfield
.imm8s
8281 + overlap
.bitfield
.imm16
8282 + overlap
.bitfield
.imm32
8283 + overlap
.bitfield
.imm32s
8284 + overlap
.bitfield
.imm64
!= 1)
8286 as_bad (_("no instruction mnemonic suffix given; "
8287 "can't determine immediate size"));
8291 i
.types
[j
] = overlap
;
8301 /* Update the first 2 immediate operands. */
8302 n
= i
.operands
> 2 ? 2 : i
.operands
;
8305 for (j
= 0; j
< n
; j
++)
8306 if (update_imm (j
) == 0)
8309 /* The 3rd operand can't be immediate operand. */
8310 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
8316 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8319 if (r
->reg_flags
& RegRex
)
8321 if (i
.rex
& rex_bit
)
8322 as_bad (_("same type of prefix used twice"));
8325 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8327 gas_assert (i
.vex
.register_specifier
== r
);
8328 i
.vex
.register_specifier
+= 8;
8331 if (r
->reg_flags
& RegVRex
)
8336 process_operands (void)
8338 /* Default segment register this instruction will use for memory
8339 accesses. 0 means unknown. This is only for optimizing out
8340 unnecessary segment overrides. */
8341 const reg_entry
*default_seg
= NULL
;
8343 /* We only need to check those implicit registers for instructions
8344 with 3 operands or less. */
8345 if (i
.operands
<= 3)
8346 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8347 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8350 if (i
.tm
.opcode_modifier
.sse2avx
)
8352 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8354 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8355 i
.prefix
[REX_PREFIX
] = 0;
8358 /* ImmExt should be processed after SSE2AVX. */
8359 else if (i
.tm
.opcode_modifier
.immext
)
8362 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8363 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8364 new destination operand here, while converting the source one to register
8366 if (i
.tm
.mnem_off
== MN_tilezero
)
8368 i
.op
[1].regs
= i
.op
[0].regs
;
8369 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8370 i
.types
[1] = i
.types
[0];
8371 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8372 i
.flags
[1] = i
.flags
[0];
8378 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8380 static const i386_operand_type regxmm
= {
8381 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8383 unsigned int dupl
= i
.operands
;
8384 unsigned int dest
= dupl
- 1;
8387 /* The destination must be an xmm register. */
8388 gas_assert (i
.reg_operands
8389 && MAX_OPERANDS
> dupl
8390 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8392 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8393 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8395 /* Keep xmm0 for instructions with VEX prefix and 3
8397 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8398 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8403 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8405 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8407 /* Add the implicit xmm0 for instructions with VEX prefix
8409 for (j
= i
.operands
; j
> 0; j
--)
8411 i
.op
[j
] = i
.op
[j
- 1];
8412 i
.types
[j
] = i
.types
[j
- 1];
8413 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8414 i
.flags
[j
] = i
.flags
[j
- 1];
8417 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8418 i
.types
[0] = regxmm
;
8419 i
.tm
.operand_types
[0] = regxmm
;
8422 i
.reg_operands
+= 2;
8427 i
.op
[dupl
] = i
.op
[dest
];
8428 i
.types
[dupl
] = i
.types
[dest
];
8429 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8430 i
.flags
[dupl
] = i
.flags
[dest
];
8439 i
.op
[dupl
] = i
.op
[dest
];
8440 i
.types
[dupl
] = i
.types
[dest
];
8441 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8442 i
.flags
[dupl
] = i
.flags
[dest
];
8445 if (i
.tm
.opcode_modifier
.immext
)
8448 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8449 && i
.tm
.opcode_modifier
.modrm
)
8453 for (j
= 1; j
< i
.operands
; j
++)
8455 i
.op
[j
- 1] = i
.op
[j
];
8456 i
.types
[j
- 1] = i
.types
[j
];
8458 /* We need to adjust fields in i.tm since they are used by
8459 build_modrm_byte. */
8460 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8462 i
.flags
[j
- 1] = i
.flags
[j
];
8465 /* No adjustment to i.reg_operands: This was already done at the top
8470 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8472 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8474 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8475 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8476 regnum
= register_number (i
.op
[1].regs
);
8477 first_reg_in_group
= regnum
& ~3;
8478 last_reg_in_group
= first_reg_in_group
+ 3;
8479 if (regnum
!= first_reg_in_group
)
8480 as_warn (_("source register `%s%s' implicitly denotes"
8481 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8482 register_prefix
, i
.op
[1].regs
->reg_name
,
8483 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8484 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8487 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8489 /* The imul $imm, %reg instruction is converted into
8490 imul $imm, %reg, %reg, and the clr %reg instruction
8491 is converted into xor %reg, %reg. */
8493 unsigned int first_reg_op
;
8495 if (operand_type_check (i
.types
[0], reg
))
8499 /* Pretend we saw the extra register operand. */
8500 gas_assert (i
.reg_operands
== 1
8501 && i
.op
[first_reg_op
+ 1].regs
== 0);
8502 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8503 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8508 if (i
.tm
.opcode_modifier
.modrm
)
8510 /* The opcode is completed (modulo i.tm.extension_opcode which
8511 must be put into the modrm byte). Now, we make the modrm and
8512 index base bytes based on all the info we've collected. */
8514 default_seg
= build_modrm_byte ();
8516 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8518 /* Warn about some common errors, but press on regardless. */
8519 if (i
.operands
== 2)
8521 /* Reversed arguments on faddp or fmulp. */
8522 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8523 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8524 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8526 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8528 /* Extraneous `l' suffix on fp insn. */
8529 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8530 register_prefix
, i
.op
[0].regs
->reg_name
);
8534 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
8536 if (flag_code
!= CODE_64BIT
8537 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8538 && i
.op
[0].regs
->reg_num
== 1
8539 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8540 && i
.op
[0].regs
->reg_num
< 4)
8542 as_bad (_("you can't `%s %s%s'"),
8543 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8546 if (i
.op
[0].regs
->reg_num
> 3
8547 && i
.tm
.opcode_space
== SPACE_BASE
)
8549 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8550 i
.tm
.opcode_space
= SPACE_0F
;
8552 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8554 else if (i
.tm
.opcode_space
== SPACE_BASE
8555 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8557 default_seg
= reg_ds
;
8559 else if (i
.tm
.opcode_modifier
.isstring
)
8561 /* For the string instructions that allow a segment override
8562 on one of their operands, the default segment is ds. */
8563 default_seg
= reg_ds
;
8565 else if (i
.short_form
)
8567 /* The register operand is in the 1st or 2nd non-immediate operand. */
8568 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
8571 && r
->reg_type
.bitfield
.instance
== Accum
8572 && i
.op
[i
.imm_operands
+ 1].regs
)
8573 r
= i
.op
[i
.imm_operands
+ 1].regs
;
8574 /* Register goes in low 3 bits of opcode. */
8575 i
.tm
.base_opcode
|= r
->reg_num
;
8576 set_rex_vrex (r
, REX_B
, false);
8578 if (dot_insn () && i
.reg_operands
== 2)
8580 gas_assert (is_any_vex_encoding (&i
.tm
)
8581 || i
.vec_encoding
!= vex_encoding_default
);
8582 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8585 else if (i
.reg_operands
== 1
8586 && !i
.flags
[i
.operands
- 1]
8587 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
8590 gas_assert (is_any_vex_encoding (&i
.tm
)
8591 || i
.vec_encoding
!= vex_encoding_default
);
8592 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8595 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8596 && i
.tm
.mnem_off
== MN_lea
)
8598 if (!quiet_warnings
)
8599 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8600 if (optimize
&& !i
.no_optimize
)
8603 i
.prefix
[SEG_PREFIX
] = 0;
8607 /* If a segment was explicitly specified, and the specified segment
8608 is neither the default nor the one already recorded from a prefix,
8609 use an opcode prefix to select it. If we never figured out what
8610 the default segment is, then default_seg will be zero at this
8611 point, and the specified segment prefix will always be used. */
8613 && i
.seg
[0] != default_seg
8614 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8616 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8622 static const reg_entry
*
8623 build_modrm_byte (void)
8625 const reg_entry
*default_seg
= NULL
;
8626 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8627 /* Compensate for kludge in md_assemble(). */
8628 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8629 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8630 unsigned int v
, op
, reg_slot
= ~0;
8632 /* Accumulator (in particular %st), shift count (%cl), and alike need
8633 to be skipped just like immediate operands do. */
8634 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8636 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8639 for (op
= source
; op
< i
.operands
; ++op
)
8640 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8643 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8647 /* There are 2 kinds of instructions:
8648 1. 5 operands: 4 register operands or 3 register operands
8649 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8650 VexW0 or VexW1. The destination must be either XMM, YMM or
8652 2. 4 operands: 4 register operands or 3 register operands
8653 plus 1 memory operand, with VexXDS.
8654 3. Other equivalent combinations when coming from s_insn(). */
8655 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8656 && i
.tm
.opcode_modifier
.vexw
);
8657 gas_assert (dot_insn ()
8658 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8660 /* Of the first two non-immediate operands the one with the template
8661 not allowing for a memory one is encoded in the immediate operand. */
8663 reg_slot
= source
+ 1;
8665 reg_slot
= source
++;
8669 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8670 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
8673 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
8675 if (i
.imm_operands
== 0)
8677 /* When there is no immediate operand, generate an 8bit
8678 immediate operand to encode the first operand. */
8679 exp
= &im_expressions
[i
.imm_operands
++];
8680 i
.op
[i
.operands
].imms
= exp
;
8681 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8684 exp
->X_op
= O_constant
;
8688 gas_assert (i
.imm_operands
== 1);
8689 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8690 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8692 /* Turn on Imm8 again so that output_imm will generate it. */
8693 i
.types
[0].bitfield
.imm8
= 1;
8697 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
8698 << (3 + !(is_evex_encoding (&i
.tm
)
8699 || i
.vec_encoding
== vex_encoding_evex
));
8702 for (v
= source
+ 1; v
< dest
; ++v
)
8707 if (i
.tm
.extension_opcode
!= None
)
8713 gas_assert (source
< dest
);
8714 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8717 unsigned int tmp
= source
;
8723 if (v
< MAX_OPERANDS
)
8725 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8726 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8729 if (op
< i
.operands
)
8733 unsigned int fake_zero_displacement
= 0;
8735 gas_assert (i
.flags
[op
] & Operand_Mem
);
8737 if (i
.tm
.opcode_modifier
.sib
)
8739 /* The index register of VSIB shouldn't be RegIZ. */
8740 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8741 && i
.index_reg
->reg_num
== RegIZ
)
8744 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8747 i
.sib
.base
= NO_BASE_REGISTER
;
8748 i
.sib
.scale
= i
.log2_scale_factor
;
8749 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8750 i
.types
[op
].bitfield
.disp32
= 1;
8753 /* Since the mandatory SIB always has index register, so
8754 the code logic remains unchanged. The non-mandatory SIB
8755 without index register is allowed and will be handled
8759 if (i
.index_reg
->reg_num
== RegIZ
)
8760 i
.sib
.index
= NO_INDEX_REGISTER
;
8762 i
.sib
.index
= i
.index_reg
->reg_num
;
8763 set_rex_vrex (i
.index_reg
, REX_X
, false);
8767 default_seg
= reg_ds
;
8769 if (i
.base_reg
== 0)
8772 if (!i
.disp_operands
)
8773 fake_zero_displacement
= 1;
8774 if (i
.index_reg
== 0)
8776 /* Both check for VSIB and mandatory non-vector SIB. */
8777 gas_assert (!i
.tm
.opcode_modifier
.sib
8778 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8779 /* Operand is just <disp> */
8780 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8781 if (flag_code
== CODE_64BIT
)
8783 /* 64bit mode overwrites the 32bit absolute
8784 addressing by RIP relative addressing and
8785 absolute addressing is encoded by one of the
8786 redundant SIB forms. */
8787 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8788 i
.sib
.base
= NO_BASE_REGISTER
;
8789 i
.sib
.index
= NO_INDEX_REGISTER
;
8790 i
.types
[op
].bitfield
.disp32
= 1;
8792 else if ((flag_code
== CODE_16BIT
)
8793 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8795 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8796 i
.types
[op
].bitfield
.disp16
= 1;
8800 i
.rm
.regmem
= NO_BASE_REGISTER
;
8801 i
.types
[op
].bitfield
.disp32
= 1;
8804 else if (!i
.tm
.opcode_modifier
.sib
)
8806 /* !i.base_reg && i.index_reg */
8807 if (i
.index_reg
->reg_num
== RegIZ
)
8808 i
.sib
.index
= NO_INDEX_REGISTER
;
8810 i
.sib
.index
= i
.index_reg
->reg_num
;
8811 i
.sib
.base
= NO_BASE_REGISTER
;
8812 i
.sib
.scale
= i
.log2_scale_factor
;
8813 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8814 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8815 i
.types
[op
].bitfield
.disp32
= 1;
8816 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8820 /* RIP addressing for 64bit mode. */
8821 else if (i
.base_reg
->reg_num
== RegIP
)
8823 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8824 i
.rm
.regmem
= NO_BASE_REGISTER
;
8825 i
.types
[op
].bitfield
.disp8
= 0;
8826 i
.types
[op
].bitfield
.disp16
= 0;
8827 i
.types
[op
].bitfield
.disp32
= 1;
8828 i
.types
[op
].bitfield
.disp64
= 0;
8829 i
.flags
[op
] |= Operand_PCrel
;
8830 if (! i
.disp_operands
)
8831 fake_zero_displacement
= 1;
8833 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8835 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8836 switch (i
.base_reg
->reg_num
)
8839 if (i
.index_reg
== 0)
8841 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8842 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8845 default_seg
= reg_ss
;
8846 if (i
.index_reg
== 0)
8849 if (operand_type_check (i
.types
[op
], disp
) == 0)
8851 /* fake (%bp) into 0(%bp) */
8852 if (i
.disp_encoding
== disp_encoding_16bit
)
8853 i
.types
[op
].bitfield
.disp16
= 1;
8855 i
.types
[op
].bitfield
.disp8
= 1;
8856 fake_zero_displacement
= 1;
8859 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8860 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8862 default: /* (%si) -> 4 or (%di) -> 5 */
8863 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8865 if (!fake_zero_displacement
8869 fake_zero_displacement
= 1;
8870 if (i
.disp_encoding
== disp_encoding_8bit
)
8871 i
.types
[op
].bitfield
.disp8
= 1;
8873 i
.types
[op
].bitfield
.disp16
= 1;
8875 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8877 else /* i.base_reg and 32/64 bit mode */
8879 if (operand_type_check (i
.types
[op
], disp
))
8881 i
.types
[op
].bitfield
.disp16
= 0;
8882 i
.types
[op
].bitfield
.disp64
= 0;
8883 i
.types
[op
].bitfield
.disp32
= 1;
8886 if (!i
.tm
.opcode_modifier
.sib
)
8887 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8888 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8890 i
.sib
.base
= i
.base_reg
->reg_num
;
8891 /* x86-64 ignores REX prefix bit here to avoid decoder
8893 if (!(i
.base_reg
->reg_flags
& RegRex
)
8894 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8895 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8896 default_seg
= reg_ss
;
8897 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8899 fake_zero_displacement
= 1;
8900 if (i
.disp_encoding
== disp_encoding_32bit
)
8901 i
.types
[op
].bitfield
.disp32
= 1;
8903 i
.types
[op
].bitfield
.disp8
= 1;
8905 i
.sib
.scale
= i
.log2_scale_factor
;
8906 if (i
.index_reg
== 0)
8908 /* Only check for VSIB. */
8909 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8910 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8911 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8913 /* <disp>(%esp) becomes two byte modrm with no index
8914 register. We've already stored the code for esp
8915 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8916 Any base register besides %esp will not use the
8917 extra modrm byte. */
8918 i
.sib
.index
= NO_INDEX_REGISTER
;
8920 else if (!i
.tm
.opcode_modifier
.sib
)
8922 if (i
.index_reg
->reg_num
== RegIZ
)
8923 i
.sib
.index
= NO_INDEX_REGISTER
;
8925 i
.sib
.index
= i
.index_reg
->reg_num
;
8926 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8927 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8932 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8933 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8937 if (!fake_zero_displacement
8941 fake_zero_displacement
= 1;
8942 if (i
.disp_encoding
== disp_encoding_8bit
)
8943 i
.types
[op
].bitfield
.disp8
= 1;
8945 i
.types
[op
].bitfield
.disp32
= 1;
8947 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8951 if (fake_zero_displacement
)
8953 /* Fakes a zero displacement assuming that i.types[op]
8954 holds the correct displacement size. */
8957 gas_assert (i
.op
[op
].disps
== 0);
8958 exp
= &disp_expressions
[i
.disp_operands
++];
8959 i
.op
[op
].disps
= exp
;
8960 exp
->X_op
= O_constant
;
8961 exp
->X_add_number
= 0;
8962 exp
->X_add_symbol
= (symbolS
*) 0;
8963 exp
->X_op_symbol
= (symbolS
*) 0;
8969 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8970 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
8981 if (!i
.tm
.opcode_modifier
.regmem
)
8983 gas_assert (source
< MAX_OPERANDS
);
8984 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8985 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
8986 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
8991 gas_assert (dest
< MAX_OPERANDS
);
8992 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8993 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8998 /* Fill in i.rm.reg field with extension opcode (if any) or the
8999 appropriate register. */
9000 if (i
.tm
.extension_opcode
!= None
)
9001 i
.rm
.reg
= i
.tm
.extension_opcode
;
9002 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
9004 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
9005 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
9009 gas_assert (source
< MAX_OPERANDS
);
9010 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
9011 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
9014 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
9016 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
9018 add_prefix (LOCK_PREFIX_OPCODE
);
9025 frag_opcode_byte (unsigned char byte
)
9027 if (now_seg
!= absolute_section
)
9028 FRAG_APPEND_1_CHAR (byte
);
9030 ++abs_section_offset
;
9034 flip_code16 (unsigned int code16
)
9036 gas_assert (i
.tm
.operands
== 1);
9038 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
9039 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
9040 : i
.tm
.operand_types
[0].bitfield
.disp16
)
9045 output_branch (void)
9051 relax_substateT subtype
;
9055 if (now_seg
== absolute_section
)
9057 as_bad (_("relaxable branches not supported in absolute section"));
9061 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
9062 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
9065 if (i
.prefix
[DATA_PREFIX
] != 0)
9069 code16
^= flip_code16(code16
);
9071 /* Pentium4 branch hints. */
9072 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9073 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9078 if (i
.prefix
[REX_PREFIX
] != 0)
9084 /* BND prefixed jump. */
9085 if (i
.prefix
[BND_PREFIX
] != 0)
9091 if (i
.prefixes
!= 0)
9092 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9094 /* It's always a symbol; End frag & setup for relax.
9095 Make sure there is enough room in this frag for the largest
9096 instruction we may generate in md_convert_frag. This is 2
9097 bytes for the opcode and room for the prefix and largest
9099 frag_grow (prefix
+ 2 + 4);
9100 /* Prefix and 1 opcode byte go in fr_fix. */
9101 p
= frag_more (prefix
+ 1);
9102 if (i
.prefix
[DATA_PREFIX
] != 0)
9103 *p
++ = DATA_PREFIX_OPCODE
;
9104 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
9105 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
9106 *p
++ = i
.prefix
[SEG_PREFIX
];
9107 if (i
.prefix
[BND_PREFIX
] != 0)
9108 *p
++ = BND_PREFIX_OPCODE
;
9109 if (i
.prefix
[REX_PREFIX
] != 0)
9110 *p
++ = i
.prefix
[REX_PREFIX
];
9111 *p
= i
.tm
.base_opcode
;
9113 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
9114 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
9115 else if (cpu_arch_flags
.bitfield
.cpui386
)
9116 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
9118 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
9121 sym
= i
.op
[0].disps
->X_add_symbol
;
9122 off
= i
.op
[0].disps
->X_add_number
;
9124 if (i
.op
[0].disps
->X_op
!= O_constant
9125 && i
.op
[0].disps
->X_op
!= O_symbol
)
9127 /* Handle complex expressions. */
9128 sym
= make_expr_symbol (i
.op
[0].disps
);
9132 frag_now
->tc_frag_data
.code64
= flag_code
== CODE_64BIT
;
9134 /* 1 possible extra opcode + 4 byte displacement go in var part.
9135 Pass reloc in fr_var. */
9136 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
9139 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9140 /* Return TRUE iff PLT32 relocation should be used for branching to
9144 need_plt32_p (symbolS
*s
)
9146 /* PLT32 relocation is ELF only. */
9151 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
9152 krtld support it. */
9156 /* Since there is no need to prepare for PLT branch on x86-64, we
9157 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
9158 be used as a marker for 32-bit PC-relative branches. */
9165 /* Weak or undefined symbol need PLT32 relocation. */
9166 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
9169 /* Non-global symbol doesn't need PLT32 relocation. */
9170 if (! S_IS_EXTERNAL (s
))
9173 /* Other global symbols need PLT32 relocation. NB: Symbol with
9174 non-default visibilities are treated as normal global symbol
9175 so that PLT32 relocation can be used as a marker for 32-bit
9176 PC-relative branches. It is useful for linker relaxation. */
9187 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
9189 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
9191 /* This is a loop or jecxz type instruction. */
9193 if (i
.prefix
[ADDR_PREFIX
] != 0)
9195 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
9198 /* Pentium4 branch hints. */
9199 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9200 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9202 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
9211 if (flag_code
== CODE_16BIT
)
9214 if (i
.prefix
[DATA_PREFIX
] != 0)
9216 frag_opcode_byte (DATA_PREFIX_OPCODE
);
9218 code16
^= flip_code16(code16
);
9226 /* BND prefixed jump. */
9227 if (i
.prefix
[BND_PREFIX
] != 0)
9229 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
9233 if (i
.prefix
[REX_PREFIX
] != 0)
9235 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
9239 if (i
.prefixes
!= 0)
9240 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9242 if (now_seg
== absolute_section
)
9244 abs_section_offset
+= i
.opcode_length
+ size
;
9248 p
= frag_more (i
.opcode_length
+ size
);
9249 switch (i
.opcode_length
)
9252 *p
++ = i
.tm
.base_opcode
>> 8;
9255 *p
++ = i
.tm
.base_opcode
;
9261 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9262 if (flag_code
== CODE_64BIT
&& size
== 4
9263 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
9264 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
9265 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
9268 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
9270 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9271 i
.op
[0].disps
, 1, jump_reloc
);
9273 /* All jumps handled here are signed, but don't unconditionally use a
9274 signed limit check for 32 and 16 bit jumps as we want to allow wrap
9275 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
9280 fixP
->fx_signed
= 1;
9284 if (i
.tm
.mnem_off
== MN_xbegin
)
9285 fixP
->fx_signed
= 1;
9289 if (flag_code
== CODE_64BIT
)
9290 fixP
->fx_signed
= 1;
9296 output_interseg_jump (void)
9304 if (flag_code
== CODE_16BIT
)
9308 if (i
.prefix
[DATA_PREFIX
] != 0)
9315 gas_assert (!i
.prefix
[REX_PREFIX
]);
9321 if (i
.prefixes
!= 0)
9322 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9324 if (now_seg
== absolute_section
)
9326 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9330 /* 1 opcode; 2 segment; offset */
9331 p
= frag_more (prefix
+ 1 + 2 + size
);
9333 if (i
.prefix
[DATA_PREFIX
] != 0)
9334 *p
++ = DATA_PREFIX_OPCODE
;
9336 if (i
.prefix
[REX_PREFIX
] != 0)
9337 *p
++ = i
.prefix
[REX_PREFIX
];
9339 *p
++ = i
.tm
.base_opcode
;
9340 if (i
.op
[1].imms
->X_op
== O_constant
)
9342 offsetT n
= i
.op
[1].imms
->X_add_number
;
9345 && !fits_in_unsigned_word (n
)
9346 && !fits_in_signed_word (n
))
9348 as_bad (_("16-bit jump out of range"));
9351 md_number_to_chars (p
, n
, size
);
9354 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9355 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9358 if (i
.op
[0].imms
->X_op
== O_constant
)
9359 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9361 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9362 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9365 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9370 asection
*seg
= now_seg
;
9371 subsegT subseg
= now_subseg
;
9373 unsigned int alignment
, align_size_1
;
9374 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9375 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9376 unsigned int padding
;
9378 if (!IS_ELF
|| !x86_used_note
)
9381 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9383 /* The .note.gnu.property section layout:
9385 Field Length Contents
9388 n_descsz 4 The note descriptor size
9389 n_type 4 NT_GNU_PROPERTY_TYPE_0
9391 n_desc n_descsz The program property array
9395 /* Create the .note.gnu.property section. */
9396 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9397 bfd_set_section_flags (sec
,
9404 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9415 bfd_set_section_alignment (sec
, alignment
);
9416 elf_section_type (sec
) = SHT_NOTE
;
9418 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9420 isa_1_descsz_raw
= 4 + 4 + 4;
9421 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9422 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9424 feature_2_descsz_raw
= isa_1_descsz
;
9425 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9427 feature_2_descsz_raw
+= 4 + 4 + 4;
9428 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9429 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9432 descsz
= feature_2_descsz
;
9433 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9434 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9436 /* Write n_namsz. */
9437 md_number_to_chars (p
, (valueT
) 4, 4);
9439 /* Write n_descsz. */
9440 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9443 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9446 memcpy (p
+ 4 * 3, "GNU", 4);
9448 /* Write 4-byte type. */
9449 md_number_to_chars (p
+ 4 * 4,
9450 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9452 /* Write 4-byte data size. */
9453 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9455 /* Write 4-byte data. */
9456 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9458 /* Zero out paddings. */
9459 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9461 memset (p
+ 4 * 7, 0, padding
);
9463 /* Write 4-byte type. */
9464 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9465 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9467 /* Write 4-byte data size. */
9468 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9470 /* Write 4-byte data. */
9471 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9472 (valueT
) x86_feature_2_used
, 4);
9474 /* Zero out paddings. */
9475 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9477 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9479 /* We probably can't restore the current segment, for there likely
9482 subseg_set (seg
, subseg
);
9486 x86_support_sframe_p (void)
9488 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9489 return (x86_elf_abi
== X86_64_ABI
);
9493 x86_sframe_ra_tracking_p (void)
9495 /* In AMD64, return address is always stored on the stack at a fixed offset
9496 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9497 Do not track explicitly via an SFrame Frame Row Entry. */
9502 x86_sframe_cfa_ra_offset (void)
9504 gas_assert (x86_elf_abi
== X86_64_ABI
);
9505 return (offsetT
) -8;
9509 x86_sframe_get_abi_arch (void)
9511 unsigned char sframe_abi_arch
= 0;
9513 if (x86_support_sframe_p ())
9515 gas_assert (!target_big_endian
);
9516 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9519 return sframe_abi_arch
;
9525 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9526 const char *frag_now_ptr
)
9528 unsigned int len
= 0;
9530 if (start_frag
!= frag_now
)
9532 const fragS
*fr
= start_frag
;
9537 } while (fr
&& fr
!= frag_now
);
9540 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9543 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9544 be macro-fused with conditional jumps.
9545 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9546 or is one of the following format:
9559 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9561 /* No RIP address. */
9562 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9565 /* No opcodes outside of base encoding space. */
9566 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9569 /* add, sub without add/sub m, imm. */
9570 if (i
.tm
.base_opcode
<= 5
9571 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9572 || ((i
.tm
.base_opcode
| 3) == 0x83
9573 && (i
.tm
.extension_opcode
== 0x5
9574 || i
.tm
.extension_opcode
== 0x0)))
9576 *mf_cmp_p
= mf_cmp_alu_cmp
;
9577 return !(i
.mem_operands
&& i
.imm_operands
);
9580 /* and without and m, imm. */
9581 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9582 || ((i
.tm
.base_opcode
| 3) == 0x83
9583 && i
.tm
.extension_opcode
== 0x4))
9585 *mf_cmp_p
= mf_cmp_test_and
;
9586 return !(i
.mem_operands
&& i
.imm_operands
);
9589 /* test without test m imm. */
9590 if ((i
.tm
.base_opcode
| 1) == 0x85
9591 || (i
.tm
.base_opcode
| 1) == 0xa9
9592 || ((i
.tm
.base_opcode
| 1) == 0xf7
9593 && i
.tm
.extension_opcode
== 0))
9595 *mf_cmp_p
= mf_cmp_test_and
;
9596 return !(i
.mem_operands
&& i
.imm_operands
);
9599 /* cmp without cmp m, imm. */
9600 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9601 || ((i
.tm
.base_opcode
| 3) == 0x83
9602 && (i
.tm
.extension_opcode
== 0x7)))
9604 *mf_cmp_p
= mf_cmp_alu_cmp
;
9605 return !(i
.mem_operands
&& i
.imm_operands
);
9608 /* inc, dec without inc/dec m. */
9609 if ((is_cpu (&i
.tm
, CpuNo64
)
9610 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9611 || ((i
.tm
.base_opcode
| 1) == 0xff
9612 && i
.tm
.extension_opcode
<= 0x1))
9614 *mf_cmp_p
= mf_cmp_incdec
;
9615 return !i
.mem_operands
;
9621 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9624 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9626 /* NB: Don't work with COND_JUMP86 without i386. */
9627 if (!align_branch_power
9628 || now_seg
== absolute_section
9629 || !cpu_arch_flags
.bitfield
.cpui386
9630 || !(align_branch
& align_branch_fused_bit
))
9633 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9635 if (last_insn
.kind
== last_insn_other
9636 || last_insn
.seg
!= now_seg
)
9639 as_warn_where (last_insn
.file
, last_insn
.line
,
9640 _("`%s` skips -malign-branch-boundary on `%s`"),
9641 last_insn
.name
, insn_name (&i
.tm
));
9647 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9650 add_branch_prefix_frag_p (void)
9652 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9653 to PadLock instructions since they include prefixes in opcode. */
9654 if (!align_branch_power
9655 || !align_branch_prefix_size
9656 || now_seg
== absolute_section
9657 || is_cpu (&i
.tm
, CpuPadLock
)
9658 || !cpu_arch_flags
.bitfield
.cpui386
)
9661 /* Don't add prefix if it is a prefix or there is no operand in case
9662 that segment prefix is special. */
9663 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9666 if (last_insn
.kind
== last_insn_other
9667 || last_insn
.seg
!= now_seg
)
9671 as_warn_where (last_insn
.file
, last_insn
.line
,
9672 _("`%s` skips -malign-branch-boundary on `%s`"),
9673 last_insn
.name
, insn_name (&i
.tm
));
9678 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9681 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9682 enum mf_jcc_kind
*mf_jcc_p
)
9686 /* NB: Don't work with COND_JUMP86 without i386. */
9687 if (!align_branch_power
9688 || now_seg
== absolute_section
9689 || !cpu_arch_flags
.bitfield
.cpui386
9690 || i
.tm
.opcode_space
!= SPACE_BASE
)
9695 /* Check for jcc and direct jmp. */
9696 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9698 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9700 *branch_p
= align_branch_jmp
;
9701 add_padding
= align_branch
& align_branch_jmp_bit
;
9705 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9706 igore the lowest bit. */
9707 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9708 *branch_p
= align_branch_jcc
;
9709 if ((align_branch
& align_branch_jcc_bit
))
9713 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9716 *branch_p
= align_branch_ret
;
9717 if ((align_branch
& align_branch_ret_bit
))
9722 /* Check for indirect jmp, direct and indirect calls. */
9723 if (i
.tm
.base_opcode
== 0xe8)
9726 *branch_p
= align_branch_call
;
9727 if ((align_branch
& align_branch_call_bit
))
9730 else if (i
.tm
.base_opcode
== 0xff
9731 && (i
.tm
.extension_opcode
== 2
9732 || i
.tm
.extension_opcode
== 4))
9734 /* Indirect call and jmp. */
9735 *branch_p
= align_branch_indirect
;
9736 if ((align_branch
& align_branch_indirect_bit
))
9743 && (i
.op
[0].disps
->X_op
== O_symbol
9744 || (i
.op
[0].disps
->X_op
== O_subtract
9745 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9747 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9748 /* No padding to call to global or undefined tls_get_addr. */
9749 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9750 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9756 && last_insn
.kind
!= last_insn_other
9757 && last_insn
.seg
== now_seg
)
9760 as_warn_where (last_insn
.file
, last_insn
.line
,
9761 _("`%s` skips -malign-branch-boundary on `%s`"),
9762 last_insn
.name
, insn_name (&i
.tm
));
9772 fragS
*insn_start_frag
;
9773 offsetT insn_start_off
;
9774 fragS
*fragP
= NULL
;
9775 enum align_branch_kind branch
= align_branch_none
;
9776 /* The initializer is arbitrary just to avoid uninitialized error.
9777 it's actually either assigned in add_branch_padding_frag_p
9778 or never be used. */
9779 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9781 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9782 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9784 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9785 || is_cpu (&i
.tm
, CpuAMX_TILE
))
9786 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9788 if (is_cpu (&i
.tm
, Cpu8087
)
9789 || is_cpu (&i
.tm
, Cpu287
)
9790 || is_cpu (&i
.tm
, Cpu387
)
9791 || is_cpu (&i
.tm
, Cpu687
)
9792 || is_cpu (&i
.tm
, CpuFISTTP
))
9793 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9795 if ((i
.xstate
& xstate_mmx
)
9796 || i
.tm
.mnem_off
== MN_emms
9797 || i
.tm
.mnem_off
== MN_femms
)
9798 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9802 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9803 i
.xstate
|= xstate_zmm
;
9804 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9805 i
.xstate
|= xstate_ymm
;
9806 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9807 i
.xstate
|= xstate_xmm
;
9810 /* vzeroall / vzeroupper */
9811 if (i
.tm
.base_opcode
== 0x77 && is_cpu (&i
.tm
, CpuAVX
))
9812 i
.xstate
|= xstate_ymm
;
9814 if ((i
.xstate
& xstate_xmm
)
9815 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9816 || (i
.tm
.base_opcode
== 0xae
9817 && (is_cpu (&i
.tm
, CpuSSE
)
9818 || is_cpu (&i
.tm
, CpuAVX
)))
9819 || is_cpu (&i
.tm
, CpuWideKL
)
9820 || is_cpu (&i
.tm
, CpuKL
))
9821 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9823 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9824 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9825 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9826 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9827 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9828 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9829 if (is_cpu (&i
.tm
, CpuFXSR
))
9830 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9831 if (is_cpu (&i
.tm
, CpuXsave
))
9832 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9833 if (is_cpu (&i
.tm
, CpuXsaveopt
))
9834 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9835 if (is_cpu (&i
.tm
, CpuXSAVEC
))
9836 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9838 if (x86_feature_2_used
9839 || is_cpu (&i
.tm
, CpuCMOV
)
9840 || is_cpu (&i
.tm
, CpuSYSCALL
)
9841 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9842 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9843 if (is_cpu (&i
.tm
, CpuSSE3
)
9844 || is_cpu (&i
.tm
, CpuSSSE3
)
9845 || is_cpu (&i
.tm
, CpuSSE4_1
)
9846 || is_cpu (&i
.tm
, CpuSSE4_2
)
9847 || is_cpu (&i
.tm
, CpuCX16
)
9848 || is_cpu (&i
.tm
, CpuPOPCNT
)
9849 /* LAHF-SAHF insns in 64-bit mode. */
9850 || (flag_code
== CODE_64BIT
9851 && (i
.tm
.base_opcode
| 1) == 0x9f
9852 && i
.tm
.opcode_space
== SPACE_BASE
))
9853 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9854 if (is_cpu (&i
.tm
, CpuAVX
)
9855 || is_cpu (&i
.tm
, CpuAVX2
)
9856 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9857 XOP, FMA4, LPW, TBM, and AMX. */
9858 || (i
.tm
.opcode_modifier
.vex
9859 && !is_cpu (&i
.tm
, CpuAVX512F
)
9860 && !is_cpu (&i
.tm
, CpuAVX512BW
)
9861 && !is_cpu (&i
.tm
, CpuAVX512DQ
)
9862 && !is_cpu (&i
.tm
, CpuXOP
)
9863 && !is_cpu (&i
.tm
, CpuFMA4
)
9864 && !is_cpu (&i
.tm
, CpuLWP
)
9865 && !is_cpu (&i
.tm
, CpuTBM
)
9866 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9867 || is_cpu (&i
.tm
, CpuF16C
)
9868 || is_cpu (&i
.tm
, CpuFMA
)
9869 || is_cpu (&i
.tm
, CpuLZCNT
)
9870 || is_cpu (&i
.tm
, CpuMovbe
)
9871 || is_cpu (&i
.tm
, CpuXSAVES
)
9872 || (x86_feature_2_used
9873 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9874 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9875 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9876 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9877 if (is_cpu (&i
.tm
, CpuAVX512F
)
9878 || is_cpu (&i
.tm
, CpuAVX512BW
)
9879 || is_cpu (&i
.tm
, CpuAVX512DQ
)
9880 || is_cpu (&i
.tm
, CpuAVX512VL
)
9881 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9882 AVX512-4FMAPS, and AVX512-4VNNIW. */
9883 || (i
.tm
.opcode_modifier
.evex
9884 && !is_cpu (&i
.tm
, CpuAVX512ER
)
9885 && !is_cpu (&i
.tm
, CpuAVX512PF
)
9886 && !is_cpu (&i
.tm
, CpuAVX512_4FMAPS
)
9887 && !is_cpu (&i
.tm
, CpuAVX512_4VNNIW
)))
9888 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9892 /* Tie dwarf2 debug info to the address at the start of the insn.
9893 We can't do this after the insn has been output as the current
9894 frag may have been closed off. eg. by frag_var. */
9895 dwarf2_emit_insn (0);
9897 insn_start_frag
= frag_now
;
9898 insn_start_off
= frag_now_fix ();
9900 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9903 /* Branch can be 8 bytes. Leave some room for prefixes. */
9904 unsigned int max_branch_padding_size
= 14;
9906 /* Align section to boundary. */
9907 record_alignment (now_seg
, align_branch_power
);
9909 /* Make room for padding. */
9910 frag_grow (max_branch_padding_size
);
9912 /* Start of the padding. */
9917 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9918 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9921 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9922 fragP
->tc_frag_data
.branch_type
= branch
;
9923 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9926 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9927 && !pre_386_16bit_warned
)
9929 as_warn (_("use .code16 to ensure correct addressing mode"));
9930 pre_386_16bit_warned
= true;
9934 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9936 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9937 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9939 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9940 output_interseg_jump ();
9943 /* Output normal instructions here. */
9947 enum mf_cmp_kind mf_cmp
;
9950 && (i
.tm
.base_opcode
== 0xaee8
9951 || i
.tm
.base_opcode
== 0xaef0
9952 || i
.tm
.base_opcode
== 0xaef8))
9954 /* Encode lfence, mfence, and sfence as
9955 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9956 if (flag_code
== CODE_16BIT
)
9957 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9958 else if (omit_lock_prefix
)
9959 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9961 else if (now_seg
!= absolute_section
)
9963 offsetT val
= 0x240483f0ULL
;
9966 md_number_to_chars (p
, val
, 5);
9969 abs_section_offset
+= 5;
9973 /* Some processors fail on LOCK prefix. This options makes
9974 assembler ignore LOCK prefix and serves as a workaround. */
9975 if (omit_lock_prefix
)
9977 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9978 && i
.tm
.opcode_modifier
.isprefix
)
9980 i
.prefix
[LOCK_PREFIX
] = 0;
9984 /* Skip if this is a branch. */
9986 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9988 /* Make room for padding. */
9989 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9994 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9995 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9998 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9999 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
10000 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
10002 else if (add_branch_prefix_frag_p ())
10004 unsigned int max_prefix_size
= align_branch_prefix_size
;
10006 /* Make room for padding. */
10007 frag_grow (max_prefix_size
);
10012 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
10013 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
10016 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
10019 /* Since the VEX/EVEX prefix contains the implicit prefix, we
10020 don't need the explicit prefix. */
10021 if (!is_any_vex_encoding (&i
.tm
))
10023 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
10032 if (!is_cpu (&i
.tm
, CpuPadLock
)
10033 || (i
.prefix
[REP_PREFIX
] != 0xf3))
10037 switch (i
.opcode_length
)
10042 /* Check for pseudo prefixes. */
10043 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
10045 as_bad_where (insn_start_frag
->fr_file
,
10046 insn_start_frag
->fr_line
,
10047 _("pseudo prefix without instruction"));
10057 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10058 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
10059 R_X86_64_GOTTPOFF relocation so that linker can safely
10060 perform IE->LE optimization. A dummy REX_OPCODE prefix
10061 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
10062 relocation for GDesc -> IE/LE optimization. */
10063 if (x86_elf_abi
== X86_64_X32_ABI
10065 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
10066 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
10067 && i
.prefix
[REX_PREFIX
] == 0)
10068 add_prefix (REX_OPCODE
);
10071 /* The prefix bytes. */
10072 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
10074 frag_opcode_byte (*q
);
10078 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
10084 frag_opcode_byte (*q
);
10087 /* There should be no other prefixes for instructions
10088 with VEX prefix. */
10092 /* For EVEX instructions i.vrex should become 0 after
10093 build_evex_prefix. For VEX instructions upper 16 registers
10094 aren't available, so VREX should be 0. */
10097 /* Now the VEX prefix. */
10098 if (now_seg
!= absolute_section
)
10100 p
= frag_more (i
.vex
.length
);
10101 for (j
= 0; j
< i
.vex
.length
; j
++)
10102 p
[j
] = i
.vex
.bytes
[j
];
10105 abs_section_offset
+= i
.vex
.length
;
10108 /* Now the opcode; be careful about word order here! */
10109 j
= i
.opcode_length
;
10111 switch (i
.tm
.opcode_space
)
10126 if (now_seg
== absolute_section
)
10127 abs_section_offset
+= j
;
10130 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
10136 && i
.tm
.opcode_space
!= SPACE_BASE
)
10139 if (i
.tm
.opcode_space
!= SPACE_0F
)
10140 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
10144 switch (i
.opcode_length
)
10147 /* Put out high byte first: can't use md_number_to_chars! */
10148 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
10149 /* Fall through. */
10151 *p
= i
.tm
.base_opcode
& 0xff;
10160 /* Now the modrm byte and sib byte (if present). */
10161 if (i
.tm
.opcode_modifier
.modrm
)
10163 frag_opcode_byte ((i
.rm
.regmem
<< 0)
10165 | (i
.rm
.mode
<< 6));
10166 /* If i.rm.regmem == ESP (4)
10167 && i.rm.mode != (Register mode)
10169 ==> need second modrm byte. */
10170 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
10172 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
10173 frag_opcode_byte ((i
.sib
.base
<< 0)
10174 | (i
.sib
.index
<< 3)
10175 | (i
.sib
.scale
<< 6));
10178 if (i
.disp_operands
)
10179 output_disp (insn_start_frag
, insn_start_off
);
10181 if (i
.imm_operands
)
10182 output_imm (insn_start_frag
, insn_start_off
);
10185 * frag_now_fix () returning plain abs_section_offset when we're in the
10186 * absolute section, and abs_section_offset not getting updated as data
10187 * gets added to the frag breaks the logic below.
10189 if (now_seg
!= absolute_section
)
10191 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
10193 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
10197 /* NB: Don't add prefix with GOTPC relocation since
10198 output_disp() above depends on the fixed encoding
10199 length. Can't add prefix with TLS relocation since
10200 it breaks TLS linker optimization. */
10201 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
10202 /* Prefix count on the current instruction. */
10203 unsigned int count
= i
.vex
.length
;
10205 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
10206 /* REX byte is encoded in VEX/EVEX prefix. */
10207 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
10210 /* Count prefixes for extended opcode maps. */
10212 switch (i
.tm
.opcode_space
)
10227 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10230 /* Set the maximum prefix size in BRANCH_PREFIX
10232 if (fragP
->tc_frag_data
.max_bytes
> max
)
10233 fragP
->tc_frag_data
.max_bytes
= max
;
10234 if (fragP
->tc_frag_data
.max_bytes
> count
)
10235 fragP
->tc_frag_data
.max_bytes
-= count
;
10237 fragP
->tc_frag_data
.max_bytes
= 0;
10241 /* Remember the maximum prefix size in FUSED_JCC_PADDING
10243 unsigned int max_prefix_size
;
10244 if (align_branch_prefix_size
> max
)
10245 max_prefix_size
= max
;
10247 max_prefix_size
= align_branch_prefix_size
;
10248 if (max_prefix_size
> count
)
10249 fragP
->tc_frag_data
.max_prefix_length
10250 = max_prefix_size
- count
;
10253 /* Use existing segment prefix if possible. Use CS
10254 segment prefix in 64-bit mode. In 32-bit mode, use SS
10255 segment prefix with ESP/EBP base register and use DS
10256 segment prefix without ESP/EBP base register. */
10257 if (i
.prefix
[SEG_PREFIX
])
10258 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
10259 else if (flag_code
== CODE_64BIT
)
10260 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
10261 else if (i
.base_reg
10262 && (i
.base_reg
->reg_num
== 4
10263 || i
.base_reg
->reg_num
== 5))
10264 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
10266 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
10271 /* NB: Don't work with COND_JUMP86 without i386. */
10272 if (align_branch_power
10273 && now_seg
!= absolute_section
10274 && cpu_arch_flags
.bitfield
.cpui386
)
10276 /* Terminate each frag so that we can add prefix and check for
10278 frag_wane (frag_now
);
10285 pi ("" /*line*/, &i
);
10287 #endif /* DEBUG386 */
10290 /* Return the size of the displacement operand N. */
10293 disp_size (unsigned int n
)
10297 if (i
.types
[n
].bitfield
.disp64
)
10299 else if (i
.types
[n
].bitfield
.disp8
)
10301 else if (i
.types
[n
].bitfield
.disp16
)
10306 /* Return the size of the immediate operand N. */
10309 imm_size (unsigned int n
)
10312 if (i
.types
[n
].bitfield
.imm64
)
10314 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10316 else if (i
.types
[n
].bitfield
.imm16
)
10322 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10327 for (n
= 0; n
< i
.operands
; n
++)
10329 if (operand_type_check (i
.types
[n
], disp
))
10331 int size
= disp_size (n
);
10333 if (now_seg
== absolute_section
)
10334 abs_section_offset
+= size
;
10335 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10337 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10339 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10341 p
= frag_more (size
);
10342 md_number_to_chars (p
, val
, size
);
10346 enum bfd_reloc_code_real reloc_type
;
10347 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10348 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10349 && (!want_disp32 (&i
.tm
)
10350 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10351 && !i
.types
[n
].bitfield
.baseindex
)))
10355 /* We can't have 8 bit displacement here. */
10356 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10358 /* The PC relative address is computed relative
10359 to the instruction boundary, so in case immediate
10360 fields follows, we need to adjust the value. */
10361 if (pcrel
&& i
.imm_operands
)
10366 for (n1
= 0; n1
< i
.operands
; n1
++)
10367 if (operand_type_check (i
.types
[n1
], imm
))
10369 /* Only one immediate is allowed for PC
10370 relative address, except with .insn. */
10371 gas_assert (sz
== 0 || dot_insn ());
10372 sz
+= imm_size (n1
);
10374 /* We should find at least one immediate. */
10375 gas_assert (sz
!= 0);
10376 i
.op
[n
].disps
->X_add_number
-= sz
;
10379 p
= frag_more (size
);
10380 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10382 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10383 && (((reloc_type
== BFD_RELOC_32
10384 || reloc_type
== BFD_RELOC_X86_64_32S
10385 || (reloc_type
== BFD_RELOC_64
10387 && (i
.op
[n
].disps
->X_op
== O_symbol
10388 || (i
.op
[n
].disps
->X_op
== O_add
10389 && ((symbol_get_value_expression
10390 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10392 || reloc_type
== BFD_RELOC_32_PCREL
))
10396 reloc_type
= BFD_RELOC_386_GOTPC
;
10397 i
.has_gotpc_tls_reloc
= true;
10398 i
.op
[n
].disps
->X_add_number
+=
10399 encoding_length (insn_start_frag
, insn_start_off
, p
);
10401 else if (reloc_type
== BFD_RELOC_64
)
10402 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10404 /* Don't do the adjustment for x86-64, as there
10405 the pcrel addressing is relative to the _next_
10406 insn, and that is taken care of in other code. */
10407 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10409 else if (align_branch_power
)
10411 switch (reloc_type
)
10413 case BFD_RELOC_386_TLS_GD
:
10414 case BFD_RELOC_386_TLS_LDM
:
10415 case BFD_RELOC_386_TLS_IE
:
10416 case BFD_RELOC_386_TLS_IE_32
:
10417 case BFD_RELOC_386_TLS_GOTIE
:
10418 case BFD_RELOC_386_TLS_GOTDESC
:
10419 case BFD_RELOC_386_TLS_DESC_CALL
:
10420 case BFD_RELOC_X86_64_TLSGD
:
10421 case BFD_RELOC_X86_64_TLSLD
:
10422 case BFD_RELOC_X86_64_GOTTPOFF
:
10423 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10424 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10425 i
.has_gotpc_tls_reloc
= true;
10430 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10431 size
, i
.op
[n
].disps
, pcrel
,
10434 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10435 && !i
.prefix
[ADDR_PREFIX
])
10436 fixP
->fx_signed
= 1;
10438 /* Check for "call/jmp *mem", "mov mem, %reg",
10439 "test %reg, mem" and "binop mem, %reg" where binop
10440 is one of adc, add, and, cmp, or, sbb, sub, xor
10441 instructions without data prefix. Always generate
10442 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10443 if (i
.prefix
[DATA_PREFIX
] == 0
10444 && (generate_relax_relocations
10447 && i
.rm
.regmem
== 5))
10449 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10450 && i
.tm
.opcode_space
== SPACE_BASE
10451 && ((i
.operands
== 1
10452 && i
.tm
.base_opcode
== 0xff
10453 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10454 || (i
.operands
== 2
10455 && (i
.tm
.base_opcode
== 0x8b
10456 || i
.tm
.base_opcode
== 0x85
10457 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10461 fixP
->fx_tcbit
= i
.rex
!= 0;
10463 && (i
.base_reg
->reg_num
== RegIP
))
10464 fixP
->fx_tcbit2
= 1;
10467 fixP
->fx_tcbit2
= 1;
10475 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10480 for (n
= 0; n
< i
.operands
; n
++)
10482 if (operand_type_check (i
.types
[n
], imm
))
10484 int size
= imm_size (n
);
10486 if (now_seg
== absolute_section
)
10487 abs_section_offset
+= size
;
10488 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10492 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10494 p
= frag_more (size
);
10495 md_number_to_chars (p
, val
, size
);
10499 /* Not absolute_section.
10500 Need a 32-bit fixup (don't support 8bit
10501 non-absolute imms). Try to support other
10503 enum bfd_reloc_code_real reloc_type
;
10506 if (i
.types
[n
].bitfield
.imm32s
10507 && (i
.suffix
== QWORD_MNEM_SUFFIX
10508 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
10509 || (i
.prefix
[REX_PREFIX
] & REX_W
)
10515 p
= frag_more (size
);
10516 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10518 /* This is tough to explain. We end up with this one if we
10519 * have operands that look like
10520 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10521 * obtain the absolute address of the GOT, and it is strongly
10522 * preferable from a performance point of view to avoid using
10523 * a runtime relocation for this. The actual sequence of
10524 * instructions often look something like:
10529 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10531 * The call and pop essentially return the absolute address
10532 * of the label .L66 and store it in %ebx. The linker itself
10533 * will ultimately change the first operand of the addl so
10534 * that %ebx points to the GOT, but to keep things simple, the
10535 * .o file must have this operand set so that it generates not
10536 * the absolute address of .L66, but the absolute address of
10537 * itself. This allows the linker itself simply treat a GOTPC
10538 * relocation as asking for a pcrel offset to the GOT to be
10539 * added in, and the addend of the relocation is stored in the
10540 * operand field for the instruction itself.
10542 * Our job here is to fix the operand so that it would add
10543 * the correct offset so that %ebx would point to itself. The
10544 * thing that is tricky is that .-.L66 will point to the
10545 * beginning of the instruction, so we need to further modify
10546 * the operand so that it will point to itself. There are
10547 * other cases where you have something like:
10549 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10551 * and here no correction would be required. Internally in
10552 * the assembler we treat operands of this form as not being
10553 * pcrel since the '.' is explicitly mentioned, and I wonder
10554 * whether it would simplify matters to do it this way. Who
10555 * knows. In earlier versions of the PIC patches, the
10556 * pcrel_adjust field was used to store the correction, but
10557 * since the expression is not pcrel, I felt it would be
10558 * confusing to do it this way. */
10560 if ((reloc_type
== BFD_RELOC_32
10561 || reloc_type
== BFD_RELOC_X86_64_32S
10562 || reloc_type
== BFD_RELOC_64
)
10564 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10565 && (i
.op
[n
].imms
->X_op
== O_symbol
10566 || (i
.op
[n
].imms
->X_op
== O_add
10567 && ((symbol_get_value_expression
10568 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10572 reloc_type
= BFD_RELOC_386_GOTPC
;
10573 else if (size
== 4)
10574 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10575 else if (size
== 8)
10576 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10577 i
.has_gotpc_tls_reloc
= true;
10578 i
.op
[n
].imms
->X_add_number
+=
10579 encoding_length (insn_start_frag
, insn_start_off
, p
);
10581 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10582 i
.op
[n
].imms
, 0, reloc_type
);
10588 /* x86_cons_fix_new is called via the expression parsing code when a
10589 reloc is needed. We use this hook to get the correct .got reloc. */
10590 static int cons_sign
= -1;
10593 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10594 expressionS
*exp
, bfd_reloc_code_real_type r
)
10596 r
= reloc (len
, 0, cons_sign
, r
);
10599 if (exp
->X_op
== O_secrel
)
10601 exp
->X_op
= O_symbol
;
10602 r
= BFD_RELOC_32_SECREL
;
10604 else if (exp
->X_op
== O_secidx
)
10605 r
= BFD_RELOC_16_SECIDX
;
10608 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10611 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10612 purpose of the `.dc.a' internal pseudo-op. */
10615 x86_address_bytes (void)
10617 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10619 return stdoutput
->arch_info
->bits_per_address
/ 8;
10622 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10623 || defined (LEX_AT)) && !defined (TE_PE)
10624 # define lex_got(reloc, adjust, types) NULL
10626 /* Parse operands of the form
10627 <symbol>@GOTOFF+<nnn>
10628 and similar .plt or .got references.
10630 If we find one, set up the correct relocation in RELOC and copy the
10631 input string, minus the `@GOTOFF' into a malloc'd buffer for
10632 parsing by the calling routine. Return this buffer, and if ADJUST
10633 is non-null set it to the length of the string we removed from the
10634 input line. Otherwise return NULL. */
10636 lex_got (enum bfd_reloc_code_real
*rel
,
10638 i386_operand_type
*types
)
10640 /* Some of the relocations depend on the size of what field is to
10641 be relocated. But in our callers i386_immediate and i386_displacement
10642 we don't yet know the operand size (this will be set by insn
10643 matching). Hence we record the word32 relocation here,
10644 and adjust the reloc according to the real size in reloc(). */
10645 static const struct
10649 const enum bfd_reloc_code_real rel
[2];
10650 const i386_operand_type types64
;
10651 bool need_GOT_symbol
;
10656 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10657 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10658 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10659 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10660 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10661 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10662 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10663 { .imm64 = 1, .disp64 = 1 } }
10666 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10667 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10668 BFD_RELOC_SIZE32
},
10669 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10671 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10672 BFD_RELOC_X86_64_PLTOFF64
},
10673 { .bitfield
= { .imm64
= 1 } }, true },
10674 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10675 BFD_RELOC_X86_64_PLT32
},
10676 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10677 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10678 BFD_RELOC_X86_64_GOTPLT64
},
10679 OPERAND_TYPE_IMM64_DISP64
, true },
10680 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10681 BFD_RELOC_X86_64_GOTOFF64
},
10682 OPERAND_TYPE_IMM64_DISP64
, true },
10683 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10684 BFD_RELOC_X86_64_GOTPCREL
},
10685 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10686 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10687 BFD_RELOC_X86_64_TLSGD
},
10688 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10689 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10690 _dummy_first_bfd_reloc_code_real
},
10691 OPERAND_TYPE_NONE
, true },
10692 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10693 BFD_RELOC_X86_64_TLSLD
},
10694 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10695 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10696 BFD_RELOC_X86_64_GOTTPOFF
},
10697 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10698 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10699 BFD_RELOC_X86_64_TPOFF32
},
10700 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10701 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10702 _dummy_first_bfd_reloc_code_real
},
10703 OPERAND_TYPE_NONE
, true },
10704 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10705 BFD_RELOC_X86_64_DTPOFF32
},
10706 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10707 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10708 _dummy_first_bfd_reloc_code_real
},
10709 OPERAND_TYPE_NONE
, true },
10710 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10711 _dummy_first_bfd_reloc_code_real
},
10712 OPERAND_TYPE_NONE
, true },
10713 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10714 BFD_RELOC_X86_64_GOT32
},
10715 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10716 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10717 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10718 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10719 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10720 BFD_RELOC_X86_64_TLSDESC_CALL
},
10721 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10723 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10724 BFD_RELOC_32_SECREL
},
10725 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10728 #undef OPERAND_TYPE_IMM32_32S_DISP32
10729 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10730 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10731 #undef OPERAND_TYPE_IMM64_DISP64
10737 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10742 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10743 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10746 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10748 int len
= gotrel
[j
].len
;
10749 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10751 if (gotrel
[j
].rel
[object_64bit
] != 0)
10754 char *tmpbuf
, *past_reloc
;
10756 *rel
= gotrel
[j
].rel
[object_64bit
];
10760 if (flag_code
!= CODE_64BIT
)
10762 types
->bitfield
.imm32
= 1;
10763 types
->bitfield
.disp32
= 1;
10766 *types
= gotrel
[j
].types64
;
10769 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10770 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10772 /* The length of the first part of our input line. */
10773 first
= cp
- input_line_pointer
;
10775 /* The second part goes from after the reloc token until
10776 (and including) an end_of_line char or comma. */
10777 past_reloc
= cp
+ 1 + len
;
10779 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10781 second
= cp
+ 1 - past_reloc
;
10783 /* Allocate and copy string. The trailing NUL shouldn't
10784 be necessary, but be safe. */
10785 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10786 memcpy (tmpbuf
, input_line_pointer
, first
);
10787 if (second
!= 0 && *past_reloc
!= ' ')
10788 /* Replace the relocation token with ' ', so that
10789 errors like foo@GOTOFF1 will be detected. */
10790 tmpbuf
[first
++] = ' ';
10792 /* Increment length by 1 if the relocation token is
10797 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10798 tmpbuf
[first
+ second
] = '\0';
10802 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10803 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10808 /* Might be a symbol version string. Don't as_bad here. */
10813 bfd_reloc_code_real_type
10814 x86_cons (expressionS
*exp
, int size
)
10816 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10818 intel_syntax
= -intel_syntax
;
10820 expr_mode
= expr_operator_none
;
10822 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10823 && !defined (LEX_AT)) \
10825 if (size
== 4 || (object_64bit
&& size
== 8))
10827 /* Handle @GOTOFF and the like in an expression. */
10829 char *gotfree_input_line
;
10832 save
= input_line_pointer
;
10833 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10834 if (gotfree_input_line
)
10835 input_line_pointer
= gotfree_input_line
;
10839 if (gotfree_input_line
)
10841 /* expression () has merrily parsed up to the end of line,
10842 or a comma - in the wrong buffer. Transfer how far
10843 input_line_pointer has moved to the right buffer. */
10844 input_line_pointer
= (save
10845 + (input_line_pointer
- gotfree_input_line
)
10847 free (gotfree_input_line
);
10848 if (exp
->X_op
== O_constant
10849 || exp
->X_op
== O_absent
10850 || exp
->X_op
== O_illegal
10851 || exp
->X_op
== O_register
10852 || exp
->X_op
== O_big
)
10854 char c
= *input_line_pointer
;
10855 *input_line_pointer
= 0;
10856 as_bad (_("missing or invalid expression `%s'"), save
);
10857 *input_line_pointer
= c
;
10859 else if ((got_reloc
== BFD_RELOC_386_PLT32
10860 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10861 && exp
->X_op
!= O_symbol
)
10863 char c
= *input_line_pointer
;
10864 *input_line_pointer
= 0;
10865 as_bad (_("invalid PLT expression `%s'"), save
);
10866 *input_line_pointer
= c
;
10874 intel_syntax
= -intel_syntax
;
10877 i386_intel_simplify (exp
);
10879 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10880 if (size
<= 4 && expr_mode
== expr_operator_present
10881 && exp
->X_op
== O_constant
&& !object_64bit
)
10882 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10888 signed_cons (int size
)
10897 s_insn (int dummy ATTRIBUTE_UNUSED
)
10899 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
10900 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10904 bool vex
= false, xop
= false, evex
= false;
10905 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10909 saved_char
= *saved_ilp
;
10912 end
= parse_insn (line
, mnemonic
, true);
10916 *saved_ilp
= saved_char
;
10917 ignore_rest_of_line ();
10921 line
+= end
- line
;
10923 current_templates
= &tt
;
10924 i
.tm
.mnem_off
= MN__insn
;
10925 i
.tm
.extension_opcode
= None
;
10927 if (startswith (line
, "VEX")
10928 && (line
[3] == '.' || is_space_char (line
[3])))
10933 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10936 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10938 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10939 && (*e
== '.' || is_space_char (*e
)))
10942 /* Arrange for build_vex_prefix() to emit 0x8f. */
10943 i
.tm
.opcode_space
= SPACE_XOP08
;
10944 i
.insn_opcode_space
= n
;
10948 else if (startswith (line
, "EVEX")
10949 && (line
[4] == '.' || is_space_char (line
[4])))
10956 ? i
.vec_encoding
== vex_encoding_evex
10958 ? i
.vec_encoding
== vex_encoding_vex
10959 || i
.vec_encoding
== vex_encoding_vex3
10960 : i
.vec_encoding
!= vex_encoding_default
)
10962 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
10966 if (line
> end
&& i
.vec_encoding
== vex_encoding_default
)
10967 i
.vec_encoding
= evex
? vex_encoding_evex
: vex_encoding_vex
;
10969 if (i
.vec_encoding
!= vex_encoding_default
)
10971 /* Only address size and segment override prefixes are permitted with
10972 VEX/XOP/EVEX encodings. */
10973 const unsigned char *p
= i
.prefix
;
10975 for (j
= 0; j
< ARRAY_SIZE (i
.prefix
); ++j
, ++p
)
10986 as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
10992 if (line
> end
&& *line
== '.')
10994 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
11002 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11004 i
.tm
.opcode_modifier
.vex
= VEX128
;
11009 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11011 i
.tm
.opcode_modifier
.vex
= VEX256
;
11016 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11021 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
11025 if (line
[3] == 'G')
11028 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11030 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11036 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
11041 if (line
[2] == '2' && line
[3] == '8')
11044 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11046 i
.tm
.opcode_modifier
.vex
= VEX128
;
11052 if (line
[2] == '5' && line
[3] == '6')
11055 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11057 i
.tm
.opcode_modifier
.vex
= VEX256
;
11063 if (evex
&& line
[2] == '1' && line
[3] == '2')
11065 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11072 if (line
> end
&& *line
== '.')
11074 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
11078 if (line
[2] == 'P')
11083 if (line
[2] == '6')
11085 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
11090 case 'F': case 'f':
11091 if (line
[2] == '3')
11093 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
11096 else if (line
[2] == '2')
11098 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
11105 if (line
> end
&& !xop
&& *line
== '.')
11107 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
11111 if (TOUPPER (line
[2]) != 'F')
11113 if (line
[3] == '.' || is_space_char (line
[3]))
11115 i
.insn_opcode_space
= SPACE_0F
;
11118 else if (line
[3] == '3'
11119 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
11120 && (line
[5] == '.' || is_space_char (line
[5])))
11122 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
11128 if (ISDIGIT (line
[2]) && line
[2] != '0')
11131 unsigned long n
= strtoul (line
+ 2, &e
, 10);
11133 if (n
<= (evex
? 15 : 31)
11134 && (*e
== '.' || is_space_char (*e
)))
11136 i
.insn_opcode_space
= n
;
11144 if (line
> end
&& *line
== '.' && line
[1] == 'W')
11146 /* VEX.W, XOP.W, EVEX.W */
11150 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11154 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11158 if (line
[3] == 'G')
11160 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11166 if (i
.tm
.opcode_modifier
.vexw
)
11170 if (line
> end
&& *line
&& !is_space_char (*line
))
11172 /* Improve diagnostic a little. */
11173 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
11178 /* Before processing the opcode expression, find trailing "+r" or
11179 "/<digit>" specifiers. */
11180 for (ptr
= line
; ; ++ptr
)
11185 ptr
= strpbrk (ptr
, "+/,");
11186 if (ptr
== NULL
|| *ptr
== ',')
11189 if (*ptr
== '+' && ptr
[1] == 'r'
11190 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11194 i
.short_form
= true;
11198 if (*ptr
== '/' && ISDIGIT (ptr
[1])
11199 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
11201 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11205 i
.tm
.extension_opcode
= n
;
11206 i
.tm
.opcode_modifier
.modrm
= 1;
11211 input_line_pointer
= line
;
11212 val
= get_absolute_expression ();
11213 line
= input_line_pointer
;
11215 if (i
.short_form
&& (val
& 7))
11216 as_warn ("`+r' assumes low three opcode bits to be clear");
11218 for (j
= 1; j
< sizeof(val
); ++j
)
11219 if (!(val
>> (j
* 8)))
11222 /* Trim off a prefix if present. */
11223 if (j
> 1 && !vex
&& !xop
&& !evex
)
11225 uint8_t byte
= val
>> ((j
- 1) * 8);
11229 case DATA_PREFIX_OPCODE
:
11230 case REPE_PREFIX_OPCODE
:
11231 case REPNE_PREFIX_OPCODE
:
11232 if (!add_prefix (byte
))
11234 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
11239 /* Trim off encoding space. */
11240 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
11242 uint8_t byte
= val
>> ((--j
- 1) * 8);
11244 i
.insn_opcode_space
= SPACE_0F
;
11245 switch (byte
& -(j
> 1))
11248 i
.insn_opcode_space
= SPACE_0F38
;
11252 i
.insn_opcode_space
= SPACE_0F3A
;
11256 i
.tm
.opcode_space
= i
.insn_opcode_space
;
11257 val
&= ((uint64_t)1 << (j
* 8)) - 1;
11259 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
11260 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
11261 Also avoid hitting abort() there or in build_evex_prefix(). */
11262 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
11267 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
11270 i
.opcode_length
= j
;
11272 /* Handle operands, if any. */
11275 i386_operand_type combined
;
11276 expressionS
*disp_exp
= NULL
;
11281 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
11289 as_bad (_("expecting operand after ','; got nothing"));
11293 if (i
.mem_operands
> 1)
11295 as_bad (_("too many memory references for `%s'"),
11296 &i386_mnemonics
[MN__insn
]);
11300 /* No need to distinguish vex_encoding_evex and vex_encoding_evex512. */
11301 if (i
.vec_encoding
== vex_encoding_evex512
)
11302 i
.vec_encoding
= vex_encoding_evex
;
11304 /* Are we to emit ModR/M encoding? */
11307 || i
.reg_operands
> (i
.vec_encoding
!= vex_encoding_default
)
11308 || i
.tm
.extension_opcode
!= None
))
11309 i
.tm
.opcode_modifier
.modrm
= 1;
11311 if (!i
.tm
.opcode_modifier
.modrm
11313 > i
.short_form
+ 0U + (i
.vec_encoding
!= vex_encoding_default
)
11314 || i
.mem_operands
))
11316 as_bad (_("too many register/memory operands"));
11320 /* Enforce certain constraints on operands. */
11321 switch (i
.reg_operands
+ i
.mem_operands
11322 + (i
.tm
.extension_opcode
!= None
))
11327 as_bad (_("too few register/memory operands"));
11330 /* Fall through. */
11332 if (i
.tm
.opcode_modifier
.modrm
)
11334 as_bad (_("too few register/memory operands"));
11344 && (i
.op
[0].imms
->X_op
!= O_constant
11345 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
11347 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
11350 /* Fall through. */
11352 if (i
.vec_encoding
!= vex_encoding_default
)
11354 i
.tm
.opcode_modifier
.vexvvvv
= 1;
11357 /* Fall through. */
11359 as_bad (_("too many register/memory operands"));
11363 /* Bring operands into canonical order (imm, mem, reg). */
11368 for (j
= 1; j
< i
.operands
; ++j
)
11370 if ((!operand_type_check (i
.types
[j
- 1], imm
)
11371 && operand_type_check (i
.types
[j
], imm
))
11372 || (i
.types
[j
- 1].bitfield
.class != ClassNone
11373 && i
.types
[j
].bitfield
.class == ClassNone
))
11375 swap_2_operands (j
- 1, j
);
11382 /* For Intel syntax swap the order of register operands. */
11384 switch (i
.reg_operands
)
11391 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
11392 /* Fall through. */
11395 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
11402 /* Enforce constraints when using VSIB. */
11404 && (i
.index_reg
->reg_type
.bitfield
.xmmword
11405 || i
.index_reg
->reg_type
.bitfield
.ymmword
11406 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
11408 if (i
.vec_encoding
== vex_encoding_default
)
11410 as_bad (_("VSIB unavailable with legacy encoding"));
11414 if (i
.vec_encoding
== vex_encoding_evex
11415 && i
.reg_operands
> 1)
11417 /* We could allow two register operands, encoding the 2nd one in
11418 an 8-bit immediate like for 4-register-operand insns, but that
11419 would require ugly fiddling with process_operands() and/or
11420 build_modrm_byte(). */
11421 as_bad (_("too many register operands with VSIB"));
11425 i
.tm
.opcode_modifier
.sib
= 1;
11428 /* Establish operand size encoding. */
11429 operand_type_set (&combined
, 0);
11431 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
11433 i
.types
[j
].bitfield
.instance
= InstanceNone
;
11435 if (operand_type_check (i
.types
[j
], disp
))
11437 i
.types
[j
].bitfield
.baseindex
= 1;
11438 disp_exp
= i
.op
[j
].disps
;
11441 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
11443 unsigned int n
= i
.memshift
;
11445 if (i
.types
[j
].bitfield
.byte
)
11447 else if (i
.types
[j
].bitfield
.word
)
11449 else if (i
.types
[j
].bitfield
.dword
)
11451 else if (i
.types
[j
].bitfield
.qword
)
11453 else if (i
.types
[j
].bitfield
.xmmword
)
11455 else if (i
.types
[j
].bitfield
.ymmword
)
11457 else if (i
.types
[j
].bitfield
.zmmword
)
11460 if (i
.memshift
< 32 && n
!= i
.memshift
)
11461 as_warn ("conflicting memory operand size specifiers");
11465 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11466 && j
== i
.broadcast
.operand
)
11469 combined
= operand_type_or (combined
, i
.types
[j
]);
11470 combined
.bitfield
.class = ClassNone
;
11473 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
11474 << (i
.memshift
< 32 ? i
.memshift
: 0))
11476 case 64: combined
.bitfield
.zmmword
= 1; break;
11477 case 32: combined
.bitfield
.ymmword
= 1; break;
11478 case 16: combined
.bitfield
.xmmword
= 1; break;
11479 case 8: combined
.bitfield
.qword
= 1; break;
11480 case 4: combined
.bitfield
.dword
= 1; break;
11483 if (i
.vec_encoding
== vex_encoding_default
)
11485 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
11487 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
11488 : combined
.bitfield
.word
)
11489 && !add_prefix (DATA_PREFIX_OPCODE
))
11492 else if (!i
.tm
.opcode_modifier
.vexw
)
11494 if (flag_code
== CODE_64BIT
)
11496 if (combined
.bitfield
.qword
)
11497 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11498 else if (combined
.bitfield
.dword
)
11499 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11502 if (!i
.tm
.opcode_modifier
.vexw
)
11503 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11508 if (!i
.tm
.opcode_modifier
.vex
)
11510 if (combined
.bitfield
.ymmword
)
11511 i
.tm
.opcode_modifier
.vex
= VEX256
;
11512 else if (combined
.bitfield
.xmmword
)
11513 i
.tm
.opcode_modifier
.vex
= VEX128
;
11518 if (!i
.tm
.opcode_modifier
.evex
)
11520 /* Do _not_ consider AVX512VL here. */
11521 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
11522 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11523 else if (combined
.bitfield
.ymmword
)
11524 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11525 else if (combined
.bitfield
.xmmword
)
11526 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11529 if (i
.memshift
>= 32)
11531 unsigned int n
= 0;
11533 switch (i
.tm
.opcode_modifier
.evex
)
11535 case EVEX512
: n
= 64; break;
11536 case EVEX256
: n
= 32; break;
11537 case EVEX128
: n
= 16; break;
11540 if (i
.broadcast
.type
)
11541 n
/= i
.broadcast
.type
;
11544 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11546 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
11547 && disp_exp
->X_add_number
!= 0
11548 && i
.disp_encoding
!= disp_encoding_32bit
)
11550 if (!quiet_warnings
)
11551 as_warn ("cannot determine memory operand size");
11552 i
.disp_encoding
= disp_encoding_32bit
;
11557 if (i
.memshift
>= 32)
11560 i
.vec_encoding
= vex_encoding_error
;
11562 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
11565 /* Establish size for immediate operands. */
11566 for (j
= 0; j
< i
.imm_operands
; ++j
)
11568 expressionS
*expP
= i
.op
[j
].imms
;
11570 gas_assert (operand_type_check (i
.types
[j
], imm
));
11571 operand_type_set (&i
.types
[j
], 0);
11573 if (i
.imm_bits
[j
] > 32)
11574 i
.types
[j
].bitfield
.imm64
= 1;
11575 else if (i
.imm_bits
[j
] > 16)
11577 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
11578 i
.types
[j
].bitfield
.imm32s
= 1;
11580 i
.types
[j
].bitfield
.imm32
= 1;
11582 else if (i
.imm_bits
[j
] > 8)
11583 i
.types
[j
].bitfield
.imm16
= 1;
11584 else if (i
.imm_bits
[j
] > 0)
11586 if (i
.flags
[j
] & Operand_Signed
)
11587 i
.types
[j
].bitfield
.imm8s
= 1;
11589 i
.types
[j
].bitfield
.imm8
= 1;
11591 else if (expP
->X_op
== O_constant
)
11593 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
11594 i
.types
[j
].bitfield
.imm1
= 0;
11595 /* Oddly enough imm_size() checks imm64 first, so the bit needs
11596 zapping since smallest_imm_type() sets it unconditionally. */
11597 if (flag_code
!= CODE_64BIT
)
11599 i
.types
[j
].bitfield
.imm64
= 0;
11600 i
.types
[j
].bitfield
.imm32s
= 0;
11601 i
.types
[j
].bitfield
.imm32
= 1;
11603 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
11604 i
.types
[j
].bitfield
.imm64
= 0;
11607 /* Non-constant expressions are sized heuristically. */
11610 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
11611 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
11612 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
11616 for (j
= 0; j
< i
.operands
; ++j
)
11617 i
.tm
.operand_types
[j
] = i
.types
[j
];
11619 process_operands ();
11622 /* Don't set opcode until after processing operands, to avoid any
11623 potential special casing there. */
11624 i
.tm
.base_opcode
|= val
;
11626 if (i
.vec_encoding
== vex_encoding_error
11627 || (i
.vec_encoding
!= vex_encoding_evex
11628 ? i
.broadcast
.type
|| i
.broadcast
.bytes
11629 || i
.rounding
.type
!= rc_none
11631 : (i
.mem_operands
&& i
.rounding
.type
!= rc_none
)
11632 || ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11633 && !(i
.flags
[i
.broadcast
.operand
] & Operand_Mem
))))
11635 as_bad (_("conflicting .insn operands"));
11641 if (!i
.tm
.opcode_modifier
.vex
)
11642 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11644 build_vex_prefix (NULL
);
11645 i
.rex
&= REX_OPCODE
;
11649 if (!i
.tm
.opcode_modifier
.evex
)
11650 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11652 build_evex_prefix ();
11653 i
.rex
&= REX_OPCODE
;
11655 else if (i
.rex
!= 0)
11656 add_prefix (REX_OPCODE
| i
.rex
);
11661 *saved_ilp
= saved_char
;
11662 input_line_pointer
= line
;
11664 demand_empty_rest_of_line ();
11666 /* Make sure dot_insn() won't yield "true" anymore. */
11672 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
11679 if (exp
.X_op
== O_symbol
)
11680 exp
.X_op
= O_secrel
;
11682 emit_expr (&exp
, 4);
11684 while (*input_line_pointer
++ == ',');
11686 input_line_pointer
--;
11687 demand_empty_rest_of_line ();
11691 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
11698 if (exp
.X_op
== O_symbol
)
11699 exp
.X_op
= O_secidx
;
11701 emit_expr (&exp
, 2);
11703 while (*input_line_pointer
++ == ',');
11705 input_line_pointer
--;
11706 demand_empty_rest_of_line ();
11710 /* Handle Rounding Control / SAE specifiers. */
11713 RC_SAE_specifier (const char *pstr
)
11717 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11719 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11721 if (i
.rounding
.type
!= rc_none
)
11723 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
11727 if (i
.vec_encoding
== vex_encoding_default
)
11728 i
.vec_encoding
= vex_encoding_evex512
;
11729 else if (i
.vec_encoding
!= vex_encoding_evex
11730 && i
.vec_encoding
!= vex_encoding_evex512
)
11733 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11735 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
11742 /* Handle Vector operations. */
11745 check_VecOperations (char *op_string
)
11747 const reg_entry
*mask
;
11754 if (*op_string
== '{')
11758 /* Check broadcasts. */
11759 if (startswith (op_string
, "1to"))
11761 unsigned int bcst_type
;
11763 if (i
.broadcast
.type
)
11764 goto duplicated_vec_op
;
11767 if (*op_string
== '8')
11769 else if (*op_string
== '4')
11771 else if (*op_string
== '2')
11773 else if (*op_string
== '1'
11774 && *(op_string
+1) == '6')
11779 else if (*op_string
== '3'
11780 && *(op_string
+1) == '2')
11787 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11792 if (i
.vec_encoding
== vex_encoding_default
)
11793 i
.vec_encoding
= vex_encoding_evex
;
11794 else if (i
.vec_encoding
!= vex_encoding_evex
11795 && i
.vec_encoding
!= vex_encoding_evex512
)
11796 goto unknown_vec_op
;
11798 i
.broadcast
.type
= bcst_type
;
11799 i
.broadcast
.operand
= this_operand
;
11801 /* For .insn a data size specifier may be appended. */
11802 if (dot_insn () && *op_string
== ':')
11803 goto dot_insn_modifier
;
11805 /* Check .insn special cases. */
11806 else if (dot_insn () && *op_string
== ':')
11809 switch (op_string
[1])
11814 if (i
.memshift
< 32)
11815 goto duplicated_vec_op
;
11817 n
= strtoul (op_string
+ 2, &end_op
, 0);
11819 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11821 if (i
.memshift
< 32 && n
== 1)
11822 op_string
= end_op
;
11825 case 's': case 'u':
11826 /* This isn't really a "vector" operation, but a sign/size
11827 specifier for immediate operands of .insn. Note that AT&T
11828 syntax handles the same in i386_immediate(). */
11832 if (i
.imm_bits
[this_operand
])
11833 goto duplicated_vec_op
;
11835 n
= strtoul (op_string
+ 2, &end_op
, 0);
11836 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11838 i
.imm_bits
[this_operand
] = n
;
11839 if (op_string
[1] == 's')
11840 i
.flags
[this_operand
] |= Operand_Signed
;
11841 op_string
= end_op
;
11846 /* Check masking operation. */
11847 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11849 if (mask
== &bad_reg
)
11852 /* k0 can't be used for write mask. */
11853 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11855 as_bad (_("`%s%s' can't be used for write mask"),
11856 register_prefix
, mask
->reg_name
);
11863 i
.mask
.operand
= this_operand
;
11865 else if (i
.mask
.reg
->reg_num
)
11866 goto duplicated_vec_op
;
11871 /* Only "{z}" is allowed here. No need to check
11872 zeroing mask explicitly. */
11873 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11875 as_bad (_("invalid write mask `%s'"), saved
);
11880 op_string
= end_op
;
11882 /* Check zeroing-flag for masking operation. */
11883 else if (*op_string
== 'z')
11887 i
.mask
.reg
= reg_k0
;
11888 i
.mask
.zeroing
= 1;
11889 i
.mask
.operand
= this_operand
;
11893 if (i
.mask
.zeroing
)
11896 as_bad (_("duplicated `%s'"), saved
);
11900 i
.mask
.zeroing
= 1;
11902 /* Only "{%k}" is allowed here. No need to check mask
11903 register explicitly. */
11904 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11906 as_bad (_("invalid zeroing-masking `%s'"),
11914 else if (intel_syntax
11915 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11916 i
.rounding
.modifier
= true;
11918 goto unknown_vec_op
;
11920 if (*op_string
!= '}')
11922 as_bad (_("missing `}' in `%s'"), saved
);
11927 /* Strip whitespace since the addition of pseudo prefixes
11928 changed how the scrubber treats '{'. */
11929 if (is_space_char (*op_string
))
11935 /* We don't know this one. */
11936 as_bad (_("unknown vector operation: `%s'"), saved
);
11940 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11942 as_bad (_("zeroing-masking only allowed with write mask"));
11950 i386_immediate (char *imm_start
)
11952 char *save_input_line_pointer
;
11953 char *gotfree_input_line
;
11956 i386_operand_type types
;
11958 operand_type_set (&types
, ~0);
11960 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
11962 as_bad (_("at most %d immediate operands are allowed"),
11963 MAX_IMMEDIATE_OPERANDS
);
11967 exp
= &im_expressions
[i
.imm_operands
++];
11968 i
.op
[this_operand
].imms
= exp
;
11970 if (is_space_char (*imm_start
))
11973 save_input_line_pointer
= input_line_pointer
;
11974 input_line_pointer
= imm_start
;
11976 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11977 if (gotfree_input_line
)
11978 input_line_pointer
= gotfree_input_line
;
11980 expr_mode
= expr_operator_none
;
11981 exp_seg
= expression (exp
);
11983 /* For .insn immediates there may be a size specifier. */
11984 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
11985 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
11988 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
11990 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11992 i
.imm_bits
[this_operand
] = n
;
11993 if (input_line_pointer
[2] == 's')
11994 i
.flags
[this_operand
] |= Operand_Signed
;
11995 input_line_pointer
= e
+ 1;
11999 SKIP_WHITESPACE ();
12000 if (*input_line_pointer
)
12001 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12003 input_line_pointer
= save_input_line_pointer
;
12004 if (gotfree_input_line
)
12006 free (gotfree_input_line
);
12008 if (exp
->X_op
== O_constant
)
12009 exp
->X_op
= O_illegal
;
12012 if (exp_seg
== reg_section
)
12014 as_bad (_("illegal immediate register operand %s"), imm_start
);
12018 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
12022 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12023 i386_operand_type types
, const char *imm_start
)
12025 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
12028 as_bad (_("missing or invalid immediate expression `%s'"),
12032 else if (exp
->X_op
== O_constant
)
12034 /* Size it properly later. */
12035 i
.types
[this_operand
].bitfield
.imm64
= 1;
12037 /* If not 64bit, sign/zero extend val, to account for wraparound
12039 if (expr_mode
== expr_operator_present
12040 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12041 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12043 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12044 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12045 && exp_seg
!= absolute_section
12046 && exp_seg
!= text_section
12047 && exp_seg
!= data_section
12048 && exp_seg
!= bss_section
12049 && exp_seg
!= undefined_section
12050 && !bfd_is_com_section (exp_seg
))
12052 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12058 /* This is an address. The size of the address will be
12059 determined later, depending on destination register,
12060 suffix, or the default for the section. */
12061 i
.types
[this_operand
].bitfield
.imm8
= 1;
12062 i
.types
[this_operand
].bitfield
.imm16
= 1;
12063 i
.types
[this_operand
].bitfield
.imm32
= 1;
12064 i
.types
[this_operand
].bitfield
.imm32s
= 1;
12065 i
.types
[this_operand
].bitfield
.imm64
= 1;
12066 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
12074 i386_scale (char *scale
)
12077 char *save
= input_line_pointer
;
12079 input_line_pointer
= scale
;
12080 val
= get_absolute_expression ();
12085 i
.log2_scale_factor
= 0;
12088 i
.log2_scale_factor
= 1;
12091 i
.log2_scale_factor
= 2;
12094 i
.log2_scale_factor
= 3;
12098 char sep
= *input_line_pointer
;
12100 *input_line_pointer
= '\0';
12101 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
12103 *input_line_pointer
= sep
;
12104 input_line_pointer
= save
;
12108 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
12110 as_warn (_("scale factor of %d without an index register"),
12111 1 << i
.log2_scale_factor
);
12112 i
.log2_scale_factor
= 0;
12114 scale
= input_line_pointer
;
12115 input_line_pointer
= save
;
12120 i386_displacement (char *disp_start
, char *disp_end
)
12124 char *save_input_line_pointer
;
12125 char *gotfree_input_line
;
12127 i386_operand_type bigdisp
, types
= anydisp
;
12130 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
12132 as_bad (_("at most %d displacement operands are allowed"),
12133 MAX_MEMORY_OPERANDS
);
12137 operand_type_set (&bigdisp
, 0);
12139 || i
.types
[this_operand
].bitfield
.baseindex
12140 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
12141 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
12143 i386_addressing_mode ();
12144 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
12145 if (flag_code
== CODE_64BIT
)
12147 bigdisp
.bitfield
.disp32
= 1;
12149 bigdisp
.bitfield
.disp64
= 1;
12151 else if ((flag_code
== CODE_16BIT
) ^ override
)
12152 bigdisp
.bitfield
.disp16
= 1;
12154 bigdisp
.bitfield
.disp32
= 1;
12158 /* For PC-relative branches, the width of the displacement may be
12159 dependent upon data size, but is never dependent upon address size.
12160 Also make sure to not unintentionally match against a non-PC-relative
12161 branch template. */
12162 static templates aux_templates
;
12163 const insn_template
*t
= current_templates
->start
;
12164 bool has_intel64
= false;
12166 aux_templates
.start
= t
;
12167 while (++t
< current_templates
->end
)
12169 if (t
->opcode_modifier
.jump
12170 != current_templates
->start
->opcode_modifier
.jump
)
12172 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
12173 has_intel64
= true;
12175 if (t
< current_templates
->end
)
12177 aux_templates
.end
= t
;
12178 current_templates
= &aux_templates
;
12181 override
= (i
.prefix
[DATA_PREFIX
] != 0);
12182 if (flag_code
== CODE_64BIT
)
12184 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
12185 && (!intel64
|| !has_intel64
))
12186 bigdisp
.bitfield
.disp16
= 1;
12188 bigdisp
.bitfield
.disp32
= 1;
12193 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
12195 : LONG_MNEM_SUFFIX
));
12196 bigdisp
.bitfield
.disp32
= 1;
12197 if ((flag_code
== CODE_16BIT
) ^ override
)
12199 bigdisp
.bitfield
.disp32
= 0;
12200 bigdisp
.bitfield
.disp16
= 1;
12204 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12207 exp
= &disp_expressions
[i
.disp_operands
];
12208 i
.op
[this_operand
].disps
= exp
;
12210 save_input_line_pointer
= input_line_pointer
;
12211 input_line_pointer
= disp_start
;
12212 END_STRING_AND_SAVE (disp_end
);
12214 #ifndef GCC_ASM_O_HACK
12215 #define GCC_ASM_O_HACK 0
12218 END_STRING_AND_SAVE (disp_end
+ 1);
12219 if (i
.types
[this_operand
].bitfield
.baseIndex
12220 && displacement_string_end
[-1] == '+')
12222 /* This hack is to avoid a warning when using the "o"
12223 constraint within gcc asm statements.
12226 #define _set_tssldt_desc(n,addr,limit,type) \
12227 __asm__ __volatile__ ( \
12228 "movw %w2,%0\n\t" \
12229 "movw %w1,2+%0\n\t" \
12230 "rorl $16,%1\n\t" \
12231 "movb %b1,4+%0\n\t" \
12232 "movb %4,5+%0\n\t" \
12233 "movb $0,6+%0\n\t" \
12234 "movb %h1,7+%0\n\t" \
12236 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
12238 This works great except that the output assembler ends
12239 up looking a bit weird if it turns out that there is
12240 no offset. You end up producing code that looks like:
12253 So here we provide the missing zero. */
12255 *displacement_string_end
= '0';
12258 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12259 if (gotfree_input_line
)
12260 input_line_pointer
= gotfree_input_line
;
12262 expr_mode
= expr_operator_none
;
12263 exp_seg
= expression (exp
);
12265 SKIP_WHITESPACE ();
12266 if (*input_line_pointer
)
12267 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12269 RESTORE_END_STRING (disp_end
+ 1);
12271 input_line_pointer
= save_input_line_pointer
;
12272 if (gotfree_input_line
)
12274 free (gotfree_input_line
);
12276 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
12277 exp
->X_op
= O_illegal
;
12280 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
12282 RESTORE_END_STRING (disp_end
);
12288 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12289 i386_operand_type types
, const char *disp_start
)
12293 /* We do this to make sure that the section symbol is in
12294 the symbol table. We will ultimately change the relocation
12295 to be relative to the beginning of the section. */
12296 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
12297 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
12298 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12300 if (exp
->X_op
!= O_symbol
)
12303 if (S_IS_LOCAL (exp
->X_add_symbol
)
12304 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
12305 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
12306 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
12307 exp
->X_op
= O_subtract
;
12308 exp
->X_op_symbol
= GOT_symbol
;
12309 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
12310 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
12311 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12312 i
.reloc
[this_operand
] = BFD_RELOC_64
;
12314 i
.reloc
[this_operand
] = BFD_RELOC_32
;
12317 else if (exp
->X_op
== O_absent
12318 || exp
->X_op
== O_illegal
12319 || exp
->X_op
== O_big
)
12322 as_bad (_("missing or invalid displacement expression `%s'"),
12327 else if (exp
->X_op
== O_constant
)
12329 /* Sizing gets taken care of by optimize_disp().
12331 If not 64bit, sign/zero extend val, to account for wraparound
12333 if (expr_mode
== expr_operator_present
12334 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12335 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12338 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12339 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12340 && exp_seg
!= absolute_section
12341 && exp_seg
!= text_section
12342 && exp_seg
!= data_section
12343 && exp_seg
!= bss_section
12344 && exp_seg
!= undefined_section
12345 && !bfd_is_com_section (exp_seg
))
12347 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12352 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
12353 i
.types
[this_operand
].bitfield
.disp8
= 1;
12355 /* Check if this is a displacement only operand. */
12356 if (!i
.types
[this_operand
].bitfield
.baseindex
)
12357 i
.types
[this_operand
] =
12358 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
12359 operand_type_and (i
.types
[this_operand
], types
));
12364 /* Return the active addressing mode, taking address override and
12365 registers forming the address into consideration. Update the
12366 address override prefix if necessary. */
12368 static enum flag_code
12369 i386_addressing_mode (void)
12371 enum flag_code addr_mode
;
12373 if (i
.prefix
[ADDR_PREFIX
])
12374 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
12375 else if (flag_code
== CODE_16BIT
12376 && is_cpu (current_templates
->start
, CpuMPX
)
12377 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
12378 from md_assemble() by "is not a valid base/index expression"
12379 when there is a base and/or index. */
12380 && !i
.types
[this_operand
].bitfield
.baseindex
)
12382 /* MPX insn memory operands with neither base nor index must be forced
12383 to use 32-bit addressing in 16-bit mode. */
12384 addr_mode
= CODE_32BIT
;
12385 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12387 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
12388 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
12392 addr_mode
= flag_code
;
12394 #if INFER_ADDR_PREFIX
12395 if (i
.mem_operands
== 0)
12397 /* Infer address prefix from the first memory operand. */
12398 const reg_entry
*addr_reg
= i
.base_reg
;
12400 if (addr_reg
== NULL
)
12401 addr_reg
= i
.index_reg
;
12405 if (addr_reg
->reg_type
.bitfield
.dword
)
12406 addr_mode
= CODE_32BIT
;
12407 else if (flag_code
!= CODE_64BIT
12408 && addr_reg
->reg_type
.bitfield
.word
)
12409 addr_mode
= CODE_16BIT
;
12411 if (addr_mode
!= flag_code
)
12413 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12415 /* Change the size of any displacement too. At most one
12416 of Disp16 or Disp32 is set.
12417 FIXME. There doesn't seem to be any real need for
12418 separate Disp16 and Disp32 flags. The same goes for
12419 Imm16 and Imm32. Removing them would probably clean
12420 up the code quite a lot. */
12421 if (flag_code
!= CODE_64BIT
12422 && (i
.types
[this_operand
].bitfield
.disp16
12423 || i
.types
[this_operand
].bitfield
.disp32
))
12425 static const i386_operand_type disp16_32
= {
12426 .bitfield
= { .disp16
= 1, .disp32
= 1 }
12429 i
.types
[this_operand
]
12430 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
12441 /* Make sure the memory operand we've been dealt is valid.
12442 Return 1 on success, 0 on a failure. */
12445 i386_index_check (const char *operand_string
)
12447 const char *kind
= "base/index";
12448 enum flag_code addr_mode
= i386_addressing_mode ();
12449 const insn_template
*t
= current_templates
->end
- 1;
12451 if (t
->opcode_modifier
.isstring
)
12453 /* Memory operands of string insns are special in that they only allow
12454 a single register (rDI, rSI, or rBX) as their memory address. */
12455 const reg_entry
*expected_reg
;
12456 static const char di_si
[][2][4] =
12462 static const char bx
[][4] = { "ebx", "bx", "rbx" };
12464 kind
= "string address";
12466 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
12468 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
12471 if (!t
->operand_types
[0].bitfield
.baseindex
12472 || ((!i
.mem_operands
!= !intel_syntax
)
12473 && t
->operand_types
[1].bitfield
.baseindex
))
12476 = (const reg_entry
*) str_hash_find (reg_hash
,
12477 di_si
[addr_mode
][op
== es_op
]);
12481 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
12483 if (i
.base_reg
!= expected_reg
12485 || operand_type_check (i
.types
[this_operand
], disp
))
12487 /* The second memory operand must have the same size as
12491 && !((addr_mode
== CODE_64BIT
12492 && i
.base_reg
->reg_type
.bitfield
.qword
)
12493 || (addr_mode
== CODE_32BIT
12494 ? i
.base_reg
->reg_type
.bitfield
.dword
12495 : i
.base_reg
->reg_type
.bitfield
.word
)))
12498 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
12500 intel_syntax
? '[' : '(',
12502 expected_reg
->reg_name
,
12503 intel_syntax
? ']' : ')');
12510 as_bad (_("`%s' is not a valid %s expression"),
12511 operand_string
, kind
);
12516 t
= current_templates
->start
;
12518 if (addr_mode
!= CODE_16BIT
)
12520 /* 32-bit/64-bit checks. */
12521 if (i
.disp_encoding
== disp_encoding_16bit
)
12524 as_bad (_("invalid `%s' prefix"),
12525 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
12530 && ((addr_mode
== CODE_64BIT
12531 ? !i
.base_reg
->reg_type
.bitfield
.qword
12532 : !i
.base_reg
->reg_type
.bitfield
.dword
)
12533 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
12534 || i
.base_reg
->reg_num
== RegIZ
))
12536 && !i
.index_reg
->reg_type
.bitfield
.xmmword
12537 && !i
.index_reg
->reg_type
.bitfield
.ymmword
12538 && !i
.index_reg
->reg_type
.bitfield
.zmmword
12539 && ((addr_mode
== CODE_64BIT
12540 ? !i
.index_reg
->reg_type
.bitfield
.qword
12541 : !i
.index_reg
->reg_type
.bitfield
.dword
)
12542 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
12545 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
12546 if (t
->mnem_off
== MN_bndmk
12547 || t
->mnem_off
== MN_bndldx
12548 || t
->mnem_off
== MN_bndstx
12549 || t
->opcode_modifier
.sib
== SIBMEM
)
12551 /* They cannot use RIP-relative addressing. */
12552 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12554 as_bad (_("`%s' cannot be used here"), operand_string
);
12558 /* bndldx and bndstx ignore their scale factor. */
12559 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
12560 && i
.log2_scale_factor
)
12561 as_warn (_("register scaling is being ignored here"));
12566 /* 16-bit checks. */
12567 if (i
.disp_encoding
== disp_encoding_32bit
)
12571 && (!i
.base_reg
->reg_type
.bitfield
.word
12572 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
12574 && (!i
.index_reg
->reg_type
.bitfield
.word
12575 || !i
.index_reg
->reg_type
.bitfield
.baseindex
12577 && i
.base_reg
->reg_num
< 6
12578 && i
.index_reg
->reg_num
>= 6
12579 && i
.log2_scale_factor
== 0))))
12586 /* Handle vector immediates. */
12589 RC_SAE_immediate (const char *imm_start
)
12591 const char *pstr
= imm_start
;
12596 pstr
= RC_SAE_specifier (pstr
+ 1);
12600 if (*pstr
++ != '}')
12602 as_bad (_("Missing '}': '%s'"), imm_start
);
12605 /* RC/SAE immediate string should contain nothing more. */;
12608 as_bad (_("Junk after '}': '%s'"), imm_start
);
12612 /* Internally this doesn't count as an operand. */
12618 static INLINE
bool starts_memory_operand (char c
)
12621 || is_name_beginner (c
)
12622 || strchr ("([\"+-!~", c
);
12625 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
12629 i386_att_operand (char *operand_string
)
12631 const reg_entry
*r
;
12633 char *op_string
= operand_string
;
12635 if (is_space_char (*op_string
))
12638 /* We check for an absolute prefix (differentiating,
12639 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
12640 if (*op_string
== ABSOLUTE_PREFIX
12641 && current_templates
->start
->opcode_modifier
.jump
)
12644 if (is_space_char (*op_string
))
12646 i
.jumpabsolute
= true;
12649 /* Check if operand is a register. */
12650 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
12652 i386_operand_type temp
;
12657 /* Check for a segment override by searching for ':' after a
12658 segment register. */
12659 op_string
= end_op
;
12660 if (is_space_char (*op_string
))
12662 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
12664 i
.seg
[i
.mem_operands
] = r
;
12666 /* Skip the ':' and whitespace. */
12668 if (is_space_char (*op_string
))
12671 /* Handle case of %es:*foo. */
12672 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
12673 && current_templates
->start
->opcode_modifier
.jump
)
12676 if (is_space_char (*op_string
))
12678 i
.jumpabsolute
= true;
12681 if (!starts_memory_operand (*op_string
))
12683 as_bad (_("bad memory operand `%s'"), op_string
);
12686 goto do_memory_reference
;
12689 /* Handle vector operations. */
12690 if (*op_string
== '{')
12692 op_string
= check_VecOperations (op_string
);
12693 if (op_string
== NULL
)
12699 as_bad (_("junk `%s' after register"), op_string
);
12703 /* Reject pseudo registers for .insn. */
12704 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
12706 as_bad (_("`%s%s' cannot be used here"),
12707 register_prefix
, r
->reg_name
);
12711 temp
= r
->reg_type
;
12712 temp
.bitfield
.baseindex
= 0;
12713 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12715 i
.types
[this_operand
].bitfield
.unspecified
= 0;
12716 i
.op
[this_operand
].regs
= r
;
12719 /* A GPR may follow an RC or SAE immediate only if a (vector) register
12720 operand was also present earlier on. */
12721 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
12722 && i
.reg_operands
== 1)
12726 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
12727 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
12729 as_bad (_("`%s': misplaced `{%s}'"),
12730 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
12734 else if (*op_string
== REGISTER_PREFIX
)
12736 as_bad (_("bad register name `%s'"), op_string
);
12739 else if (*op_string
== IMMEDIATE_PREFIX
)
12742 if (i
.jumpabsolute
)
12744 as_bad (_("immediate operand illegal with absolute jump"));
12747 if (!i386_immediate (op_string
))
12749 if (i
.rounding
.type
!= rc_none
)
12751 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
12752 insn_name (current_templates
->start
));
12756 else if (RC_SAE_immediate (operand_string
))
12758 /* If it is a RC or SAE immediate, do the necessary placement check:
12759 Only another immediate or a GPR may precede it. */
12760 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
12761 || (i
.reg_operands
== 1
12762 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
12764 as_bad (_("`%s': misplaced `%s'"),
12765 insn_name (current_templates
->start
), operand_string
);
12769 else if (starts_memory_operand (*op_string
))
12771 /* This is a memory reference of some sort. */
12774 /* Start and end of displacement string expression (if found). */
12775 char *displacement_string_start
;
12776 char *displacement_string_end
;
12778 do_memory_reference
:
12779 /* Check for base index form. We detect the base index form by
12780 looking for an ')' at the end of the operand, searching
12781 for the '(' matching it, and finding a REGISTER_PREFIX or ','
12783 base_string
= op_string
+ strlen (op_string
);
12785 /* Handle vector operations. */
12787 if (is_space_char (*base_string
))
12790 if (*base_string
== '}')
12792 char *vop_start
= NULL
;
12794 while (base_string
-- > op_string
)
12796 if (*base_string
== '"')
12798 if (*base_string
!= '{')
12801 vop_start
= base_string
;
12804 if (is_space_char (*base_string
))
12807 if (*base_string
!= '}')
12815 as_bad (_("unbalanced figure braces"));
12819 if (check_VecOperations (vop_start
) == NULL
)
12823 /* If we only have a displacement, set-up for it to be parsed later. */
12824 displacement_string_start
= op_string
;
12825 displacement_string_end
= base_string
+ 1;
12827 if (*base_string
== ')')
12830 unsigned int parens_not_balanced
= 0;
12831 bool in_quotes
= false;
12833 /* We've already checked that the number of left & right ()'s are
12834 equal, and that there's a matching set of double quotes. */
12835 end_op
= base_string
;
12836 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
12838 if (*temp_string
== '\\' && temp_string
[1] == '"')
12840 else if (*temp_string
== '"')
12841 in_quotes
= !in_quotes
;
12842 else if (!in_quotes
)
12844 if (*temp_string
== '(' && !parens_not_balanced
++)
12845 base_string
= temp_string
;
12846 if (*temp_string
== ')')
12847 --parens_not_balanced
;
12851 temp_string
= base_string
;
12853 /* Skip past '(' and whitespace. */
12854 gas_assert (*base_string
== '(');
12856 if (is_space_char (*base_string
))
12859 if (*base_string
== ','
12860 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12863 displacement_string_end
= temp_string
;
12865 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12869 if (i
.base_reg
== &bad_reg
)
12871 base_string
= end_op
;
12872 if (is_space_char (*base_string
))
12876 /* There may be an index reg or scale factor here. */
12877 if (*base_string
== ',')
12880 if (is_space_char (*base_string
))
12883 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12886 if (i
.index_reg
== &bad_reg
)
12888 base_string
= end_op
;
12889 if (is_space_char (*base_string
))
12891 if (*base_string
== ',')
12894 if (is_space_char (*base_string
))
12897 else if (*base_string
!= ')')
12899 as_bad (_("expecting `,' or `)' "
12900 "after index register in `%s'"),
12905 else if (*base_string
== REGISTER_PREFIX
)
12907 end_op
= strchr (base_string
, ',');
12910 as_bad (_("bad register name `%s'"), base_string
);
12914 /* Check for scale factor. */
12915 if (*base_string
!= ')')
12917 char *end_scale
= i386_scale (base_string
);
12922 base_string
= end_scale
;
12923 if (is_space_char (*base_string
))
12925 if (*base_string
!= ')')
12927 as_bad (_("expecting `)' "
12928 "after scale factor in `%s'"),
12933 else if (!i
.index_reg
)
12935 as_bad (_("expecting index register or scale factor "
12936 "after `,'; got '%c'"),
12941 else if (*base_string
!= ')')
12943 as_bad (_("expecting `,' or `)' "
12944 "after base register in `%s'"),
12949 else if (*base_string
== REGISTER_PREFIX
)
12951 end_op
= strchr (base_string
, ',');
12954 as_bad (_("bad register name `%s'"), base_string
);
12959 /* If there's an expression beginning the operand, parse it,
12960 assuming displacement_string_start and
12961 displacement_string_end are meaningful. */
12962 if (displacement_string_start
!= displacement_string_end
)
12964 if (!i386_displacement (displacement_string_start
,
12965 displacement_string_end
))
12969 /* Special case for (%dx) while doing input/output op. */
12971 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
12972 && i
.base_reg
->reg_type
.bitfield
.word
12973 && i
.index_reg
== 0
12974 && i
.log2_scale_factor
== 0
12975 && i
.seg
[i
.mem_operands
] == 0
12976 && !operand_type_check (i
.types
[this_operand
], disp
))
12978 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
12979 i
.input_output_operand
= true;
12983 if (i386_index_check (operand_string
) == 0)
12985 i
.flags
[this_operand
] |= Operand_Mem
;
12990 /* It's not a memory operand; argh! */
12991 as_bad (_("invalid char %s beginning operand %d `%s'"),
12992 output_invalid (*op_string
),
12997 return 1; /* Normal return. */
13000 /* Calculate the maximum variable size (i.e., excluding fr_fix)
13001 that an rs_machine_dependent frag may reach. */
13004 i386_frag_max_var (fragS
*frag
)
13006 /* The only relaxable frags are for jumps.
13007 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
13008 gas_assert (frag
->fr_type
== rs_machine_dependent
);
13009 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
13012 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13014 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
13016 /* STT_GNU_IFUNC symbol must go through PLT. */
13017 if ((symbol_get_bfdsym (fr_symbol
)->flags
13018 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
13021 if (!S_IS_EXTERNAL (fr_symbol
))
13022 /* Symbol may be weak or local. */
13023 return !S_IS_WEAK (fr_symbol
);
13025 /* Global symbols with non-default visibility can't be preempted. */
13026 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
13029 if (fr_var
!= NO_RELOC
)
13030 switch ((enum bfd_reloc_code_real
) fr_var
)
13032 case BFD_RELOC_386_PLT32
:
13033 case BFD_RELOC_X86_64_PLT32
:
13034 /* Symbol with PLT relocation may be preempted. */
13040 /* Global symbols with default visibility in a shared library may be
13041 preempted by another definition. */
13046 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
13047 Note also work for Skylake and Cascadelake.
13048 ---------------------------------------------------------------------
13049 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
13050 | ------ | ----------- | ------- | -------- |
13052 | Jno | N | N | Y |
13053 | Jc/Jb | Y | N | Y |
13054 | Jae/Jnb | Y | N | Y |
13055 | Je/Jz | Y | Y | Y |
13056 | Jne/Jnz | Y | Y | Y |
13057 | Jna/Jbe | Y | N | Y |
13058 | Ja/Jnbe | Y | N | Y |
13060 | Jns | N | N | Y |
13061 | Jp/Jpe | N | N | Y |
13062 | Jnp/Jpo | N | N | Y |
13063 | Jl/Jnge | Y | Y | Y |
13064 | Jge/Jnl | Y | Y | Y |
13065 | Jle/Jng | Y | Y | Y |
13066 | Jg/Jnle | Y | Y | Y |
13067 --------------------------------------------------------------------- */
13069 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
13071 if (mf_cmp
== mf_cmp_alu_cmp
)
13072 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
13073 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
13074 if (mf_cmp
== mf_cmp_incdec
)
13075 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
13076 || mf_jcc
== mf_jcc_jle
);
13077 if (mf_cmp
== mf_cmp_test_and
)
13082 /* Return the next non-empty frag. */
13085 i386_next_non_empty_frag (fragS
*fragP
)
13087 /* There may be a frag with a ".fill 0" when there is no room in
13088 the current frag for frag_grow in output_insn. */
13089 for (fragP
= fragP
->fr_next
;
13091 && fragP
->fr_type
== rs_fill
13092 && fragP
->fr_fix
== 0);
13093 fragP
= fragP
->fr_next
)
13098 /* Return the next jcc frag after BRANCH_PADDING. */
13101 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
13103 fragS
*branch_fragP
;
13107 if (pad_fragP
->fr_type
== rs_machine_dependent
13108 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
13109 == BRANCH_PADDING
))
13111 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
13112 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
13114 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
13115 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
13116 pad_fragP
->tc_frag_data
.mf_type
))
13117 return branch_fragP
;
13123 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
13126 i386_classify_machine_dependent_frag (fragS
*fragP
)
13130 fragS
*branch_fragP
;
13132 unsigned int max_prefix_length
;
13134 if (fragP
->tc_frag_data
.classified
)
13137 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
13138 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
13139 for (next_fragP
= fragP
;
13140 next_fragP
!= NULL
;
13141 next_fragP
= next_fragP
->fr_next
)
13143 next_fragP
->tc_frag_data
.classified
= 1;
13144 if (next_fragP
->fr_type
== rs_machine_dependent
)
13145 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
13147 case BRANCH_PADDING
:
13148 /* The BRANCH_PADDING frag must be followed by a branch
13150 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
13151 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13153 case FUSED_JCC_PADDING
:
13154 /* Check if this is a fused jcc:
13156 CMP like instruction
13160 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
13161 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
13162 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
13165 /* The BRANCH_PADDING frag is merged with the
13166 FUSED_JCC_PADDING frag. */
13167 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13168 /* CMP like instruction size. */
13169 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
13170 frag_wane (pad_fragP
);
13171 /* Skip to branch_fragP. */
13172 next_fragP
= branch_fragP
;
13174 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
13176 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
13178 next_fragP
->fr_subtype
13179 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
13180 next_fragP
->tc_frag_data
.max_bytes
13181 = next_fragP
->tc_frag_data
.max_prefix_length
;
13182 /* This will be updated in the BRANCH_PREFIX scan. */
13183 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
13186 frag_wane (next_fragP
);
13191 /* Stop if there is no BRANCH_PREFIX. */
13192 if (!align_branch_prefix_size
)
13195 /* Scan for BRANCH_PREFIX. */
13196 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
13198 if (fragP
->fr_type
!= rs_machine_dependent
13199 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13203 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
13204 COND_JUMP_PREFIX. */
13205 max_prefix_length
= 0;
13206 for (next_fragP
= fragP
;
13207 next_fragP
!= NULL
;
13208 next_fragP
= next_fragP
->fr_next
)
13210 if (next_fragP
->fr_type
== rs_fill
)
13211 /* Skip rs_fill frags. */
13213 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
13214 /* Stop for all other frags. */
13217 /* rs_machine_dependent frags. */
13218 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13221 /* Count BRANCH_PREFIX frags. */
13222 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
13224 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
13225 frag_wane (next_fragP
);
13229 += next_fragP
->tc_frag_data
.max_bytes
;
13231 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13233 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13234 == FUSED_JCC_PADDING
))
13236 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
13237 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
13241 /* Stop for other rs_machine_dependent frags. */
13245 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
13247 /* Skip to the next frag. */
13248 fragP
= next_fragP
;
13252 /* Compute padding size for
13255 CMP like instruction
13257 COND_JUMP/UNCOND_JUMP
13262 COND_JUMP/UNCOND_JUMP
13266 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
13268 unsigned int offset
, size
, padding_size
;
13269 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
13271 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
13273 address
= fragP
->fr_address
;
13274 address
+= fragP
->fr_fix
;
13276 /* CMP like instrunction size. */
13277 size
= fragP
->tc_frag_data
.cmp_size
;
13279 /* The base size of the branch frag. */
13280 size
+= branch_fragP
->fr_fix
;
13282 /* Add opcode and displacement bytes for the rs_machine_dependent
13284 if (branch_fragP
->fr_type
== rs_machine_dependent
)
13285 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
13287 /* Check if branch is within boundary and doesn't end at the last
13289 offset
= address
& ((1U << align_branch_power
) - 1);
13290 if ((offset
+ size
) >= (1U << align_branch_power
))
13291 /* Padding needed to avoid crossing boundary. */
13292 padding_size
= (1U << align_branch_power
) - offset
;
13294 /* No padding needed. */
13297 /* The return value may be saved in tc_frag_data.length which is
13299 if (!fits_in_unsigned_byte (padding_size
))
13302 return padding_size
;
13305 /* i386_generic_table_relax_frag()
13307 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
13308 grow/shrink padding to align branch frags. Hand others to
13312 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
13314 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13315 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13317 long padding_size
= i386_branch_padding_size (fragP
, 0);
13318 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
13320 /* When the BRANCH_PREFIX frag is used, the computed address
13321 must match the actual address and there should be no padding. */
13322 if (fragP
->tc_frag_data
.padding_address
13323 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
13327 /* Update the padding size. */
13329 fragP
->tc_frag_data
.length
= padding_size
;
13333 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13335 fragS
*padding_fragP
, *next_fragP
;
13336 long padding_size
, left_size
, last_size
;
13338 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13339 if (!padding_fragP
)
13340 /* Use the padding set by the leading BRANCH_PREFIX frag. */
13341 return (fragP
->tc_frag_data
.length
13342 - fragP
->tc_frag_data
.last_length
);
13344 /* Compute the relative address of the padding frag in the very
13345 first time where the BRANCH_PREFIX frag sizes are zero. */
13346 if (!fragP
->tc_frag_data
.padding_address
)
13347 fragP
->tc_frag_data
.padding_address
13348 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
13350 /* First update the last length from the previous interation. */
13351 left_size
= fragP
->tc_frag_data
.prefix_length
;
13352 for (next_fragP
= fragP
;
13353 next_fragP
!= padding_fragP
;
13354 next_fragP
= next_fragP
->fr_next
)
13355 if (next_fragP
->fr_type
== rs_machine_dependent
13356 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13361 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13365 if (max
> left_size
)
13370 next_fragP
->tc_frag_data
.last_length
= size
;
13374 next_fragP
->tc_frag_data
.last_length
= 0;
13377 /* Check the padding size for the padding frag. */
13378 padding_size
= i386_branch_padding_size
13379 (padding_fragP
, (fragP
->fr_address
13380 + fragP
->tc_frag_data
.padding_address
));
13382 last_size
= fragP
->tc_frag_data
.prefix_length
;
13383 /* Check if there is change from the last interation. */
13384 if (padding_size
== last_size
)
13386 /* Update the expected address of the padding frag. */
13387 padding_fragP
->tc_frag_data
.padding_address
13388 = (fragP
->fr_address
+ padding_size
13389 + fragP
->tc_frag_data
.padding_address
);
13393 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
13395 /* No padding if there is no sufficient room. Clear the
13396 expected address of the padding frag. */
13397 padding_fragP
->tc_frag_data
.padding_address
= 0;
13401 /* Store the expected address of the padding frag. */
13402 padding_fragP
->tc_frag_data
.padding_address
13403 = (fragP
->fr_address
+ padding_size
13404 + fragP
->tc_frag_data
.padding_address
);
13406 fragP
->tc_frag_data
.prefix_length
= padding_size
;
13408 /* Update the length for the current interation. */
13409 left_size
= padding_size
;
13410 for (next_fragP
= fragP
;
13411 next_fragP
!= padding_fragP
;
13412 next_fragP
= next_fragP
->fr_next
)
13413 if (next_fragP
->fr_type
== rs_machine_dependent
13414 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13419 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13423 if (max
> left_size
)
13428 next_fragP
->tc_frag_data
.length
= size
;
13432 next_fragP
->tc_frag_data
.length
= 0;
13435 return (fragP
->tc_frag_data
.length
13436 - fragP
->tc_frag_data
.last_length
);
13438 return relax_frag (segment
, fragP
, stretch
);
13441 /* md_estimate_size_before_relax()
13443 Called just before relax() for rs_machine_dependent frags. The x86
13444 assembler uses these frags to handle variable size jump
13447 Any symbol that is now undefined will not become defined.
13448 Return the correct fr_subtype in the frag.
13449 Return the initial "guess for variable size of frag" to caller.
13450 The guess is actually the growth beyond the fixed part. Whatever
13451 we do to grow the fixed or variable part contributes to our
13455 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
13457 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13458 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
13459 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13461 i386_classify_machine_dependent_frag (fragP
);
13462 return fragP
->tc_frag_data
.length
;
13465 /* We've already got fragP->fr_subtype right; all we have to do is
13466 check for un-relaxable symbols. On an ELF system, we can't relax
13467 an externally visible symbol, because it may be overridden by a
13469 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
13470 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13472 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
13475 #if defined (OBJ_COFF) && defined (TE_PE)
13476 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
13477 && S_IS_WEAK (fragP
->fr_symbol
))
13481 /* Symbol is undefined in this segment, or we need to keep a
13482 reloc so that weak symbols can be overridden. */
13483 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
13484 enum bfd_reloc_code_real reloc_type
;
13485 unsigned char *opcode
;
13489 if (fragP
->fr_var
!= NO_RELOC
)
13490 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
13491 else if (size
== 2)
13492 reloc_type
= BFD_RELOC_16_PCREL
;
13493 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13494 else if (fragP
->tc_frag_data
.code64
&& fragP
->fr_offset
== 0
13495 && need_plt32_p (fragP
->fr_symbol
))
13496 reloc_type
= BFD_RELOC_X86_64_PLT32
;
13499 reloc_type
= BFD_RELOC_32_PCREL
;
13501 old_fr_fix
= fragP
->fr_fix
;
13502 opcode
= (unsigned char *) fragP
->fr_opcode
;
13504 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
13507 /* Make jmp (0xeb) a (d)word displacement jump. */
13509 fragP
->fr_fix
+= size
;
13510 fixP
= fix_new (fragP
, old_fr_fix
, size
,
13512 fragP
->fr_offset
, 1,
13518 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
13520 /* Negate the condition, and branch past an
13521 unconditional jump. */
13524 /* Insert an unconditional jump. */
13526 /* We added two extra opcode bytes, and have a two byte
13528 fragP
->fr_fix
+= 2 + 2;
13529 fix_new (fragP
, old_fr_fix
+ 2, 2,
13531 fragP
->fr_offset
, 1,
13535 /* Fall through. */
13538 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
13540 fragP
->fr_fix
+= 1;
13541 fixP
= fix_new (fragP
, old_fr_fix
, 1,
13543 fragP
->fr_offset
, 1,
13544 BFD_RELOC_8_PCREL
);
13545 fixP
->fx_signed
= 1;
13549 /* This changes the byte-displacement jump 0x7N
13550 to the (d)word-displacement jump 0x0f,0x8N. */
13551 opcode
[1] = opcode
[0] + 0x10;
13552 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13553 /* We've added an opcode byte. */
13554 fragP
->fr_fix
+= 1 + size
;
13555 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
13557 fragP
->fr_offset
, 1,
13562 BAD_CASE (fragP
->fr_subtype
);
13566 /* All jumps handled here are signed, but don't unconditionally use a
13567 signed limit check for 32 and 16 bit jumps as we want to allow wrap
13568 around at 4G (outside of 64-bit mode) and 64k. */
13569 if (size
== 4 && flag_code
== CODE_64BIT
)
13570 fixP
->fx_signed
= 1;
13573 return fragP
->fr_fix
- old_fr_fix
;
13576 /* Guess size depending on current relax state. Initially the relax
13577 state will correspond to a short jump and we return 1, because
13578 the variable part of the frag (the branch offset) is one byte
13579 long. However, we can relax a section more than once and in that
13580 case we must either set fr_subtype back to the unrelaxed state,
13581 or return the value for the appropriate branch. */
13582 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
13585 /* Called after relax() is finished.
13587 In: Address of frag.
13588 fr_type == rs_machine_dependent.
13589 fr_subtype is what the address relaxed to.
13591 Out: Any fixSs and constants are set up.
13592 Caller will turn frag into a ".space 0". */
13595 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
13598 unsigned char *opcode
;
13599 unsigned char *where_to_put_displacement
= NULL
;
13600 offsetT target_address
;
13601 offsetT opcode_address
;
13602 unsigned int extension
= 0;
13603 offsetT displacement_from_opcode_start
;
13605 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13606 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
13607 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13609 /* Generate nop padding. */
13610 unsigned int size
= fragP
->tc_frag_data
.length
;
13613 if (size
> fragP
->tc_frag_data
.max_bytes
)
13619 const char *branch
= "branch";
13620 const char *prefix
= "";
13621 fragS
*padding_fragP
;
13622 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13625 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13626 switch (fragP
->tc_frag_data
.default_prefix
)
13631 case CS_PREFIX_OPCODE
:
13634 case DS_PREFIX_OPCODE
:
13637 case ES_PREFIX_OPCODE
:
13640 case FS_PREFIX_OPCODE
:
13643 case GS_PREFIX_OPCODE
:
13646 case SS_PREFIX_OPCODE
:
13651 msg
= _("%s:%u: add %d%s at 0x%llx to align "
13652 "%s within %d-byte boundary\n");
13654 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
13655 "align %s within %d-byte boundary\n");
13659 padding_fragP
= fragP
;
13660 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
13661 "%s within %d-byte boundary\n");
13665 switch (padding_fragP
->tc_frag_data
.branch_type
)
13667 case align_branch_jcc
:
13670 case align_branch_fused
:
13671 branch
= "fused jcc";
13673 case align_branch_jmp
:
13676 case align_branch_call
:
13679 case align_branch_indirect
:
13680 branch
= "indiret branch";
13682 case align_branch_ret
:
13689 fprintf (stdout
, msg
,
13690 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
13691 (long long) fragP
->fr_address
, branch
,
13692 1 << align_branch_power
);
13694 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13695 memset (fragP
->fr_opcode
,
13696 fragP
->tc_frag_data
.default_prefix
, size
);
13698 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
13700 fragP
->fr_fix
+= size
;
13705 opcode
= (unsigned char *) fragP
->fr_opcode
;
13707 /* Address we want to reach in file space. */
13708 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
13710 /* Address opcode resides at in file space. */
13711 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
13713 /* Displacement from opcode start to fill into instruction. */
13714 displacement_from_opcode_start
= target_address
- opcode_address
;
13716 if ((fragP
->fr_subtype
& BIG
) == 0)
13718 /* Don't have to change opcode. */
13719 extension
= 1; /* 1 opcode + 1 displacement */
13720 where_to_put_displacement
= &opcode
[1];
13724 if (no_cond_jump_promotion
13725 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
13726 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
13727 _("long jump required"));
13729 switch (fragP
->fr_subtype
)
13731 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
13732 extension
= 4; /* 1 opcode + 4 displacement */
13734 where_to_put_displacement
= &opcode
[1];
13737 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
13738 extension
= 2; /* 1 opcode + 2 displacement */
13740 where_to_put_displacement
= &opcode
[1];
13743 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
13744 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
13745 extension
= 5; /* 2 opcode + 4 displacement */
13746 opcode
[1] = opcode
[0] + 0x10;
13747 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13748 where_to_put_displacement
= &opcode
[2];
13751 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
13752 extension
= 3; /* 2 opcode + 2 displacement */
13753 opcode
[1] = opcode
[0] + 0x10;
13754 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13755 where_to_put_displacement
= &opcode
[2];
13758 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
13763 where_to_put_displacement
= &opcode
[3];
13767 BAD_CASE (fragP
->fr_subtype
);
13772 /* If size if less then four we are sure that the operand fits,
13773 but if it's 4, then it could be that the displacement is larger
13775 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
13777 && ((addressT
) (displacement_from_opcode_start
- extension
13778 + ((addressT
) 1 << 31))
13779 > (((addressT
) 2 << 31) - 1)))
13781 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
13782 _("jump target out of range"));
13783 /* Make us emit 0. */
13784 displacement_from_opcode_start
= extension
;
13786 /* Now put displacement after opcode. */
13787 md_number_to_chars ((char *) where_to_put_displacement
,
13788 (valueT
) (displacement_from_opcode_start
- extension
),
13789 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
13790 fragP
->fr_fix
+= extension
;
13793 /* Apply a fixup (fixP) to segment data, once it has been determined
13794 by our caller that we have all the info we need to fix it up.
13796 Parameter valP is the pointer to the value of the bits.
13798 On the 386, immediates, displacements, and data pointers are all in
13799 the same (little-endian) format, so we don't need to care about which
13800 we are handling. */
13803 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13805 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
13806 valueT value
= *valP
;
13808 #if !defined (TE_Mach)
13809 if (fixP
->fx_pcrel
)
13811 switch (fixP
->fx_r_type
)
13817 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
13820 case BFD_RELOC_X86_64_32S
:
13821 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
13824 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
13827 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
13832 if (fixP
->fx_addsy
!= NULL
13833 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
13834 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
13835 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
13836 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
13837 && !use_rela_relocations
)
13839 /* This is a hack. There should be a better way to handle this.
13840 This covers for the fact that bfd_install_relocation will
13841 subtract the current location (for partial_inplace, PC relative
13842 relocations); see more below. */
13846 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
13849 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13851 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13854 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
13856 if ((sym_seg
== seg
13857 || (symbol_section_p (fixP
->fx_addsy
)
13858 && sym_seg
!= absolute_section
))
13859 && !generic_force_reloc (fixP
))
13861 /* Yes, we add the values in twice. This is because
13862 bfd_install_relocation subtracts them out again. I think
13863 bfd_install_relocation is broken, but I don't dare change
13865 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13869 #if defined (OBJ_COFF) && defined (TE_PE)
13870 /* For some reason, the PE format does not store a
13871 section address offset for a PC relative symbol. */
13872 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13873 || S_IS_WEAK (fixP
->fx_addsy
))
13874 value
+= md_pcrel_from (fixP
);
13877 #if defined (OBJ_COFF) && defined (TE_PE)
13878 if (fixP
->fx_addsy
!= NULL
13879 && S_IS_WEAK (fixP
->fx_addsy
)
13880 /* PR 16858: Do not modify weak function references. */
13881 && ! fixP
->fx_pcrel
)
13883 #if !defined (TE_PEP)
13884 /* For x86 PE weak function symbols are neither PC-relative
13885 nor do they set S_IS_FUNCTION. So the only reliable way
13886 to detect them is to check the flags of their containing
13888 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13889 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13893 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13897 /* Fix a few things - the dynamic linker expects certain values here,
13898 and we must not disappoint it. */
13899 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13900 if (IS_ELF
&& fixP
->fx_addsy
)
13901 switch (fixP
->fx_r_type
)
13903 case BFD_RELOC_386_PLT32
:
13904 case BFD_RELOC_X86_64_PLT32
:
13905 /* Make the jump instruction point to the address of the operand.
13906 At runtime we merely add the offset to the actual PLT entry.
13907 NB: Subtract the offset size only for jump instructions. */
13908 if (fixP
->fx_pcrel
)
13912 case BFD_RELOC_386_TLS_GD
:
13913 case BFD_RELOC_386_TLS_LDM
:
13914 case BFD_RELOC_386_TLS_IE_32
:
13915 case BFD_RELOC_386_TLS_IE
:
13916 case BFD_RELOC_386_TLS_GOTIE
:
13917 case BFD_RELOC_386_TLS_GOTDESC
:
13918 case BFD_RELOC_X86_64_TLSGD
:
13919 case BFD_RELOC_X86_64_TLSLD
:
13920 case BFD_RELOC_X86_64_GOTTPOFF
:
13921 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13922 value
= 0; /* Fully resolved at runtime. No addend. */
13924 case BFD_RELOC_386_TLS_LE
:
13925 case BFD_RELOC_386_TLS_LDO_32
:
13926 case BFD_RELOC_386_TLS_LE_32
:
13927 case BFD_RELOC_X86_64_DTPOFF32
:
13928 case BFD_RELOC_X86_64_DTPOFF64
:
13929 case BFD_RELOC_X86_64_TPOFF32
:
13930 case BFD_RELOC_X86_64_TPOFF64
:
13931 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13934 case BFD_RELOC_386_TLS_DESC_CALL
:
13935 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13936 value
= 0; /* Fully resolved at runtime. No addend. */
13937 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13941 case BFD_RELOC_VTABLE_INHERIT
:
13942 case BFD_RELOC_VTABLE_ENTRY
:
13949 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13951 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13953 value
= extend_to_32bit_address (value
);
13956 #endif /* !defined (TE_Mach) */
13958 /* Are we finished with this relocation now? */
13959 if (fixP
->fx_addsy
== NULL
)
13962 switch (fixP
->fx_r_type
)
13964 case BFD_RELOC_X86_64_32S
:
13965 fixP
->fx_signed
= 1;
13972 #if defined (OBJ_COFF) && defined (TE_PE)
13973 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
13976 /* Remember value for tc_gen_reloc. */
13977 fixP
->fx_addnumber
= value
;
13978 /* Clear out the frag for now. */
13982 else if (use_rela_relocations
)
13984 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
13985 fixP
->fx_no_overflow
= 1;
13986 /* Remember value for tc_gen_reloc. */
13987 fixP
->fx_addnumber
= value
;
13991 md_number_to_chars (p
, value
, fixP
->fx_size
);
13995 md_atof (int type
, char *litP
, int *sizeP
)
13997 /* This outputs the LITTLENUMs in REVERSE order;
13998 in accord with the bigendian 386. */
13999 return ieee_md_atof (type
, litP
, sizeP
, false);
14002 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
14005 output_invalid (int c
)
14008 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14011 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
14012 "(0x%x)", (unsigned char) c
);
14013 return output_invalid_buf
;
14016 /* Verify that @r can be used in the current context. */
14018 static bool check_register (const reg_entry
*r
)
14020 if (allow_pseudo_reg
)
14023 if (operand_type_all_zero (&r
->reg_type
))
14026 if ((r
->reg_type
.bitfield
.dword
14027 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
14028 || r
->reg_type
.bitfield
.class == RegCR
14029 || r
->reg_type
.bitfield
.class == RegDR
)
14030 && !cpu_arch_flags
.bitfield
.cpui386
)
14033 if (r
->reg_type
.bitfield
.class == RegTR
14034 && (flag_code
== CODE_64BIT
14035 || !cpu_arch_flags
.bitfield
.cpui386
14036 || cpu_arch_isa_flags
.bitfield
.cpui586
14037 || cpu_arch_isa_flags
.bitfield
.cpui686
))
14040 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
14043 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
14045 if (r
->reg_type
.bitfield
.zmmword
14046 || r
->reg_type
.bitfield
.class == RegMask
)
14049 if (!cpu_arch_flags
.bitfield
.cpuavx
)
14051 if (r
->reg_type
.bitfield
.ymmword
)
14054 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
14059 if (r
->reg_type
.bitfield
.zmmword
)
14061 if (vector_size
< VSZ512
)
14064 if (i
.vec_encoding
== vex_encoding_default
)
14065 i
.vec_encoding
= vex_encoding_evex512
;
14066 else if (i
.vec_encoding
!= vex_encoding_evex
14067 && i
.vec_encoding
!= vex_encoding_evex512
)
14068 i
.vec_encoding
= vex_encoding_error
;
14071 if (vector_size
< VSZ256
&& r
->reg_type
.bitfield
.ymmword
)
14074 if (r
->reg_type
.bitfield
.tmmword
14075 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
14076 || flag_code
!= CODE_64BIT
))
14079 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
14082 /* Don't allow fake index register unless allow_index_reg isn't 0. */
14083 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
14086 /* Upper 16 vector registers are only available with VREX in 64bit
14087 mode, and require EVEX encoding. */
14088 if (r
->reg_flags
& RegVRex
)
14090 if (!cpu_arch_flags
.bitfield
.cpuavx512f
14091 || flag_code
!= CODE_64BIT
)
14094 if (i
.vec_encoding
== vex_encoding_default
14095 || i
.vec_encoding
== vex_encoding_evex512
)
14096 i
.vec_encoding
= vex_encoding_evex
;
14097 else if (i
.vec_encoding
!= vex_encoding_evex
)
14098 i
.vec_encoding
= vex_encoding_error
;
14101 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
14102 && (!cpu_arch_flags
.bitfield
.cpu64
14103 || r
->reg_type
.bitfield
.class != RegCR
14105 && flag_code
!= CODE_64BIT
)
14108 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
14115 /* REG_STRING starts *before* REGISTER_PREFIX. */
14117 static const reg_entry
*
14118 parse_real_register (const char *reg_string
, char **end_op
)
14120 const char *s
= reg_string
;
14122 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
14123 const reg_entry
*r
;
14125 /* Skip possible REGISTER_PREFIX and possible whitespace. */
14126 if (*s
== REGISTER_PREFIX
)
14129 if (is_space_char (*s
))
14132 p
= reg_name_given
;
14133 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
14135 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
14136 return (const reg_entry
*) NULL
;
14140 if (is_part_of_name (*s
))
14141 return (const reg_entry
*) NULL
;
14143 *end_op
= (char *) s
;
14145 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
14147 /* Handle floating point regs, allowing spaces in the (i) part. */
14150 if (!cpu_arch_flags
.bitfield
.cpu8087
14151 && !cpu_arch_flags
.bitfield
.cpu287
14152 && !cpu_arch_flags
.bitfield
.cpu387
14153 && !allow_pseudo_reg
)
14154 return (const reg_entry
*) NULL
;
14156 if (is_space_char (*s
))
14161 if (is_space_char (*s
))
14163 if (*s
>= '0' && *s
<= '7')
14165 int fpr
= *s
- '0';
14167 if (is_space_char (*s
))
14171 *end_op
= (char *) s
+ 1;
14172 know (r
[fpr
].reg_num
== fpr
);
14176 /* We have "%st(" then garbage. */
14177 return (const reg_entry
*) NULL
;
14181 return r
&& check_register (r
) ? r
: NULL
;
14184 /* REG_STRING starts *before* REGISTER_PREFIX. */
14186 static const reg_entry
*
14187 parse_register (const char *reg_string
, char **end_op
)
14189 const reg_entry
*r
;
14191 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
14192 r
= parse_real_register (reg_string
, end_op
);
14197 char *save
= input_line_pointer
;
14198 char *buf
= xstrdup (reg_string
), *name
;
14201 input_line_pointer
= buf
;
14202 get_symbol_name (&name
);
14203 symbolP
= symbol_find (name
);
14204 while (symbolP
&& symbol_equated_p (symbolP
))
14206 const expressionS
*e
= symbol_get_value_expression(symbolP
);
14208 if (e
->X_add_number
)
14210 symbolP
= e
->X_add_symbol
;
14212 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
14214 const expressionS
*e
= symbol_get_value_expression (symbolP
);
14216 if (e
->X_op
== O_register
)
14218 know (e
->X_add_number
>= 0
14219 && (valueT
) e
->X_add_number
< i386_regtab_size
);
14220 r
= i386_regtab
+ e
->X_add_number
;
14221 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
14223 if (r
&& !check_register (r
))
14225 as_bad (_("register '%s%s' cannot be used here"),
14226 register_prefix
, r
->reg_name
);
14230 input_line_pointer
= save
;
14237 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
14239 const reg_entry
*r
= NULL
;
14240 char *end
= input_line_pointer
;
14242 /* We only know the terminating character here. It being double quote could
14243 be the closing one of a quoted symbol name, or an opening one from a
14244 following string (or another quoted symbol name). Since the latter can't
14245 be valid syntax for anything, bailing in either case is good enough. */
14246 if (*nextcharP
== '"')
14250 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
14251 r
= parse_real_register (name
, &input_line_pointer
);
14252 if (r
&& end
<= input_line_pointer
)
14254 *nextcharP
= *input_line_pointer
;
14255 *input_line_pointer
= 0;
14256 e
->X_op
= O_register
;
14257 e
->X_add_number
= r
- i386_regtab
;
14260 input_line_pointer
= end
;
14262 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
14266 md_operand (expressionS
*e
)
14269 const reg_entry
*r
;
14271 switch (*input_line_pointer
)
14273 case REGISTER_PREFIX
:
14274 r
= parse_real_register (input_line_pointer
, &end
);
14277 e
->X_op
= O_register
;
14278 e
->X_add_number
= r
- i386_regtab
;
14279 input_line_pointer
= end
;
14284 gas_assert (intel_syntax
);
14285 end
= input_line_pointer
++;
14287 if (*input_line_pointer
== ']')
14289 ++input_line_pointer
;
14290 e
->X_op_symbol
= make_expr_symbol (e
);
14291 e
->X_add_symbol
= NULL
;
14292 e
->X_add_number
= 0;
14297 e
->X_op
= O_absent
;
14298 input_line_pointer
= end
;
14305 /* To maintain consistency with !BFD64 builds of gas record, whether any
14306 (binary) operator was involved in an expression. As expressions are
14307 evaluated in only 32 bits when !BFD64, we use this to decide whether to
14308 truncate results. */
14309 bool i386_record_operator (operatorT op
,
14310 const expressionS
*left
,
14311 const expressionS
*right
)
14313 if (op
== O_absent
)
14318 /* Since the expression parser applies unary operators fine to bignum
14319 operands, we don't need to be concerned of respective operands not
14320 fitting in 32 bits. */
14321 if (right
->X_op
== O_constant
&& right
->X_unsigned
14322 && !fits_in_unsigned_long (right
->X_add_number
))
14325 /* This isn't entirely right: The pattern can also result when constant
14326 expressions are folded (e.g. 0xffffffff + 1). */
14327 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
14328 && !fits_in_unsigned_long (left
->X_add_number
))
14329 || (right
->X_op
== O_constant
&& right
->X_unsigned
14330 && !fits_in_unsigned_long (right
->X_add_number
)))
14331 expr_mode
= expr_large_value
;
14333 if (expr_mode
!= expr_large_value
)
14334 expr_mode
= expr_operator_present
;
14340 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14341 const char *md_shortopts
= "kVQ:sqnO::";
14343 const char *md_shortopts
= "qnO::";
14346 #define OPTION_32 (OPTION_MD_BASE + 0)
14347 #define OPTION_64 (OPTION_MD_BASE + 1)
14348 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
14349 #define OPTION_MARCH (OPTION_MD_BASE + 3)
14350 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
14351 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
14352 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
14353 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
14354 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
14355 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
14356 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
14357 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
14358 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
14359 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
14360 #define OPTION_X32 (OPTION_MD_BASE + 14)
14361 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
14362 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
14363 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
14364 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
14365 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
14366 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
14367 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
14368 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
14369 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
14370 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
14371 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
14372 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
14373 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
14374 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
14375 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
14376 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
14377 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
14378 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
14379 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
14380 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
14382 struct option md_longopts
[] =
14384 {"32", no_argument
, NULL
, OPTION_32
},
14385 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14386 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14387 {"64", no_argument
, NULL
, OPTION_64
},
14389 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14390 {"x32", no_argument
, NULL
, OPTION_X32
},
14391 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14392 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
14394 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
14395 {"march", required_argument
, NULL
, OPTION_MARCH
},
14396 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14397 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
14398 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
14399 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
14400 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
14401 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
14402 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
14403 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
14404 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
14405 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
14406 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
14407 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
14408 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
14409 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
14410 # if defined (TE_PE) || defined (TE_PEP)
14411 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
14413 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
14414 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
14415 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
14416 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
14417 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
14418 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
14419 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
14420 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
14421 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
14422 {"mlfence-before-indirect-branch", required_argument
, NULL
,
14423 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
14424 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
14425 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
14426 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
14427 {NULL
, no_argument
, NULL
, 0}
14429 size_t md_longopts_size
= sizeof (md_longopts
);
14432 md_parse_option (int c
, const char *arg
)
14435 char *arch
, *next
, *saved
, *type
;
14440 optimize_align_code
= 0;
14444 quiet_warnings
= 1;
14447 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14448 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
14449 should be emitted or not. FIXME: Not implemented. */
14451 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
14455 /* -V: SVR4 argument to print version ID. */
14457 print_version_id ();
14460 /* -k: Ignore for FreeBSD compatibility. */
14465 /* -s: On i386 Solaris, this tells the native assembler to use
14466 .stab instead of .stab.excl. We always use .stab anyhow. */
14469 case OPTION_MSHARED
:
14473 case OPTION_X86_USED_NOTE
:
14474 if (strcasecmp (arg
, "yes") == 0)
14476 else if (strcasecmp (arg
, "no") == 0)
14479 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
14484 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14485 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14488 const char **list
, **l
;
14490 list
= bfd_target_list ();
14491 for (l
= list
; *l
!= NULL
; l
++)
14492 if (startswith (*l
, "elf64-x86-64")
14493 || strcmp (*l
, "coff-x86-64") == 0
14494 || strcmp (*l
, "pe-x86-64") == 0
14495 || strcmp (*l
, "pei-x86-64") == 0
14496 || strcmp (*l
, "mach-o-x86-64") == 0)
14498 default_arch
= "x86_64";
14502 as_fatal (_("no compiled in support for x86_64"));
14508 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14512 const char **list
, **l
;
14514 list
= bfd_target_list ();
14515 for (l
= list
; *l
!= NULL
; l
++)
14516 if (startswith (*l
, "elf32-x86-64"))
14518 default_arch
= "x86_64:32";
14522 as_fatal (_("no compiled in support for 32bit x86_64"));
14526 as_fatal (_("32bit x86_64 is only supported for ELF"));
14532 const char **list
, **l
;
14534 list
= bfd_target_list ();
14535 for (l
= list
; *l
!= NULL
; l
++)
14536 if (strstr (*l
, "-i386")
14537 || strstr (*l
, "-go32"))
14539 default_arch
= "i386";
14543 as_fatal (_("no compiled in support for ix86"));
14548 case OPTION_DIVIDE
:
14549 #ifdef SVR4_COMMENT_CHARS
14554 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
14556 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
14560 i386_comment_chars
= n
;
14566 saved
= xstrdup (arg
);
14568 /* Allow -march=+nosse. */
14576 as_fatal (_("invalid -march= option: `%s'"), arg
);
14577 next
= strchr (arch
, '+');
14580 vsz
= strchr (arch
, '/');
14583 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14585 if (vsz
&& cpu_arch
[j
].vsz
!= vsz_set
)
14588 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
14589 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
14592 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14595 cpu_arch_name
= cpu_arch
[j
].name
;
14596 free (cpu_sub_arch_name
);
14597 cpu_sub_arch_name
= NULL
;
14598 cpu_arch_flags
= cpu_arch
[j
].enable
;
14599 cpu_arch_isa
= cpu_arch
[j
].type
;
14600 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
14601 if (!cpu_arch_tune_set
)
14603 cpu_arch_tune
= cpu_arch_isa
;
14604 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
14606 vector_size
= VSZ_DEFAULT
;
14609 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
14610 && strcmp (arch
, cpu_arch
[j
].name
) == 0
14611 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14613 /* ISA extension. */
14614 i386_cpu_flags flags
;
14616 flags
= cpu_flags_or (cpu_arch_flags
,
14617 cpu_arch
[j
].enable
);
14619 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
14621 extend_cpu_sub_arch_name (arch
);
14622 cpu_arch_flags
= flags
;
14623 cpu_arch_isa_flags
= flags
;
14627 = cpu_flags_or (cpu_arch_isa_flags
,
14628 cpu_arch
[j
].enable
);
14630 switch (cpu_arch
[j
].vsz
)
14639 unsigned long val
= strtoul (vsz
, &end
, 0);
14645 case 512: vector_size
= VSZ512
; break;
14646 case 256: vector_size
= VSZ256
; break;
14647 case 128: vector_size
= VSZ128
; break;
14649 as_warn (_("Unrecognized vector size specifier ignored"));
14654 /* Fall through. */
14656 vector_size
= VSZ_DEFAULT
;
14664 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
14666 /* Disable an ISA extension. */
14667 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14668 if (cpu_arch
[j
].type
== PROCESSOR_NONE
14669 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
14671 i386_cpu_flags flags
;
14673 flags
= cpu_flags_and_not (cpu_arch_flags
,
14674 cpu_arch
[j
].disable
);
14675 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
14677 extend_cpu_sub_arch_name (arch
);
14678 cpu_arch_flags
= flags
;
14679 cpu_arch_isa_flags
= flags
;
14681 if (cpu_arch
[j
].vsz
== vsz_set
)
14682 vector_size
= VSZ_DEFAULT
;
14687 if (j
>= ARRAY_SIZE (cpu_arch
))
14688 as_fatal (_("invalid -march= option: `%s'"), arg
);
14692 while (next
!= NULL
);
14698 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14699 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14701 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14702 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
14704 cpu_arch_tune_set
= 1;
14705 cpu_arch_tune
= cpu_arch
[j
].type
;
14706 cpu_arch_tune_flags
= cpu_arch
[j
].enable
;
14710 if (j
>= ARRAY_SIZE (cpu_arch
))
14711 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14714 case OPTION_MMNEMONIC
:
14715 if (strcasecmp (arg
, "att") == 0)
14716 intel_mnemonic
= 0;
14717 else if (strcasecmp (arg
, "intel") == 0)
14718 intel_mnemonic
= 1;
14720 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
14723 case OPTION_MSYNTAX
:
14724 if (strcasecmp (arg
, "att") == 0)
14726 else if (strcasecmp (arg
, "intel") == 0)
14729 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
14732 case OPTION_MINDEX_REG
:
14733 allow_index_reg
= 1;
14736 case OPTION_MNAKED_REG
:
14737 allow_naked_reg
= 1;
14740 case OPTION_MSSE2AVX
:
14744 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
14745 use_unaligned_vector_move
= 1;
14748 case OPTION_MSSE_CHECK
:
14749 if (strcasecmp (arg
, "error") == 0)
14750 sse_check
= check_error
;
14751 else if (strcasecmp (arg
, "warning") == 0)
14752 sse_check
= check_warning
;
14753 else if (strcasecmp (arg
, "none") == 0)
14754 sse_check
= check_none
;
14756 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
14759 case OPTION_MOPERAND_CHECK
:
14760 if (strcasecmp (arg
, "error") == 0)
14761 operand_check
= check_error
;
14762 else if (strcasecmp (arg
, "warning") == 0)
14763 operand_check
= check_warning
;
14764 else if (strcasecmp (arg
, "none") == 0)
14765 operand_check
= check_none
;
14767 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
14770 case OPTION_MAVXSCALAR
:
14771 if (strcasecmp (arg
, "128") == 0)
14772 avxscalar
= vex128
;
14773 else if (strcasecmp (arg
, "256") == 0)
14774 avxscalar
= vex256
;
14776 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
14779 case OPTION_MVEXWIG
:
14780 if (strcmp (arg
, "0") == 0)
14782 else if (strcmp (arg
, "1") == 0)
14785 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
14788 case OPTION_MADD_BND_PREFIX
:
14789 add_bnd_prefix
= 1;
14792 case OPTION_MEVEXLIG
:
14793 if (strcmp (arg
, "128") == 0)
14794 evexlig
= evexl128
;
14795 else if (strcmp (arg
, "256") == 0)
14796 evexlig
= evexl256
;
14797 else if (strcmp (arg
, "512") == 0)
14798 evexlig
= evexl512
;
14800 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
14803 case OPTION_MEVEXRCIG
:
14804 if (strcmp (arg
, "rne") == 0)
14806 else if (strcmp (arg
, "rd") == 0)
14808 else if (strcmp (arg
, "ru") == 0)
14810 else if (strcmp (arg
, "rz") == 0)
14813 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
14816 case OPTION_MEVEXWIG
:
14817 if (strcmp (arg
, "0") == 0)
14819 else if (strcmp (arg
, "1") == 0)
14822 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
14825 # if defined (TE_PE) || defined (TE_PEP)
14826 case OPTION_MBIG_OBJ
:
14831 case OPTION_MOMIT_LOCK_PREFIX
:
14832 if (strcasecmp (arg
, "yes") == 0)
14833 omit_lock_prefix
= 1;
14834 else if (strcasecmp (arg
, "no") == 0)
14835 omit_lock_prefix
= 0;
14837 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
14840 case OPTION_MFENCE_AS_LOCK_ADD
:
14841 if (strcasecmp (arg
, "yes") == 0)
14843 else if (strcasecmp (arg
, "no") == 0)
14846 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
14849 case OPTION_MLFENCE_AFTER_LOAD
:
14850 if (strcasecmp (arg
, "yes") == 0)
14851 lfence_after_load
= 1;
14852 else if (strcasecmp (arg
, "no") == 0)
14853 lfence_after_load
= 0;
14855 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
14858 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
14859 if (strcasecmp (arg
, "all") == 0)
14861 lfence_before_indirect_branch
= lfence_branch_all
;
14862 if (lfence_before_ret
== lfence_before_ret_none
)
14863 lfence_before_ret
= lfence_before_ret_shl
;
14865 else if (strcasecmp (arg
, "memory") == 0)
14866 lfence_before_indirect_branch
= lfence_branch_memory
;
14867 else if (strcasecmp (arg
, "register") == 0)
14868 lfence_before_indirect_branch
= lfence_branch_register
;
14869 else if (strcasecmp (arg
, "none") == 0)
14870 lfence_before_indirect_branch
= lfence_branch_none
;
14872 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
14876 case OPTION_MLFENCE_BEFORE_RET
:
14877 if (strcasecmp (arg
, "or") == 0)
14878 lfence_before_ret
= lfence_before_ret_or
;
14879 else if (strcasecmp (arg
, "not") == 0)
14880 lfence_before_ret
= lfence_before_ret_not
;
14881 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
14882 lfence_before_ret
= lfence_before_ret_shl
;
14883 else if (strcasecmp (arg
, "none") == 0)
14884 lfence_before_ret
= lfence_before_ret_none
;
14886 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
14890 case OPTION_MRELAX_RELOCATIONS
:
14891 if (strcasecmp (arg
, "yes") == 0)
14892 generate_relax_relocations
= 1;
14893 else if (strcasecmp (arg
, "no") == 0)
14894 generate_relax_relocations
= 0;
14896 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
14899 case OPTION_MALIGN_BRANCH_BOUNDARY
:
14902 long int align
= strtoul (arg
, &end
, 0);
14907 align_branch_power
= 0;
14910 else if (align
>= 16)
14913 for (align_power
= 0;
14915 align
>>= 1, align_power
++)
14917 /* Limit alignment power to 31. */
14918 if (align
== 1 && align_power
< 32)
14920 align_branch_power
= align_power
;
14925 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
14929 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
14932 int align
= strtoul (arg
, &end
, 0);
14933 /* Some processors only support 5 prefixes. */
14934 if (*end
== '\0' && align
>= 0 && align
< 6)
14936 align_branch_prefix_size
= align
;
14939 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
14944 case OPTION_MALIGN_BRANCH
:
14946 saved
= xstrdup (arg
);
14950 next
= strchr (type
, '+');
14953 if (strcasecmp (type
, "jcc") == 0)
14954 align_branch
|= align_branch_jcc_bit
;
14955 else if (strcasecmp (type
, "fused") == 0)
14956 align_branch
|= align_branch_fused_bit
;
14957 else if (strcasecmp (type
, "jmp") == 0)
14958 align_branch
|= align_branch_jmp_bit
;
14959 else if (strcasecmp (type
, "call") == 0)
14960 align_branch
|= align_branch_call_bit
;
14961 else if (strcasecmp (type
, "ret") == 0)
14962 align_branch
|= align_branch_ret_bit
;
14963 else if (strcasecmp (type
, "indirect") == 0)
14964 align_branch
|= align_branch_indirect_bit
;
14966 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14969 while (next
!= NULL
);
14973 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14974 align_branch_power
= 5;
14975 align_branch_prefix_size
= 5;
14976 align_branch
= (align_branch_jcc_bit
14977 | align_branch_fused_bit
14978 | align_branch_jmp_bit
);
14981 case OPTION_MAMD64
:
14985 case OPTION_MINTEL64
:
14993 /* Turn off -Os. */
14994 optimize_for_space
= 0;
14996 else if (*arg
== 's')
14998 optimize_for_space
= 1;
14999 /* Turn on all encoding optimizations. */
15000 optimize
= INT_MAX
;
15004 optimize
= atoi (arg
);
15005 /* Turn off -Os. */
15006 optimize_for_space
= 0;
15016 #define MESSAGE_TEMPLATE \
15020 output_message (FILE *stream
, char *p
, char *message
, char *start
,
15021 int *left_p
, const char *name
, int len
)
15023 int size
= sizeof (MESSAGE_TEMPLATE
);
15024 int left
= *left_p
;
15026 /* Reserve 2 spaces for ", " or ",\0" */
15029 /* Check if there is any room. */
15037 p
= mempcpy (p
, name
, len
);
15041 /* Output the current message now and start a new one. */
15044 fprintf (stream
, "%s\n", message
);
15046 left
= size
- (start
- message
) - len
- 2;
15048 gas_assert (left
>= 0);
15050 p
= mempcpy (p
, name
, len
);
15058 show_arch (FILE *stream
, int ext
, int check
)
15060 static char message
[] = MESSAGE_TEMPLATE
;
15061 char *start
= message
+ 27;
15063 int size
= sizeof (MESSAGE_TEMPLATE
);
15070 left
= size
- (start
- message
);
15074 p
= output_message (stream
, p
, message
, start
, &left
,
15075 STRING_COMMA_LEN ("default"));
15076 p
= output_message (stream
, p
, message
, start
, &left
,
15077 STRING_COMMA_LEN ("push"));
15078 p
= output_message (stream
, p
, message
, start
, &left
,
15079 STRING_COMMA_LEN ("pop"));
15082 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15084 /* Should it be skipped? */
15085 if (cpu_arch
[j
].skip
)
15088 name
= cpu_arch
[j
].name
;
15089 len
= cpu_arch
[j
].len
;
15090 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
15092 /* It is an extension. Skip if we aren't asked to show it. */
15093 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15098 /* It is an processor. Skip if we show only extension. */
15101 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
15103 /* It is an impossible processor - skip. */
15107 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
15110 /* Display disabled extensions. */
15112 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15116 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
15117 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15119 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
15120 p
= output_message (stream
, p
, message
, start
, &left
, str
,
15126 fprintf (stream
, "%s\n", message
);
15130 md_show_usage (FILE *stream
)
15132 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15133 fprintf (stream
, _("\
15134 -Qy, -Qn ignored\n\
15135 -V print assembler version number\n\
15138 fprintf (stream
, _("\
15139 -n do not optimize code alignment\n\
15140 -O{012s} attempt some code optimizations\n\
15141 -q quieten some warnings\n"));
15142 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15143 fprintf (stream
, _("\
15147 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15148 fprintf (stream
, _("\
15149 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
15150 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
15151 fprintf (stream
, _("\
15152 --32/--64 generate 32bit/64bit object\n"));
15155 #ifdef SVR4_COMMENT_CHARS
15156 fprintf (stream
, _("\
15157 --divide do not treat `/' as a comment character\n"));
15159 fprintf (stream
, _("\
15160 --divide ignored\n"));
15162 fprintf (stream
, _("\
15163 -march=CPU[,+EXTENSION...]\n\
15164 generate code for CPU and EXTENSION, CPU is one of:\n"));
15165 show_arch (stream
, 0, 1);
15166 fprintf (stream
, _("\
15167 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
15168 show_arch (stream
, 1, 0);
15169 fprintf (stream
, _("\
15170 -mtune=CPU optimize for CPU, CPU is one of:\n"));
15171 show_arch (stream
, 0, 0);
15172 fprintf (stream
, _("\
15173 -msse2avx encode SSE instructions with VEX prefix\n"));
15174 fprintf (stream
, _("\
15175 -muse-unaligned-vector-move\n\
15176 encode aligned vector move as unaligned vector move\n"));
15177 fprintf (stream
, _("\
15178 -msse-check=[none|error|warning] (default: warning)\n\
15179 check SSE instructions\n"));
15180 fprintf (stream
, _("\
15181 -moperand-check=[none|error|warning] (default: warning)\n\
15182 check operand combinations for validity\n"));
15183 fprintf (stream
, _("\
15184 -mavxscalar=[128|256] (default: 128)\n\
15185 encode scalar AVX instructions with specific vector\n\
15187 fprintf (stream
, _("\
15188 -mvexwig=[0|1] (default: 0)\n\
15189 encode VEX instructions with specific VEX.W value\n\
15190 for VEX.W bit ignored instructions\n"));
15191 fprintf (stream
, _("\
15192 -mevexlig=[128|256|512] (default: 128)\n\
15193 encode scalar EVEX instructions with specific vector\n\
15195 fprintf (stream
, _("\
15196 -mevexwig=[0|1] (default: 0)\n\
15197 encode EVEX instructions with specific EVEX.W value\n\
15198 for EVEX.W bit ignored instructions\n"));
15199 fprintf (stream
, _("\
15200 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
15201 encode EVEX instructions with specific EVEX.RC value\n\
15202 for SAE-only ignored instructions\n"));
15203 fprintf (stream
, _("\
15204 -mmnemonic=[att|intel] "));
15205 if (SYSV386_COMPAT
)
15206 fprintf (stream
, _("(default: att)\n"));
15208 fprintf (stream
, _("(default: intel)\n"));
15209 fprintf (stream
, _("\
15210 use AT&T/Intel mnemonic\n"));
15211 fprintf (stream
, _("\
15212 -msyntax=[att|intel] (default: att)\n\
15213 use AT&T/Intel syntax\n"));
15214 fprintf (stream
, _("\
15215 -mindex-reg support pseudo index registers\n"));
15216 fprintf (stream
, _("\
15217 -mnaked-reg don't require `%%' prefix for registers\n"));
15218 fprintf (stream
, _("\
15219 -madd-bnd-prefix add BND prefix for all valid branches\n"));
15220 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15221 fprintf (stream
, _("\
15222 -mshared disable branch optimization for shared code\n"));
15223 fprintf (stream
, _("\
15224 -mx86-used-note=[no|yes] "));
15225 if (DEFAULT_X86_USED_NOTE
)
15226 fprintf (stream
, _("(default: yes)\n"));
15228 fprintf (stream
, _("(default: no)\n"));
15229 fprintf (stream
, _("\
15230 generate x86 used ISA and feature properties\n"));
15232 #if defined (TE_PE) || defined (TE_PEP)
15233 fprintf (stream
, _("\
15234 -mbig-obj generate big object files\n"));
15236 fprintf (stream
, _("\
15237 -momit-lock-prefix=[no|yes] (default: no)\n\
15238 strip all lock prefixes\n"));
15239 fprintf (stream
, _("\
15240 -mfence-as-lock-add=[no|yes] (default: no)\n\
15241 encode lfence, mfence and sfence as\n\
15242 lock addl $0x0, (%%{re}sp)\n"));
15243 fprintf (stream
, _("\
15244 -mrelax-relocations=[no|yes] "));
15245 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
15246 fprintf (stream
, _("(default: yes)\n"));
15248 fprintf (stream
, _("(default: no)\n"));
15249 fprintf (stream
, _("\
15250 generate relax relocations\n"));
15251 fprintf (stream
, _("\
15252 -malign-branch-boundary=NUM (default: 0)\n\
15253 align branches within NUM byte boundary\n"));
15254 fprintf (stream
, _("\
15255 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
15256 TYPE is combination of jcc, fused, jmp, call, ret,\n\
15258 specify types of branches to align\n"));
15259 fprintf (stream
, _("\
15260 -malign-branch-prefix-size=NUM (default: 5)\n\
15261 align branches with NUM prefixes per instruction\n"));
15262 fprintf (stream
, _("\
15263 -mbranches-within-32B-boundaries\n\
15264 align branches within 32 byte boundary\n"));
15265 fprintf (stream
, _("\
15266 -mlfence-after-load=[no|yes] (default: no)\n\
15267 generate lfence after load\n"));
15268 fprintf (stream
, _("\
15269 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
15270 generate lfence before indirect near branch\n"));
15271 fprintf (stream
, _("\
15272 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
15273 generate lfence before ret\n"));
15274 fprintf (stream
, _("\
15275 -mamd64 accept only AMD64 ISA [default]\n"));
15276 fprintf (stream
, _("\
15277 -mintel64 accept only Intel64 ISA\n"));
15280 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
15281 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
15282 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
15284 /* Pick the target format to use. */
15287 i386_target_format (void)
15289 if (startswith (default_arch
, "x86_64"))
15291 update_code_flag (CODE_64BIT
, 1);
15292 if (default_arch
[6] == '\0')
15293 x86_elf_abi
= X86_64_ABI
;
15295 x86_elf_abi
= X86_64_X32_ABI
;
15297 else if (!strcmp (default_arch
, "i386"))
15298 update_code_flag (CODE_32BIT
, 1);
15299 else if (!strcmp (default_arch
, "iamcu"))
15301 update_code_flag (CODE_32BIT
, 1);
15302 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
15304 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
15305 cpu_arch_name
= "iamcu";
15306 free (cpu_sub_arch_name
);
15307 cpu_sub_arch_name
= NULL
;
15308 cpu_arch_flags
= iamcu_flags
;
15309 cpu_arch_isa
= PROCESSOR_IAMCU
;
15310 cpu_arch_isa_flags
= iamcu_flags
;
15311 if (!cpu_arch_tune_set
)
15313 cpu_arch_tune
= cpu_arch_isa
;
15314 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
15317 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
15318 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
15322 as_fatal (_("unknown architecture"));
15324 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
15325 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15326 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
15327 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15329 switch (OUTPUT_FLAVOR
)
15331 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
15332 case bfd_target_aout_flavour
:
15333 return AOUT_TARGET_FORMAT
;
15335 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
15336 # if defined (TE_PE) || defined (TE_PEP)
15337 case bfd_target_coff_flavour
:
15338 if (flag_code
== CODE_64BIT
)
15341 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
15343 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
15344 # elif defined (TE_GO32)
15345 case bfd_target_coff_flavour
:
15346 return "coff-go32";
15348 case bfd_target_coff_flavour
:
15349 return "coff-i386";
15352 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15353 case bfd_target_elf_flavour
:
15355 const char *format
;
15357 switch (x86_elf_abi
)
15360 format
= ELF_TARGET_FORMAT
;
15362 tls_get_addr
= "___tls_get_addr";
15366 use_rela_relocations
= 1;
15369 tls_get_addr
= "__tls_get_addr";
15371 format
= ELF_TARGET_FORMAT64
;
15373 case X86_64_X32_ABI
:
15374 use_rela_relocations
= 1;
15377 tls_get_addr
= "__tls_get_addr";
15379 disallow_64bit_reloc
= 1;
15380 format
= ELF_TARGET_FORMAT32
;
15383 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
15385 if (x86_elf_abi
!= I386_ABI
)
15386 as_fatal (_("Intel MCU is 32bit only"));
15387 return ELF_TARGET_IAMCU_FORMAT
;
15393 #if defined (OBJ_MACH_O)
15394 case bfd_target_mach_o_flavour
:
15395 if (flag_code
== CODE_64BIT
)
15397 use_rela_relocations
= 1;
15399 return "mach-o-x86-64";
15402 return "mach-o-i386";
15410 #endif /* OBJ_MAYBE_ more than one */
15413 md_undefined_symbol (char *name
)
15415 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
15416 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
15417 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
15418 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
15422 if (symbol_find (name
))
15423 as_bad (_("GOT already in symbol table"));
15424 GOT_symbol
= symbol_new (name
, undefined_section
,
15425 &zero_address_frag
, 0);
15432 /* Round up a section size to the appropriate boundary. */
15435 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
15437 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
15438 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
15440 /* For a.out, force the section size to be aligned. If we don't do
15441 this, BFD will align it for us, but it will not write out the
15442 final bytes of the section. This may be a bug in BFD, but it is
15443 easier to fix it here since that is how the other a.out targets
15447 align
= bfd_section_alignment (segment
);
15448 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
15455 /* On the i386, PC-relative offsets are relative to the start of the
15456 next instruction. That is, the address of the offset, plus its
15457 size, since the offset is always the last part of the insn. */
15460 md_pcrel_from (fixS
*fixP
)
15462 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15468 s_bss (int ignore ATTRIBUTE_UNUSED
)
15472 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15474 obj_elf_section_change_hook ();
15476 temp
= get_absolute_expression ();
15477 subseg_set (bss_section
, (subsegT
) temp
);
15478 demand_empty_rest_of_line ();
15483 /* Remember constant directive. */
15486 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
15488 if (last_insn
.kind
!= last_insn_directive
15489 && (bfd_section_flags (now_seg
) & SEC_CODE
))
15491 last_insn
.seg
= now_seg
;
15492 last_insn
.kind
= last_insn_directive
;
15493 last_insn
.name
= "constant directive";
15494 last_insn
.file
= as_where (&last_insn
.line
);
15495 if (lfence_before_ret
!= lfence_before_ret_none
)
15497 if (lfence_before_indirect_branch
!= lfence_branch_none
)
15498 as_warn (_("constant directive skips -mlfence-before-ret "
15499 "and -mlfence-before-indirect-branch"));
15501 as_warn (_("constant directive skips -mlfence-before-ret"));
15503 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
15504 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
15509 i386_validate_fix (fixS
*fixp
)
15511 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
15513 reloc_howto_type
*howto
;
15515 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
15516 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15517 _("invalid %s relocation against register"),
15518 howto
? howto
->name
: "<unknown>");
15522 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15523 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15524 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
15525 return IS_ELF
&& fixp
->fx_addsy
15526 && (!S_IS_DEFINED (fixp
->fx_addsy
)
15527 || S_IS_EXTERNAL (fixp
->fx_addsy
));
15530 if (fixp
->fx_subsy
)
15532 if (fixp
->fx_subsy
== GOT_symbol
)
15534 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
15538 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15539 if (fixp
->fx_tcbit2
)
15540 fixp
->fx_r_type
= (fixp
->fx_tcbit
15541 ? BFD_RELOC_X86_64_REX_GOTPCRELX
15542 : BFD_RELOC_X86_64_GOTPCRELX
);
15545 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
15550 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
15552 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
15554 fixp
->fx_subsy
= 0;
15557 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15560 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
15561 to section. Since PLT32 relocation must be against symbols,
15562 turn such PLT32 relocation into PC32 relocation. */
15564 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
15565 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
15566 && symbol_section_p (fixp
->fx_addsy
))
15567 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
15570 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
15571 && fixp
->fx_tcbit2
)
15572 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
15581 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
15584 bfd_reloc_code_real_type code
;
15586 switch (fixp
->fx_r_type
)
15588 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15591 case BFD_RELOC_SIZE32
:
15592 case BFD_RELOC_SIZE64
:
15594 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
15595 && (!fixp
->fx_subsy
15596 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
15597 sym
= fixp
->fx_addsy
;
15598 else if (fixp
->fx_subsy
15599 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
15600 && (!fixp
->fx_addsy
15601 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
15602 sym
= fixp
->fx_subsy
;
15605 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
15607 /* Resolve size relocation against local symbol to size of
15608 the symbol plus addend. */
15609 valueT value
= S_GET_SIZE (sym
);
15611 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
15612 value
= bfd_section_size (S_GET_SEGMENT (sym
));
15613 if (sym
== fixp
->fx_subsy
)
15616 if (fixp
->fx_addsy
)
15617 value
+= S_GET_VALUE (fixp
->fx_addsy
);
15619 else if (fixp
->fx_subsy
)
15620 value
-= S_GET_VALUE (fixp
->fx_subsy
);
15621 value
+= fixp
->fx_offset
;
15622 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15624 && !fits_in_unsigned_long (value
))
15625 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15626 _("symbol size computation overflow"));
15627 fixp
->fx_addsy
= NULL
;
15628 fixp
->fx_subsy
= NULL
;
15629 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
15632 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
15634 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15635 "unsupported expression involving @size");
15639 /* Fall through. */
15641 case BFD_RELOC_X86_64_PLT32
:
15642 case BFD_RELOC_X86_64_GOT32
:
15643 case BFD_RELOC_X86_64_GOTPCREL
:
15644 case BFD_RELOC_X86_64_GOTPCRELX
:
15645 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15646 case BFD_RELOC_386_PLT32
:
15647 case BFD_RELOC_386_GOT32
:
15648 case BFD_RELOC_386_GOT32X
:
15649 case BFD_RELOC_386_GOTOFF
:
15650 case BFD_RELOC_386_GOTPC
:
15651 case BFD_RELOC_386_TLS_GD
:
15652 case BFD_RELOC_386_TLS_LDM
:
15653 case BFD_RELOC_386_TLS_LDO_32
:
15654 case BFD_RELOC_386_TLS_IE_32
:
15655 case BFD_RELOC_386_TLS_IE
:
15656 case BFD_RELOC_386_TLS_GOTIE
:
15657 case BFD_RELOC_386_TLS_LE_32
:
15658 case BFD_RELOC_386_TLS_LE
:
15659 case BFD_RELOC_386_TLS_GOTDESC
:
15660 case BFD_RELOC_386_TLS_DESC_CALL
:
15661 case BFD_RELOC_X86_64_TLSGD
:
15662 case BFD_RELOC_X86_64_TLSLD
:
15663 case BFD_RELOC_X86_64_DTPOFF32
:
15664 case BFD_RELOC_X86_64_DTPOFF64
:
15665 case BFD_RELOC_X86_64_GOTTPOFF
:
15666 case BFD_RELOC_X86_64_TPOFF32
:
15667 case BFD_RELOC_X86_64_TPOFF64
:
15668 case BFD_RELOC_X86_64_GOTOFF64
:
15669 case BFD_RELOC_X86_64_GOTPC32
:
15670 case BFD_RELOC_X86_64_GOT64
:
15671 case BFD_RELOC_X86_64_GOTPCREL64
:
15672 case BFD_RELOC_X86_64_GOTPC64
:
15673 case BFD_RELOC_X86_64_GOTPLT64
:
15674 case BFD_RELOC_X86_64_PLTOFF64
:
15675 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15676 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15677 case BFD_RELOC_RVA
:
15678 case BFD_RELOC_VTABLE_ENTRY
:
15679 case BFD_RELOC_VTABLE_INHERIT
:
15681 case BFD_RELOC_32_SECREL
:
15682 case BFD_RELOC_16_SECIDX
:
15684 code
= fixp
->fx_r_type
;
15686 case BFD_RELOC_X86_64_32S
:
15687 if (!fixp
->fx_pcrel
)
15689 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
15690 code
= fixp
->fx_r_type
;
15693 /* Fall through. */
15695 if (fixp
->fx_pcrel
)
15697 switch (fixp
->fx_size
)
15700 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15701 _("can not do %d byte pc-relative relocation"),
15703 code
= BFD_RELOC_32_PCREL
;
15705 case 1: code
= BFD_RELOC_8_PCREL
; break;
15706 case 2: code
= BFD_RELOC_16_PCREL
; break;
15707 case 4: code
= BFD_RELOC_32_PCREL
; break;
15709 case 8: code
= BFD_RELOC_64_PCREL
; break;
15715 switch (fixp
->fx_size
)
15718 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15719 _("can not do %d byte relocation"),
15721 code
= BFD_RELOC_32
;
15723 case 1: code
= BFD_RELOC_8
; break;
15724 case 2: code
= BFD_RELOC_16
; break;
15725 case 4: code
= BFD_RELOC_32
; break;
15727 case 8: code
= BFD_RELOC_64
; break;
15734 if ((code
== BFD_RELOC_32
15735 || code
== BFD_RELOC_32_PCREL
15736 || code
== BFD_RELOC_X86_64_32S
)
15738 && fixp
->fx_addsy
== GOT_symbol
)
15741 code
= BFD_RELOC_386_GOTPC
;
15743 code
= BFD_RELOC_X86_64_GOTPC32
;
15745 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
15747 && fixp
->fx_addsy
== GOT_symbol
)
15749 code
= BFD_RELOC_X86_64_GOTPC64
;
15752 rel
= XNEW (arelent
);
15753 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
15754 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
15756 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
15758 if (!use_rela_relocations
)
15760 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
15761 vtable entry to be used in the relocation's section offset. */
15762 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15763 rel
->address
= fixp
->fx_offset
;
15764 #if defined (OBJ_COFF) && defined (TE_PE)
15765 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
15766 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
15771 /* Use the rela in 64bit mode. */
15774 if (disallow_64bit_reloc
)
15777 case BFD_RELOC_X86_64_DTPOFF64
:
15778 case BFD_RELOC_X86_64_TPOFF64
:
15779 case BFD_RELOC_64_PCREL
:
15780 case BFD_RELOC_X86_64_GOTOFF64
:
15781 case BFD_RELOC_X86_64_GOT64
:
15782 case BFD_RELOC_X86_64_GOTPCREL64
:
15783 case BFD_RELOC_X86_64_GOTPC64
:
15784 case BFD_RELOC_X86_64_GOTPLT64
:
15785 case BFD_RELOC_X86_64_PLTOFF64
:
15786 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15787 _("cannot represent relocation type %s in x32 mode"),
15788 bfd_get_reloc_code_name (code
));
15794 if (!fixp
->fx_pcrel
)
15795 rel
->addend
= fixp
->fx_offset
;
15799 case BFD_RELOC_X86_64_PLT32
:
15800 case BFD_RELOC_X86_64_GOT32
:
15801 case BFD_RELOC_X86_64_GOTPCREL
:
15802 case BFD_RELOC_X86_64_GOTPCRELX
:
15803 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15804 case BFD_RELOC_X86_64_TLSGD
:
15805 case BFD_RELOC_X86_64_TLSLD
:
15806 case BFD_RELOC_X86_64_GOTTPOFF
:
15807 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15808 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15809 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
15812 rel
->addend
= (section
->vma
15814 + fixp
->fx_addnumber
15815 + md_pcrel_from (fixp
));
15820 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
15821 if (rel
->howto
== NULL
)
15823 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15824 _("cannot represent relocation type %s"),
15825 bfd_get_reloc_code_name (code
));
15826 /* Set howto to a garbage value so that we can keep going. */
15827 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
15828 gas_assert (rel
->howto
!= NULL
);
15834 #include "tc-i386-intel.c"
15837 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
15839 int saved_naked_reg
;
15840 char saved_register_dot
;
15842 saved_naked_reg
= allow_naked_reg
;
15843 allow_naked_reg
= 1;
15844 saved_register_dot
= register_chars
['.'];
15845 register_chars
['.'] = '.';
15846 allow_pseudo_reg
= 1;
15847 expression_and_evaluate (exp
);
15848 allow_pseudo_reg
= 0;
15849 register_chars
['.'] = saved_register_dot
;
15850 allow_naked_reg
= saved_naked_reg
;
15852 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
15854 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
15856 exp
->X_op
= O_constant
;
15857 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
15858 .dw2_regnum
[flag_code
>> 1];
15861 exp
->X_op
= O_illegal
;
15866 tc_x86_frame_initial_instructions (void)
15868 static unsigned int sp_regno
[2];
15870 if (!sp_regno
[flag_code
>> 1])
15872 char *saved_input
= input_line_pointer
;
15873 char sp
[][4] = {"esp", "rsp"};
15876 input_line_pointer
= sp
[flag_code
>> 1];
15877 tc_x86_parse_to_dw2regnum (&exp
);
15878 gas_assert (exp
.X_op
== O_constant
);
15879 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
15880 input_line_pointer
= saved_input
;
15883 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
15884 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
15888 x86_dwarf2_addr_size (void)
15890 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15891 if (x86_elf_abi
== X86_64_X32_ABI
)
15894 return bfd_arch_bits_per_address (stdoutput
) / 8;
15898 i386_elf_section_type (const char *str
, size_t len
)
15900 if (flag_code
== CODE_64BIT
15901 && len
== sizeof ("unwind") - 1
15902 && startswith (str
, "unwind"))
15903 return SHT_X86_64_UNWIND
;
15910 i386_solaris_fix_up_eh_frame (segT sec
)
15912 if (flag_code
== CODE_64BIT
)
15913 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
15919 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
15923 exp
.X_op
= O_secrel
;
15924 exp
.X_add_symbol
= symbol
;
15925 exp
.X_add_number
= 0;
15926 emit_expr (&exp
, size
);
15930 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15931 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
15934 x86_64_section_letter (int letter
, const char **ptr_msg
)
15936 if (flag_code
== CODE_64BIT
)
15939 return SHF_X86_64_LARGE
;
15941 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
15944 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
15949 handle_large_common (int small ATTRIBUTE_UNUSED
)
15951 if (flag_code
!= CODE_64BIT
)
15953 s_comm_internal (0, elf_common_parse
);
15954 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
15958 static segT lbss_section
;
15959 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15960 asection
*saved_bss_section
= bss_section
;
15962 if (lbss_section
== NULL
)
15964 flagword applicable
;
15965 segT seg
= now_seg
;
15966 subsegT subseg
= now_subseg
;
15968 /* The .lbss section is for local .largecomm symbols. */
15969 lbss_section
= subseg_new (".lbss", 0);
15970 applicable
= bfd_applicable_section_flags (stdoutput
);
15971 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15972 seg_info (lbss_section
)->bss
= 1;
15974 subseg_set (seg
, subseg
);
15977 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15978 bss_section
= lbss_section
;
15980 s_comm_internal (0, elf_common_parse
);
15982 elf_com_section_ptr
= saved_com_section_ptr
;
15983 bss_section
= saved_bss_section
;
15986 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */