gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqrshrn_n.c

   1 #include <arm_neon.h>
   2 #include "arm-neon-ref.h"
   3 #include "compute-ref-data.h"
   4
   5 /* Expected results.  */
   6 VECT_VAR_DECL(expected,int,8,8) [] = { 0xf8, 0xf9, 0xf9, 0xfa,
   7                                        0xfa, 0xfb, 0xfb, 0xfc };
   8 VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff8, 0xfff9, 0xfff9, 0xfffa };
   9 VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffffc, 0xfffffffc };
  10 VECT_VAR_DECL(expected,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff,
  11                                         0xff, 0xff, 0xff, 0xff };
  12 VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
  13 VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0xffffffff };
  14
  15 /* Expected results with shift by 3.  */
  16 VECT_VAR_DECL(expected_sh3,int,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f,
  17                                            0x7f, 0x7f, 0x7f, 0x7f };
  18 VECT_VAR_DECL(expected_sh3,int,16,4) [] = { 0x7fff, 0x7fff, 0x7fff, 0x7fff };
  19 VECT_VAR_DECL(expected_sh3,int,32,2) [] = { 0x7fffffff, 0x7fffffff };
  20 VECT_VAR_DECL(expected_sh3,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff,
  21                                             0xff, 0xff, 0xff, 0xff };
  22 VECT_VAR_DECL(expected_sh3,uint,16,4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
  23 VECT_VAR_DECL(expected_sh3,uint,32,2) [] = { 0xffffffff, 0xffffffff };
  24
  25 /* Expected results with shift by max amount.  */
  26 VECT_VAR_DECL(expected_shmax,int,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f,
  27                                              0x7f, 0x7f, 0x7f, 0x7f };
  28 VECT_VAR_DECL(expected_shmax,int,16,4) [] = { 0x7fff, 0x7fff, 0x7fff, 0x7fff };
  29 VECT_VAR_DECL(expected_shmax,int,32,2) [] = { 0x7fffffff, 0x7fffffff };
  30 VECT_VAR_DECL(expected_shmax,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff,
  31                                               0xff, 0xff, 0xff, 0xff };
  32 VECT_VAR_DECL(expected_shmax,uint,16,4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
  33 VECT_VAR_DECL(expected_shmax,uint,32,2) [] = { 0xffffffff, 0xffffffff };
  34
  35 #define INSN vqrshrn_n
  36 #define TEST_MSG "VQRSHRN_N"
  37
  38 #define FNNAME1(NAME) void exec_ ## NAME (void)
  39 #define FNNAME(NAME) FNNAME1(NAME)
  40
  41 FNNAME (INSN)
  42 {
  43   /* Basic test: y=vqrshrn_n(x,v), then store the result.  */
  44 #define TEST_VQRSHRN_N2(INSN, T1, T2, W, W2, N, V, CMT) \
  45   Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W2, N));          \
  46   VECT_VAR(vector_res, T1, W2, N) =                                     \
  47     INSN##_##T2##W(VECT_VAR(vector, T1, W, N),                          \
  48                    V);                                                  \
  49   vst1_##T2##W2(VECT_VAR(result, T1, W2, N),                            \
  50                 VECT_VAR(vector_res, T1, W2, N))
  51
  52   /* Two auxliary macros are necessary to expand INSN */
  53 #define TEST_VQRSHRN_N1(INSN, T1, T2, W, W2, N, V, CMT) \
  54   TEST_VQRSHRN_N2(INSN, T1, T2, W, W2, N, V, CMT)
  55
  56 #define TEST_VQRSHRN_N(T1, T2, W, W2, N, V, CMT) \
  57   TEST_VQRSHRN_N1(INSN, T1, T2, W, W2, N, V, CMT)
  58
  59
  60   /* vector is twice as large as vector_res.  */
  61   DECL_VARIABLE(vector, int, 16, 8);
  62   DECL_VARIABLE(vector, int, 32, 4);
  63   DECL_VARIABLE(vector, int, 64, 2);
  64   DECL_VARIABLE(vector, uint, 16, 8);
  65   DECL_VARIABLE(vector, uint, 32, 4);
  66   DECL_VARIABLE(vector, uint, 64, 2);
  67
  68   DECL_VARIABLE(vector_res, int, 8, 8);
  69   DECL_VARIABLE(vector_res, int, 16, 4);
  70   DECL_VARIABLE(vector_res, int, 32, 2);
  71   DECL_VARIABLE(vector_res, uint, 8, 8);
  72   DECL_VARIABLE(vector_res, uint, 16, 4);
  73   DECL_VARIABLE(vector_res, uint, 32, 2);
  74
  75   clean_results ();
  76
  77   VLOAD(vector, buffer, q, int, s, 16, 8);
  78   VLOAD(vector, buffer, q, int, s, 32, 4);
  79   VLOAD(vector, buffer, q, int, s, 64, 2);
  80   VLOAD(vector, buffer, q, uint, u, 16, 8);
  81   VLOAD(vector, buffer, q, uint, u, 32, 4);
  82   VLOAD(vector, buffer, q, uint, u, 64, 2);
  83
  84   /* Choose shift amount arbitrarily.  */
  85 #define CMT ""
  86   TEST_VQRSHRN_N(int, s, 16, 8, 8, 1, CMT);
  87   TEST_VQRSHRN_N(int, s, 32, 16, 4, 1, CMT);
  88   TEST_VQRSHRN_N(int, s, 64, 32, 2, 2, CMT);
  89   TEST_VQRSHRN_N(uint, u, 16, 8, 8, 2, CMT);
  90   TEST_VQRSHRN_N(uint, u, 32, 16, 4, 3, CMT);
  91   TEST_VQRSHRN_N(uint, u, 64, 32, 2, 3, CMT);
  92
  93   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, CMT);
  94   CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, CMT);
  95   CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, CMT);
  96   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, CMT);
  97   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, CMT);
  98   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, CMT);
  99
 100
 101   /* Another set of tests, shifting max value by 3.  */
 102   VDUP(vector, q, int, s, 16, 8, 0x7FFF);
 103   VDUP(vector, q, int, s, 32, 4, 0x7FFFFFFF);
 104   VDUP(vector, q, int, s, 64, 2, 0x7FFFFFFFFFFFFFFFLL);
 105   VDUP(vector, q, uint, u, 16, 8, 0xFFFF);
 106   VDUP(vector, q, uint, u, 32, 4, 0xFFFFFFFF);
 107   VDUP(vector, q, uint, u, 64, 2, 0xFFFFFFFFFFFFFFFFULL);
 108
 109 #undef CMT
 110 #define CMT " (check saturation: shift by 3)"
 111   TEST_VQRSHRN_N(int, s, 16, 8, 8, 3, CMT);
 112   TEST_VQRSHRN_N(int, s, 32, 16, 4, 3, CMT);
 113   TEST_VQRSHRN_N(int, s, 64, 32, 2, 3, CMT);
 114   TEST_VQRSHRN_N(uint, u, 16, 8, 8, 3, CMT);
 115   TEST_VQRSHRN_N(uint, u, 32, 16, 4, 3, CMT);
 116   TEST_VQRSHRN_N(uint, u, 64, 32, 2, 3, CMT);
 117
 118   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_sh3, CMT);
 119   CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_sh3, CMT);
 120   CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_sh3, CMT);
 121   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_sh3, CMT);
 122   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_sh3, CMT);
 123   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_sh3, CMT);
 124
 125
 126   /* Shift by max amount.  */
 127 #undef CMT
 128 #define CMT " (check saturation: shift by max)"
 129   TEST_VQRSHRN_N(int, s, 16, 8, 8, 8, CMT);
 130   TEST_VQRSHRN_N(int, s, 32, 16, 4, 16, CMT);
 131   TEST_VQRSHRN_N(int, s, 64, 32, 2, 32, CMT);
 132   TEST_VQRSHRN_N(uint, u, 16, 8, 8, 8, CMT);
 133   TEST_VQRSHRN_N(uint, u, 32, 16, 4, 16, CMT);
 134   TEST_VQRSHRN_N(uint, u, 64, 32, 2, 32, CMT);
 135
 136   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_shmax, CMT);
 137   CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_shmax, CMT);
 138   CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_shmax, CMT);
 139   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_shmax, CMT);
 140   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_shmax, CMT);
 141   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_shmax, CMT);
 142 }
 143
 144 int main (void)
 145 {
 146   exec_vqrshrn_n ();
 147   return 0;
 148 }