2 -- Set associative icache
4 -- TODO (in no specific order):
6 -- * Add debug interface to inspect cache content
7 -- * Add snoop/invalidate path
8 -- * Add multi-hit error detection
9 -- * Pipelined bus interface (wb or axi)
10 -- * Maybe add parity ? There's a few bits free in each BRAM row on Xilinx
11 -- * Add optimization: service hits on partially loaded lines
12 -- * Add optimization: (maybe) interrupt reload on fluch/redirect
13 -- * Check if playing with the geometry of the cache tags allow for more
14 -- efficient use of distributed RAM and less logic/muxes. Currently we
15 -- write TAG_BITS width which may not match full ram blocks and might
16 -- cause muxes to be inferred for "partial writes".
17 -- * Check if making the read size of PLRU a ROM helps utilization
20 use ieee.std_logic_1164.all;
21 use ieee.numeric_std.all;
25 use work.wishbone_types.all;
27 -- 64 bit direct mapped icache. All instructions are 4B aligned.
32 LINE_SIZE : positive := 64;
33 -- Number of lines in a set
34 NUM_LINES : positive := 32;
36 NUM_WAYS : positive := 4
42 i_in : in Fetch1ToIcacheType;
43 i_out : out IcacheToFetch2Type;
45 stall_out : out std_ulogic;
46 flush_in : in std_ulogic;
48 wishbone_out : out wishbone_master_out;
49 wishbone_in : in wishbone_slave_out
53 architecture rtl of icache is
54 function log2(i : natural) return integer is
55 variable tmp : integer := i;
56 variable ret : integer := 0;
65 function ispow2(i : integer) return boolean is
67 if to_integer(to_unsigned(i, 32) and to_unsigned(i - 1, 32)) = 0 then
74 -- BRAM organisation: We never access more than wishbone_data_bits at
75 -- a time so to save resources we make the array only that wide, and
76 -- use consecutive indices for to make a cache "line"
78 -- ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
79 constant ROW_SIZE : natural := wishbone_data_bits / 8;
80 -- ROW_PER_LINE is the number of row (wishbone transactions) in a line
81 constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
82 -- BRAM_ROWS is the number of rows in BRAM needed to represent the full
84 constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
85 -- INSN_PER_ROW is the number of 32bit instructions per BRAM row
86 constant INSN_PER_ROW : natural := wishbone_data_bits / 32;
87 -- Bit fields counts in the address
89 -- INSN_BITS is the number of bits to select an instruction in a row
90 constant INSN_BITS : natural := log2(INSN_PER_ROW);
91 -- ROW_BITS is the number of bits to select a row
92 constant ROW_BITS : natural := log2(BRAM_ROWS);
93 -- ROW_LINEBITS is the number of bits to select a row within a line
94 constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
95 -- LINE_OFF_BITS is the number of bits for the offset in a cache line
96 constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
97 -- ROW_OFF_BITS is the number of bits for the offset in a row
98 constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
99 -- INDEX_BITS is the number if bits to select a cache line
100 constant INDEX_BITS : natural := log2(NUM_LINES);
101 -- TAG_BITS is the number of bits of the tag part of the address
102 constant TAG_BITS : natural := 64 - LINE_OFF_BITS - INDEX_BITS;
103 -- WAY_BITS is the number of bits to select a way
104 constant WAY_BITS : natural := log2(NUM_WAYS);
106 -- Example of layout for 32 lines of 64 bytes:
108 -- .. tag |index| line |
110 -- .. | | | |00| zero (2)
111 -- .. | | |-| | INSN_BITS (1)
112 -- .. | |---| | ROW_LINEBITS (3)
113 -- .. | |--- - --| LINE_OFF_BITS (6)
114 -- .. | |- --| ROW_OFF_BITS (3)
115 -- .. |----- ---| | ROW_BITS (8)
116 -- .. |-----| | INDEX_BITS (5)
117 -- .. --------| | TAG_BITS (53)
119 subtype row_t is integer range 0 to BRAM_ROWS-1;
120 subtype index_t is integer range 0 to NUM_LINES-1;
121 subtype way_t is integer range 0 to NUM_WAYS-1;
123 -- The cache data BRAM organized as described above for each way
124 subtype cache_row_t is std_ulogic_vector(wishbone_data_bits-1 downto 0);
126 -- The cache tags LUTRAM has a row per set. Vivado is a pain and will
127 -- not handle a clean (commented) definition of the cache tags as a 3d
128 -- memory. For now, work around it by putting all the tags
129 subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
130 -- type cache_tags_set_t is array(way_t) of cache_tag_t;
131 -- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
132 constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
133 subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
134 type cache_tags_array_t is array(index_t) of cache_tags_set_t;
136 -- The cache valid bits
137 subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
138 type cache_valids_t is array(index_t) of cache_way_valids_t;
140 -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
141 signal cache_tags : cache_tags_array_t;
142 signal cache_valids : cache_valids_t;
144 attribute ram_style : string;
145 attribute ram_style of cache_tags : signal is "distributed";
147 -- Cache reload state machine
148 type state_t is (IDLE, WAIT_ACK);
150 type reg_internal_t is record
151 -- Cache hit state (Latches for 1 cycle BRAM access)
153 hit_nia : std_ulogic_vector(63 downto 0);
154 hit_smark : std_ulogic;
155 hit_valid : std_ulogic;
157 -- Cache miss state (reload state machine)
159 wb : wishbone_master_out;
161 store_index : index_t;
164 signal r : reg_internal_t;
166 -- Async signals on incoming request
167 signal req_index : index_t;
168 signal req_row : row_t;
169 signal req_hit_way : way_t;
170 signal req_tag : cache_tag_t;
171 signal req_is_hit : std_ulogic;
172 signal req_is_miss : std_ulogic;
174 -- Cache RAM interface
175 type cache_ram_out_t is array(way_t) of cache_row_t;
176 signal cache_out : cache_ram_out_t;
178 -- PLRU output interface
179 type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
180 signal plru_victim : plru_out_t;
181 signal replace_way : way_t;
183 -- Return the cache line index (tag index) for an address
184 function get_index(addr: std_ulogic_vector(63 downto 0)) return index_t is
186 return to_integer(unsigned(addr(63-TAG_BITS downto LINE_OFF_BITS)));
189 -- Return the cache row index (data memory) for an address
190 function get_row(addr: std_ulogic_vector(63 downto 0)) return row_t is
192 return to_integer(unsigned(addr(63-TAG_BITS downto ROW_OFF_BITS)));
195 -- Returns whether this is the last row of a line
196 function is_last_row(addr: wishbone_addr_type) return boolean is
197 constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
199 return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones;
202 -- Return the address of the next row in the current cache line
203 function next_row_addr(addr: wishbone_addr_type)
204 return std_ulogic_vector is
205 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
206 variable result : wishbone_addr_type;
208 -- Is there no simpler way in VHDL to generate that 3 bits adder ?
209 row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
210 row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
212 result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
216 -- Read the instruction word for the given address in the current cache row
217 function read_insn_word(addr: std_ulogic_vector(63 downto 0);
218 data: cache_row_t) return std_ulogic_vector is
219 variable word: integer range 0 to INSN_PER_ROW-1;
221 word := to_integer(unsigned(addr(INSN_BITS+2-1 downto 2)));
222 return data(31+word*32 downto word*32);
225 -- Get the tag value from the address
226 function get_tag(addr: std_ulogic_vector(63 downto 0)) return cache_tag_t is
228 return addr(63 downto 64-TAG_BITS);
231 -- Read a tag from a tag memory row
232 function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
234 return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
237 -- Write a tag to tag memory row
238 procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t;
241 tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
246 assert LINE_SIZE mod ROW_SIZE = 0;
247 assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE;
248 assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE;
249 assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
250 assert ispow2(INSN_PER_ROW) report "INSN_PER_ROW not power of 2" severity FAILURE;
251 assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
252 report "geometry bits don't add up" severity FAILURE;
253 assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
254 report "geometry bits don't add up" severity FAILURE;
255 assert (64 = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
256 report "geometry bits don't add up" severity FAILURE;
257 assert (64 = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
258 report "geometry bits don't add up" severity FAILURE;
262 report "ROW_SIZE = " & natural'image(ROW_SIZE);
263 report "ROW_PER_LINE = " & natural'image(ROW_PER_LINE);
264 report "BRAM_ROWS = " & natural'image(BRAM_ROWS);
265 report "INSN_PER_ROW = " & natural'image(INSN_PER_ROW);
266 report "INSN_BITS = " & natural'image(INSN_BITS);
267 report "ROW_BITS = " & natural'image(ROW_BITS);
268 report "ROW_LINEBITS = " & natural'image(ROW_LINEBITS);
269 report "LINE_OFF_BITS = " & natural'image(LINE_OFF_BITS);
270 report "ROW_OFF_BITS = " & natural'image(ROW_OFF_BITS);
271 report "INDEX_BITS = " & natural'image(INDEX_BITS);
272 report "TAG_BITS = " & natural'image(TAG_BITS);
273 report "WAY_BITS = " & natural'image(WAY_BITS);
277 -- Generate a cache RAM for each way
278 rams: for i in 0 to NUM_WAYS-1 generate
279 signal do_read : std_ulogic;
280 signal do_write : std_ulogic;
281 signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
282 signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
283 signal dout : cache_row_t;
285 way: entity work.cache_ram
287 ROW_BITS => ROW_BITS,
288 WIDTH => wishbone_data_bits
296 wr_sel => (others => '1'),
298 wr_data => wishbone_in.dat
301 variable tmp_adr : std_ulogic_vector(63 downto 0);
305 if wishbone_in.ack = '1' and r.store_way = i then
308 cache_out(i) <= dout;
309 rd_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
310 tmp_adr := (r.wb.adr'left downto 0 => r.wb.adr, others => '0');
311 wr_addr <= std_ulogic_vector(to_unsigned(get_row(tmp_adr), ROW_BITS));
316 maybe_plrus: if NUM_WAYS > 1 generate
318 plrus: for i in 0 to NUM_LINES-1 generate
320 signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
321 signal plru_acc_en : std_ulogic;
322 signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
325 plru : entity work.plru
333 acc_en => plru_acc_en,
337 process(req_index, req_is_hit, req_hit_way, req_is_hit, plru_out)
340 if req_is_hit = '1' and req_index = i then
341 plru_acc_en <= req_is_hit;
345 plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way, WAY_BITS));
346 plru_victim(i) <= plru_out;
351 -- Cache hit detection, output to fetch2 and other misc logic
352 icache_comb : process(all)
353 variable is_hit : std_ulogic;
354 variable hit_way : way_t;
356 -- Extract line, row and tag from request
357 req_index <= get_index(i_in.nia);
358 req_row <= get_row(i_in.nia);
359 req_tag <= get_tag(i_in.nia);
361 -- Test if pending request is a hit on any way
365 if i_in.req = '1' and cache_valids(req_index)(i) = '1' then
366 if read_tag(i, cache_tags(req_index)) = req_tag then
373 -- Generate the "hit" and "miss" signals for the synchronous blocks
374 req_is_hit <= i_in.req and is_hit and not flush_in;
375 req_is_miss <= i_in.req and not is_hit and not flush_in;
376 req_hit_way <= hit_way;
378 -- The way to replace on a miss
379 replace_way <= to_integer(unsigned(plru_victim(req_index)));
381 -- Output instruction from current cache row
383 -- Note: This is a mild violation of our design principle of having pipeline
384 -- stages output from a clean latch. In this case we output the result
385 -- of a mux. The alternative would be output an entire row which
386 -- I prefer not to do just yet as it would force fetch2 to know about
387 -- some of the cache geometry information.
389 i_out.insn <= read_insn_word(r.hit_nia, cache_out(r.hit_way));
390 i_out.valid <= r.hit_valid;
391 i_out.nia <= r.hit_nia;
392 i_out.stop_mark <= r.hit_smark;
394 -- Stall fetch1 if we have a miss
395 stall_out <= not is_hit;
397 -- Wishbone requests output (from the cache miss reload machine)
398 wishbone_out <= r.wb;
401 -- Cache hit synchronous machine
402 icache_hit : process(clk)
404 if rising_edge(clk) then
405 -- On a hit, latch the request for the next cycle, when the BRAM data
406 -- will be available on the cache_out output of the corresponding way
408 if req_is_hit = '1' then
409 r.hit_way <= req_hit_way;
410 r.hit_nia <= i_in.nia;
411 r.hit_smark <= i_in.stop_mark;
414 report "cache hit nia:" & to_hstring(i_in.nia) &
415 " SM:" & std_ulogic'image(i_in.stop_mark) &
416 " idx:" & integer'image(req_index) &
417 " tag:" & to_hstring(req_tag) &
418 " way: " & integer'image(req_hit_way);
422 -- Send stop marks down regardless of validity
423 r.hit_smark <= i_in.stop_mark;
428 -- Cache miss/reload synchronous machine
429 icache_miss : process(clk)
430 variable tagset : cache_tags_set_t;
432 if rising_edge(clk) then
433 -- On reset, clear all valid bits to force misses
435 for i in index_t loop
436 cache_valids(i) <= (others => '0');
442 -- We only ever do reads on wishbone
443 r.wb.dat <= (others => '0');
444 r.wb.sel <= "11111111";
447 -- Not useful normally but helps avoiding tons of sim warnings
448 r.wb.adr <= (others => '0');
450 -- Main state machine
453 -- We need to read a cache line
454 if req_is_miss = '1' then
455 report "cache miss nia:" & to_hstring(i_in.nia) &
456 " SM:" & std_ulogic'image(i_in.stop_mark) &
457 " idx:" & integer'image(req_index) &
458 " way:" & integer'image(replace_way) &
459 " tag:" & to_hstring(req_tag);
461 -- Force misses on that way while reloading that line
462 cache_valids(req_index)(replace_way) <= '0';
464 -- Store new tag in selected way
465 for i in 0 to NUM_WAYS-1 loop
466 if i = replace_way then
467 tagset := cache_tags(req_index);
468 write_tag(i, tagset, req_tag);
469 cache_tags(req_index) <= tagset;
473 -- Keep track of our index and way for subsequent stores
474 r.store_index <= req_index;
475 r.store_way <= replace_way;
477 -- Prep for first wishbone read. We calculate the address of
478 -- the start of the cache line
480 r.wb.adr <= i_in.nia(r.wb.adr'left downto LINE_OFF_BITS) &
481 (LINE_OFF_BITS-1 downto 0 => '0');
488 if wishbone_in.ack = '1' then
489 -- That was the last word ? We are done
490 if is_last_row(r.wb.adr) then
491 cache_valids(r.store_index)(r.store_way) <= '1';
496 -- Otherwise, calculate the next row address
497 r.wb.adr <= next_row_addr(r.wb.adr);