2 -- Set associative icache
4 -- TODO (in no specific order):
6 -- * Add debug interface to inspect cache content
7 -- * Add snoop/invalidate path
8 -- * Add multi-hit error detection
9 -- * Pipelined bus interface (wb or axi)
10 -- * Maybe add parity ? There's a few bits free in each BRAM row on Xilinx
11 -- * Add optimization: service hits on partially loaded lines
12 -- * Add optimization: (maybe) interrupt reload on fluch/redirect
13 -- * Check if playing with the geometry of the cache tags allow for more
14 -- efficient use of distributed RAM and less logic/muxes. Currently we
15 -- write TAG_BITS width which may not match full ram blocks and might
16 -- cause muxes to be inferred for "partial writes".
17 -- * Check if making the read size of PLRU a ROM helps utilization
20 use ieee.std_logic_1164.all;
21 use ieee.numeric_std.all;
26 use work.wishbone_types.all;
28 -- 64 bit direct mapped icache. All instructions are 4B aligned.
32 SIM : boolean := false;
34 LINE_SIZE : positive := 64;
35 -- Number of lines in a set
36 NUM_LINES : positive := 32;
38 NUM_WAYS : positive := 4;
39 -- L1 ITLB number of entries (direct mapped)
40 TLB_SIZE : positive := 64;
41 -- L1 ITLB log_2(page_size)
42 TLB_LG_PGSZ : positive := 12;
43 -- Number of real address bits that we store
44 REAL_ADDR_BITS : positive := 56
50 i_in : in Fetch1ToIcacheType;
51 i_out : out IcacheToDecode1Type;
53 m_in : in MmuToIcacheType;
55 stall_in : in std_ulogic;
56 stall_out : out std_ulogic;
57 flush_in : in std_ulogic;
58 inval_in : in std_ulogic;
60 wishbone_out : out wishbone_master_out;
61 wishbone_in : in wishbone_slave_out;
63 log_out : out std_ulogic_vector(53 downto 0)
67 architecture rtl of icache is
68 -- BRAM organisation: We never access more than wishbone_data_bits at
69 -- a time so to save resources we make the array only that wide, and
70 -- use consecutive indices for to make a cache "line"
72 -- ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
73 constant ROW_SIZE : natural := wishbone_data_bits / 8;
74 -- ROW_PER_LINE is the number of row (wishbone transactions) in a line
75 constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
76 -- BRAM_ROWS is the number of rows in BRAM needed to represent the full
78 constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
79 -- INSN_PER_ROW is the number of 32bit instructions per BRAM row
80 constant INSN_PER_ROW : natural := wishbone_data_bits / 32;
81 -- Bit fields counts in the address
83 -- INSN_BITS is the number of bits to select an instruction in a row
84 constant INSN_BITS : natural := log2(INSN_PER_ROW);
85 -- ROW_BITS is the number of bits to select a row
86 constant ROW_BITS : natural := log2(BRAM_ROWS);
87 -- ROW_LINEBITS is the number of bits to select a row within a line
88 constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
89 -- LINE_OFF_BITS is the number of bits for the offset in a cache line
90 constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
91 -- ROW_OFF_BITS is the number of bits for the offset in a row
92 constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
93 -- INDEX_BITS is the number of bits to select a cache line
94 constant INDEX_BITS : natural := log2(NUM_LINES);
95 -- SET_SIZE_BITS is the log base 2 of the set size
96 constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS;
97 -- TAG_BITS is the number of bits of the tag part of the address
98 constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
99 -- WAY_BITS is the number of bits to select a way
100 constant WAY_BITS : natural := log2(NUM_WAYS);
102 -- Example of layout for 32 lines of 64 bytes:
104 -- .. tag |index| line |
106 -- .. | | | |00| zero (2)
107 -- .. | | |-| | INSN_BITS (1)
108 -- .. | |---| | ROW_LINEBITS (3)
109 -- .. | |--- - --| LINE_OFF_BITS (6)
110 -- .. | |- --| ROW_OFF_BITS (3)
111 -- .. |----- ---| | ROW_BITS (8)
112 -- .. |-----| | INDEX_BITS (5)
113 -- .. --------| | TAG_BITS (53)
115 subtype row_t is integer range 0 to BRAM_ROWS-1;
116 subtype index_t is integer range 0 to NUM_LINES-1;
117 subtype way_t is integer range 0 to NUM_WAYS-1;
118 subtype row_in_line_t is unsigned(ROW_LINEBITS-1 downto 0);
120 -- The cache data BRAM organized as described above for each way
121 subtype cache_row_t is std_ulogic_vector(wishbone_data_bits-1 downto 0);
123 -- The cache tags LUTRAM has a row per set. Vivado is a pain and will
124 -- not handle a clean (commented) definition of the cache tags as a 3d
125 -- memory. For now, work around it by putting all the tags
126 subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
127 -- type cache_tags_set_t is array(way_t) of cache_tag_t;
128 -- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
129 constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
130 subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
131 type cache_tags_array_t is array(index_t) of cache_tags_set_t;
133 -- The cache valid bits
134 subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
135 type cache_valids_t is array(index_t) of cache_way_valids_t;
136 type row_per_line_valid_t is array(0 to ROW_PER_LINE - 1) of std_ulogic;
138 -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
139 signal cache_tags : cache_tags_array_t;
140 signal cache_valids : cache_valids_t;
142 attribute ram_style : string;
143 attribute ram_style of cache_tags : signal is "distributed";
146 constant TLB_BITS : natural := log2(TLB_SIZE);
147 constant TLB_EA_TAG_BITS : natural := 64 - (TLB_LG_PGSZ + TLB_BITS);
148 constant TLB_PTE_BITS : natural := 64;
150 subtype tlb_index_t is integer range 0 to TLB_SIZE - 1;
151 type tlb_valids_t is array(tlb_index_t) of std_ulogic;
152 subtype tlb_tag_t is std_ulogic_vector(TLB_EA_TAG_BITS - 1 downto 0);
153 type tlb_tags_t is array(tlb_index_t) of tlb_tag_t;
154 subtype tlb_pte_t is std_ulogic_vector(TLB_PTE_BITS - 1 downto 0);
155 type tlb_ptes_t is array(tlb_index_t) of tlb_pte_t;
157 signal itlb_valids : tlb_valids_t;
158 signal itlb_tags : tlb_tags_t;
159 signal itlb_ptes : tlb_ptes_t;
160 attribute ram_style of itlb_tags : signal is "distributed";
161 attribute ram_style of itlb_ptes : signal is "distributed";
163 -- Privilege bit from PTE EAA field
164 signal eaa_priv : std_ulogic;
166 -- Cache reload state machine
167 type state_t is (IDLE, CLR_TAG, WAIT_ACK);
169 type reg_internal_t is record
170 -- Cache hit state (Latches for 1 cycle BRAM access)
172 hit_nia : std_ulogic_vector(63 downto 0);
173 hit_smark : std_ulogic;
174 hit_valid : std_ulogic;
176 -- Cache miss state (reload state machine)
178 wb : wishbone_master_out;
180 store_index : index_t;
182 store_tag : cache_tag_t;
183 store_valid : std_ulogic;
184 end_row_ix : row_in_line_t;
185 rows_valid : row_per_line_valid_t;
188 fetch_failed : std_ulogic;
191 signal r : reg_internal_t;
193 -- Async signals on incoming request
194 signal req_index : index_t;
195 signal req_row : row_t;
196 signal req_hit_way : way_t;
197 signal req_tag : cache_tag_t;
198 signal req_is_hit : std_ulogic;
199 signal req_is_miss : std_ulogic;
200 signal req_laddr : std_ulogic_vector(63 downto 0);
202 signal tlb_req_index : tlb_index_t;
203 signal real_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
204 signal ra_valid : std_ulogic;
205 signal priv_fault : std_ulogic;
206 signal access_ok : std_ulogic;
207 signal use_previous : std_ulogic;
209 -- Output data to logger
210 signal log_data : std_ulogic_vector(53 downto 0);
212 -- Cache RAM interface
213 type cache_ram_out_t is array(way_t) of cache_row_t;
214 signal cache_out : cache_ram_out_t;
216 -- PLRU output interface
217 type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
218 signal plru_victim : plru_out_t;
219 signal replace_way : way_t;
221 -- Return the cache line index (tag index) for an address
222 function get_index(addr: std_ulogic_vector(63 downto 0)) return index_t is
224 return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS)));
227 -- Return the cache row index (data memory) for an address
228 function get_row(addr: std_ulogic_vector(63 downto 0)) return row_t is
230 return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS)));
233 -- Return the index of a row within a line
234 function get_row_of_line(row: row_t) return row_in_line_t is
235 variable row_v : unsigned(ROW_BITS-1 downto 0);
237 row_v := to_unsigned(row, ROW_BITS);
238 return row_v(ROW_LINEBITS-1 downto 0);
241 -- Returns whether this is the last row of a line
242 function is_last_row_addr(addr: wishbone_addr_type; last: row_in_line_t) return boolean is
244 return unsigned(addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS)) = last;
247 -- Returns whether this is the last row of a line
248 function is_last_row(row: row_t; last: row_in_line_t) return boolean is
250 return get_row_of_line(row) = last;
253 -- Return the address of the next row in the current cache line
254 function next_row_addr(addr: wishbone_addr_type)
255 return std_ulogic_vector is
256 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
257 variable result : wishbone_addr_type;
259 -- Is there no simpler way in VHDL to generate that 3 bits adder ?
260 row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
261 row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
263 result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
267 -- Return the next row in the current cache line. We use a dedicated
268 -- function in order to limit the size of the generated adder to be
269 -- only the bits within a cache line (3 bits with default settings)
271 function next_row(row: row_t) return row_t is
272 variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
273 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
274 variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
276 row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
277 row_idx := row_v(ROW_LINEBITS-1 downto 0);
278 row_v(ROW_LINEBITS-1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
279 return to_integer(unsigned(row_v));
282 -- Read the instruction word for the given address in the current cache row
283 function read_insn_word(addr: std_ulogic_vector(63 downto 0);
284 data: cache_row_t) return std_ulogic_vector is
285 variable word: integer range 0 to INSN_PER_ROW-1;
287 word := to_integer(unsigned(addr(INSN_BITS+2-1 downto 2)));
288 return data(31+word*32 downto word*32);
291 -- Get the tag value from the address
292 function get_tag(addr: std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0)) return cache_tag_t is
294 return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
297 -- Read a tag from a tag memory row
298 function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
300 return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
303 -- Write a tag to tag memory row
304 procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t;
307 tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
310 -- Simple hash for direct-mapped TLB index
311 function hash_ea(addr: std_ulogic_vector(63 downto 0)) return tlb_index_t is
312 variable hash : std_ulogic_vector(TLB_BITS - 1 downto 0);
314 hash := addr(TLB_LG_PGSZ + TLB_BITS - 1 downto TLB_LG_PGSZ)
315 xor addr(TLB_LG_PGSZ + 2 * TLB_BITS - 1 downto TLB_LG_PGSZ + TLB_BITS)
316 xor addr(TLB_LG_PGSZ + 3 * TLB_BITS - 1 downto TLB_LG_PGSZ + 2 * TLB_BITS);
317 return to_integer(unsigned(hash));
321 assert LINE_SIZE mod ROW_SIZE = 0;
322 assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE;
323 assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE;
324 assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
325 assert ispow2(INSN_PER_ROW) report "INSN_PER_ROW not power of 2" severity FAILURE;
326 assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
327 report "geometry bits don't add up" severity FAILURE;
328 assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
329 report "geometry bits don't add up" severity FAILURE;
330 assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
331 report "geometry bits don't add up" severity FAILURE;
332 assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
333 report "geometry bits don't add up" severity FAILURE;
335 sim_debug: if SIM generate
338 report "ROW_SIZE = " & natural'image(ROW_SIZE);
339 report "ROW_PER_LINE = " & natural'image(ROW_PER_LINE);
340 report "BRAM_ROWS = " & natural'image(BRAM_ROWS);
341 report "INSN_PER_ROW = " & natural'image(INSN_PER_ROW);
342 report "INSN_BITS = " & natural'image(INSN_BITS);
343 report "ROW_BITS = " & natural'image(ROW_BITS);
344 report "ROW_LINEBITS = " & natural'image(ROW_LINEBITS);
345 report "LINE_OFF_BITS = " & natural'image(LINE_OFF_BITS);
346 report "ROW_OFF_BITS = " & natural'image(ROW_OFF_BITS);
347 report "INDEX_BITS = " & natural'image(INDEX_BITS);
348 report "TAG_BITS = " & natural'image(TAG_BITS);
349 report "WAY_BITS = " & natural'image(WAY_BITS);
354 -- Generate a cache RAM for each way
355 rams: for i in 0 to NUM_WAYS-1 generate
356 signal do_read : std_ulogic;
357 signal do_write : std_ulogic;
358 signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
359 signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
360 signal dout : cache_row_t;
361 signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
363 way: entity work.cache_ram
365 ROW_BITS => ROW_BITS,
366 WIDTH => wishbone_data_bits
375 wr_data => wishbone_in.dat
379 do_read <= not (stall_in or use_previous);
381 if wishbone_in.ack = '1' and r.store_way = i then
384 cache_out(i) <= dout;
385 rd_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
386 wr_addr <= std_ulogic_vector(to_unsigned(r.store_row, ROW_BITS));
387 for i in 0 to ROW_SIZE-1 loop
388 wr_sel(i) <= do_write;
394 maybe_plrus: if NUM_WAYS > 1 generate
396 plrus: for i in 0 to NUM_LINES-1 generate
398 signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
399 signal plru_acc_en : std_ulogic;
400 signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
403 plru : entity work.plru
411 acc_en => plru_acc_en,
415 process(req_index, req_is_hit, req_hit_way, req_is_hit, plru_out)
418 if req_is_hit = '1' and req_index = i then
419 plru_acc_en <= req_is_hit;
423 plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way, WAY_BITS));
424 plru_victim(i) <= plru_out;
429 -- TLB hit detection and real address generation
430 itlb_lookup : process(all)
431 variable pte : tlb_pte_t;
432 variable ttag : tlb_tag_t;
434 tlb_req_index <= hash_ea(i_in.nia);
435 pte := itlb_ptes(tlb_req_index);
436 ttag := itlb_tags(tlb_req_index);
437 if i_in.virt_mode = '1' then
438 real_addr <= pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
439 i_in.nia(TLB_LG_PGSZ - 1 downto 0);
440 if ttag = i_in.nia(63 downto TLB_LG_PGSZ + TLB_BITS) then
441 ra_valid <= itlb_valids(tlb_req_index);
447 real_addr <= i_in.nia(REAL_ADDR_BITS - 1 downto 0);
452 -- no IAMR, so no KUEP support for now
453 priv_fault <= eaa_priv and not i_in.priv_mode;
454 access_ok <= ra_valid and not priv_fault;
458 itlb_update: process(clk)
459 variable wr_index : tlb_index_t;
461 if rising_edge(clk) then
462 wr_index := hash_ea(m_in.addr);
463 if rst = '1' or (m_in.tlbie = '1' and m_in.doall = '1') then
464 -- clear all valid bits
465 for i in tlb_index_t loop
466 itlb_valids(i) <= '0';
468 elsif m_in.tlbie = '1' then
469 -- clear entry regardless of hit or miss
470 itlb_valids(wr_index) <= '0';
471 elsif m_in.tlbld = '1' then
472 itlb_tags(wr_index) <= m_in.addr(63 downto TLB_LG_PGSZ + TLB_BITS);
473 itlb_ptes(wr_index) <= m_in.pte;
474 itlb_valids(wr_index) <= '1';
479 -- Cache hit detection, output to fetch2 and other misc logic
480 icache_comb : process(all)
481 variable is_hit : std_ulogic;
482 variable hit_way : way_t;
484 -- i_in.sequential means that i_in.nia this cycle is 4 more than
485 -- last cycle. If we read more than 32 bits at a time, had a cache hit
486 -- last cycle, and we don't want the first 32-bit chunk, then we can
487 -- keep the data we read last cycle and just use that.
488 if unsigned(i_in.nia(INSN_BITS+2-1 downto 2)) /= 0 then
489 use_previous <= i_in.sequential and r.hit_valid;
494 -- Extract line, row and tag from request
495 req_index <= get_index(i_in.nia);
496 req_row <= get_row(i_in.nia);
497 req_tag <= get_tag(real_addr);
499 -- Calculate address of beginning of cache row, will be
500 -- used for cache miss processing if needed
502 req_laddr <= (63 downto REAL_ADDR_BITS => '0') &
503 real_addr(REAL_ADDR_BITS - 1 downto ROW_OFF_BITS) &
504 (ROW_OFF_BITS-1 downto 0 => '0');
506 -- Test if pending request is a hit on any way
510 if i_in.req = '1' and
511 (cache_valids(req_index)(i) = '1' or
512 (r.state = WAIT_ACK and
513 req_index = r.store_index and
515 r.rows_valid(req_row mod ROW_PER_LINE) = '1')) then
516 if read_tag(i, cache_tags(req_index)) = req_tag then
523 -- Generate the "hit" and "miss" signals for the synchronous blocks
524 if i_in.req = '1' and access_ok = '1' and flush_in = '0' and rst = '0' then
525 req_is_hit <= is_hit;
526 req_is_miss <= not is_hit;
531 req_hit_way <= hit_way;
533 -- The way to replace on a miss
534 replace_way <= to_integer(unsigned(plru_victim(req_index)));
536 -- Output instruction from current cache row
538 -- Note: This is a mild violation of our design principle of having pipeline
539 -- stages output from a clean latch. In this case we output the result
540 -- of a mux. The alternative would be output an entire row which
541 -- I prefer not to do just yet as it would force fetch2 to know about
542 -- some of the cache geometry information.
544 i_out.insn <= read_insn_word(r.hit_nia, cache_out(r.hit_way));
545 i_out.valid <= r.hit_valid;
546 i_out.nia <= r.hit_nia;
547 i_out.stop_mark <= r.hit_smark;
548 i_out.fetch_failed <= r.fetch_failed;
550 -- Stall fetch1 if we have a miss on cache or TLB or a protection fault
551 stall_out <= not (is_hit and access_ok);
553 -- Wishbone requests output (from the cache miss reload machine)
554 wishbone_out <= r.wb;
557 -- Cache hit synchronous machine
558 icache_hit : process(clk)
560 if rising_edge(clk) then
561 -- keep outputs to fetch2 unchanged on a stall
562 -- except that flush or reset sets valid to 0
563 -- If use_previous, keep the same data as last cycle and use the second half
564 if stall_in = '1' or use_previous = '1' then
565 if rst = '1' or flush_in = '1' then
569 -- On a hit, latch the request for the next cycle, when the BRAM data
570 -- will be available on the cache_out output of the corresponding way
572 r.hit_valid <= req_is_hit;
573 if req_is_hit = '1' then
574 r.hit_way <= req_hit_way;
576 report "cache hit nia:" & to_hstring(i_in.nia) &
577 " IR:" & std_ulogic'image(i_in.virt_mode) &
578 " SM:" & std_ulogic'image(i_in.stop_mark) &
579 " idx:" & integer'image(req_index) &
580 " tag:" & to_hstring(req_tag) &
581 " way:" & integer'image(req_hit_way) &
582 " RA:" & to_hstring(real_addr);
585 if stall_in = '0' then
586 -- Send stop marks and NIA down regardless of validity
587 r.hit_smark <= i_in.stop_mark;
588 r.hit_nia <= i_in.nia;
593 -- Cache miss/reload synchronous machine
594 icache_miss : process(clk)
595 variable tagset : cache_tags_set_t;
596 variable stbs_done : boolean;
598 if rising_edge(clk) then
599 -- On reset, clear all valid bits to force misses
601 for i in index_t loop
602 cache_valids(i) <= (others => '0');
608 -- We only ever do reads on wishbone
609 r.wb.dat <= (others => '0');
610 r.wb.sel <= "11111111";
613 -- Not useful normally but helps avoiding tons of sim warnings
614 r.wb.adr <= (others => '0');
616 -- Process cache invalidations
617 if inval_in = '1' then
618 for i in index_t loop
619 cache_valids(i) <= (others => '0');
621 r.store_valid <= '0';
624 -- Main state machine
627 -- Reset per-row valid flags, only used in WAIT_ACK
628 for i in 0 to ROW_PER_LINE - 1 loop
629 r.rows_valid(i) <= '0';
632 -- We need to read a cache line
633 if req_is_miss = '1' then
634 report "cache miss nia:" & to_hstring(i_in.nia) &
635 " IR:" & std_ulogic'image(i_in.virt_mode) &
636 " SM:" & std_ulogic'image(i_in.stop_mark) &
637 " idx:" & integer'image(req_index) &
638 " way:" & integer'image(replace_way) &
639 " tag:" & to_hstring(req_tag) &
640 " RA:" & to_hstring(real_addr);
642 -- Keep track of our index and way for subsequent stores
643 r.store_index <= req_index;
644 r.store_way <= replace_way;
645 r.store_row <= get_row(req_laddr);
646 r.store_tag <= req_tag;
647 r.store_valid <= '1';
648 r.end_row_ix <= get_row_of_line(get_row(req_laddr)) - 1;
650 -- Prep for first wishbone read. We calculate the address of
651 -- the start of the cache line and start the WB cycle.
653 r.wb.adr <= req_laddr(r.wb.adr'left downto 0);
657 -- Track that we had one request sent
661 when CLR_TAG | WAIT_ACK =>
662 if r.state = CLR_TAG then
663 -- Force misses on that way while reloading that line
664 cache_valids(req_index)(r.store_way) <= '0';
666 -- Store new tag in selected way
667 for i in 0 to NUM_WAYS-1 loop
668 if i = r.store_way then
669 tagset := cache_tags(r.store_index);
670 write_tag(i, tagset, r.store_tag);
671 cache_tags(r.store_index) <= tagset;
677 -- Requests are all sent if stb is 0
678 stbs_done := r.wb.stb = '0';
680 -- If we are still sending requests, was one accepted ?
681 if wishbone_in.stall = '0' and not stbs_done then
682 -- That was the last word ? We are done sending. Clear
683 -- stb and set stbs_done so we can handle an eventual last
684 -- ack on the same cycle.
686 if is_last_row_addr(r.wb.adr, r.end_row_ix) then
691 -- Calculate the next row address
692 r.wb.adr <= next_row_addr(r.wb.adr);
695 -- Incoming acks processing
696 if wishbone_in.ack = '1' then
697 r.rows_valid(r.store_row mod ROW_PER_LINE) <= '1';
698 -- Check for completion
699 if stbs_done and is_last_row(r.store_row, r.end_row_ix) then
700 -- Complete wishbone cycle
703 -- Cache line is now valid
704 cache_valids(r.store_index)(r.store_way) <= r.store_valid and not inval_in;
710 -- Increment store row counter
711 r.store_row <= next_row(r.store_row);
716 -- TLB miss and protection fault processing
717 if rst = '1' or flush_in = '1' or m_in.tlbld = '1' then
718 r.fetch_failed <= '0';
719 elsif i_in.req = '1' and access_ok = '0' and stall_in = '0' then
720 r.fetch_failed <= '1';
725 data_log: process(clk)
726 variable lway: way_t;
727 variable wstate: std_ulogic;
729 if rising_edge(clk) then
736 if r.state /= IDLE then
739 log_data <= i_out.valid &
742 r.wb.adr(5 downto 3) &
743 r.wb.stb & r.wb.cyc &
747 r.hit_nia(5 downto 2) &
749 std_ulogic_vector(to_unsigned(lway, 3)) &
750 req_is_hit & req_is_miss &