2 -- Set associative icache
4 -- TODO (in no specific order):
6 -- * Add debug interface to inspect cache content
7 -- * Add snoop/invalidate path
8 -- * Add multi-hit error detection
9 -- * Pipelined bus interface (wb or axi)
10 -- * Maybe add parity ? There's a few bits free in each BRAM row on Xilinx
11 -- * Add optimization: service hits on partially loaded lines
12 -- * Add optimization: (maybe) interrupt reload on fluch/redirect
13 -- * Check if playing with the geometry of the cache tags allow for more
14 -- efficient use of distributed RAM and less logic/muxes. Currently we
15 -- write TAG_BITS width which may not match full ram blocks and might
16 -- cause muxes to be inferred for "partial writes".
17 -- * Check if making the read size of PLRU a ROM helps utilization
20 use ieee.std_logic_1164.all;
21 use ieee.numeric_std.all;
26 use work.wishbone_types.all;
28 -- 64 bit direct mapped icache. All instructions are 4B aligned.
32 SIM : boolean := false;
34 LINE_SIZE : positive := 64;
35 -- Number of lines in a set
36 NUM_LINES : positive := 32;
38 NUM_WAYS : positive := 4;
39 -- L1 ITLB number of entries (direct mapped)
40 TLB_SIZE : positive := 64;
41 -- L1 ITLB log_2(page_size)
42 TLB_LG_PGSZ : positive := 12;
43 -- Number of real address bits that we store
44 REAL_ADDR_BITS : positive := 56
50 i_in : in Fetch1ToIcacheType;
51 i_out : out IcacheToFetch2Type;
53 m_in : in MmuToIcacheType;
55 stall_out : out std_ulogic;
56 flush_in : in std_ulogic;
57 inval_in : in std_ulogic;
59 wishbone_out : out wishbone_master_out;
60 wishbone_in : in wishbone_slave_out
64 architecture rtl of icache is
65 -- BRAM organisation: We never access more than wishbone_data_bits at
66 -- a time so to save resources we make the array only that wide, and
67 -- use consecutive indices for to make a cache "line"
69 -- ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
70 constant ROW_SIZE : natural := wishbone_data_bits / 8;
71 -- ROW_PER_LINE is the number of row (wishbone transactions) in a line
72 constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
73 -- BRAM_ROWS is the number of rows in BRAM needed to represent the full
75 constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
76 -- INSN_PER_ROW is the number of 32bit instructions per BRAM row
77 constant INSN_PER_ROW : natural := wishbone_data_bits / 32;
78 -- Bit fields counts in the address
80 -- INSN_BITS is the number of bits to select an instruction in a row
81 constant INSN_BITS : natural := log2(INSN_PER_ROW);
82 -- ROW_BITS is the number of bits to select a row
83 constant ROW_BITS : natural := log2(BRAM_ROWS);
84 -- ROW_LINEBITS is the number of bits to select a row within a line
85 constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
86 -- LINE_OFF_BITS is the number of bits for the offset in a cache line
87 constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
88 -- ROW_OFF_BITS is the number of bits for the offset in a row
89 constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
90 -- INDEX_BITS is the number of bits to select a cache line
91 constant INDEX_BITS : natural := log2(NUM_LINES);
92 -- SET_SIZE_BITS is the log base 2 of the set size
93 constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS;
94 -- TAG_BITS is the number of bits of the tag part of the address
95 constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
96 -- WAY_BITS is the number of bits to select a way
97 constant WAY_BITS : natural := log2(NUM_WAYS);
99 -- Example of layout for 32 lines of 64 bytes:
101 -- .. tag |index| line |
103 -- .. | | | |00| zero (2)
104 -- .. | | |-| | INSN_BITS (1)
105 -- .. | |---| | ROW_LINEBITS (3)
106 -- .. | |--- - --| LINE_OFF_BITS (6)
107 -- .. | |- --| ROW_OFF_BITS (3)
108 -- .. |----- ---| | ROW_BITS (8)
109 -- .. |-----| | INDEX_BITS (5)
110 -- .. --------| | TAG_BITS (53)
112 subtype row_t is integer range 0 to BRAM_ROWS-1;
113 subtype index_t is integer range 0 to NUM_LINES-1;
114 subtype way_t is integer range 0 to NUM_WAYS-1;
116 -- The cache data BRAM organized as described above for each way
117 subtype cache_row_t is std_ulogic_vector(wishbone_data_bits-1 downto 0);
119 -- The cache tags LUTRAM has a row per set. Vivado is a pain and will
120 -- not handle a clean (commented) definition of the cache tags as a 3d
121 -- memory. For now, work around it by putting all the tags
122 subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
123 -- type cache_tags_set_t is array(way_t) of cache_tag_t;
124 -- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
125 constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
126 subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
127 type cache_tags_array_t is array(index_t) of cache_tags_set_t;
129 -- The cache valid bits
130 subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
131 type cache_valids_t is array(index_t) of cache_way_valids_t;
133 -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
134 signal cache_tags : cache_tags_array_t;
135 signal cache_valids : cache_valids_t;
137 attribute ram_style : string;
138 attribute ram_style of cache_tags : signal is "distributed";
141 constant TLB_BITS : natural := log2(TLB_SIZE);
142 constant TLB_EA_TAG_BITS : natural := 64 - (TLB_LG_PGSZ + TLB_BITS);
143 constant TLB_PTE_BITS : natural := 64;
145 subtype tlb_index_t is integer range 0 to TLB_SIZE - 1;
146 type tlb_valids_t is array(tlb_index_t) of std_ulogic;
147 subtype tlb_tag_t is std_ulogic_vector(TLB_EA_TAG_BITS - 1 downto 0);
148 type tlb_tags_t is array(tlb_index_t) of tlb_tag_t;
149 subtype tlb_pte_t is std_ulogic_vector(TLB_PTE_BITS - 1 downto 0);
150 type tlb_ptes_t is array(tlb_index_t) of tlb_pte_t;
152 signal itlb_valids : tlb_valids_t;
153 signal itlb_tags : tlb_tags_t;
154 signal itlb_ptes : tlb_ptes_t;
155 attribute ram_style of itlb_tags : signal is "distributed";
156 attribute ram_style of itlb_ptes : signal is "distributed";
158 -- Privilege bit from PTE EAA field
159 signal eaa_priv : std_ulogic;
161 -- Cache reload state machine
162 type state_t is (IDLE, WAIT_ACK);
164 type reg_internal_t is record
165 -- Cache hit state (Latches for 1 cycle BRAM access)
167 hit_nia : std_ulogic_vector(63 downto 0);
168 hit_smark : std_ulogic;
169 hit_valid : std_ulogic;
171 -- Cache miss state (reload state machine)
173 wb : wishbone_master_out;
175 store_index : index_t;
177 store_valid : std_ulogic;
180 fetch_failed : std_ulogic;
183 signal r : reg_internal_t;
185 -- Async signals on incoming request
186 signal req_index : index_t;
187 signal req_row : row_t;
188 signal req_hit_way : way_t;
189 signal req_tag : cache_tag_t;
190 signal req_is_hit : std_ulogic;
191 signal req_is_miss : std_ulogic;
192 signal req_laddr : std_ulogic_vector(63 downto 0);
194 signal tlb_req_index : tlb_index_t;
195 signal real_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
196 signal ra_valid : std_ulogic;
197 signal priv_fault : std_ulogic;
198 signal access_ok : std_ulogic;
200 -- Cache RAM interface
201 type cache_ram_out_t is array(way_t) of cache_row_t;
202 signal cache_out : cache_ram_out_t;
204 -- PLRU output interface
205 type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
206 signal plru_victim : plru_out_t;
207 signal replace_way : way_t;
209 -- Return the cache line index (tag index) for an address
210 function get_index(addr: std_ulogic_vector(63 downto 0)) return index_t is
212 return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS)));
215 -- Return the cache row index (data memory) for an address
216 function get_row(addr: std_ulogic_vector(63 downto 0)) return row_t is
218 return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS)));
221 -- Returns whether this is the last row of a line
222 function is_last_row_addr(addr: wishbone_addr_type) return boolean is
223 constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
225 return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones;
228 -- Returns whether this is the last row of a line
229 function is_last_row(row: row_t) return boolean is
230 variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
231 constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
233 row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
234 return row_v(ROW_LINEBITS-1 downto 0) = ones;
237 -- Return the address of the next row in the current cache line
238 function next_row_addr(addr: wishbone_addr_type)
239 return std_ulogic_vector is
240 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
241 variable result : wishbone_addr_type;
243 -- Is there no simpler way in VHDL to generate that 3 bits adder ?
244 row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
245 row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
247 result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
251 -- Return the next row in the current cache line. We use a dedicated
252 -- function in order to limit the size of the generated adder to be
253 -- only the bits within a cache line (3 bits with default settings)
255 function next_row(row: row_t) return row_t is
256 variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
257 variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
258 variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
260 row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
261 row_idx := row_v(ROW_LINEBITS-1 downto 0);
262 row_v(ROW_LINEBITS-1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1);
263 return to_integer(unsigned(row_v));
266 -- Read the instruction word for the given address in the current cache row
267 function read_insn_word(addr: std_ulogic_vector(63 downto 0);
268 data: cache_row_t) return std_ulogic_vector is
269 variable word: integer range 0 to INSN_PER_ROW-1;
271 word := to_integer(unsigned(addr(INSN_BITS+2-1 downto 2)));
272 return data(31+word*32 downto word*32);
275 -- Get the tag value from the address
276 function get_tag(addr: std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0)) return cache_tag_t is
278 return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
281 -- Read a tag from a tag memory row
282 function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
284 return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
287 -- Write a tag to tag memory row
288 procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t;
291 tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
294 -- Simple hash for direct-mapped TLB index
295 function hash_ea(addr: std_ulogic_vector(63 downto 0)) return tlb_index_t is
296 variable hash : std_ulogic_vector(TLB_BITS - 1 downto 0);
298 hash := addr(TLB_LG_PGSZ + TLB_BITS - 1 downto TLB_LG_PGSZ)
299 xor addr(TLB_LG_PGSZ + 2 * TLB_BITS - 1 downto TLB_LG_PGSZ + TLB_BITS)
300 xor addr(TLB_LG_PGSZ + 3 * TLB_BITS - 1 downto TLB_LG_PGSZ + 2 * TLB_BITS);
301 return to_integer(unsigned(hash));
305 assert LINE_SIZE mod ROW_SIZE = 0;
306 assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE;
307 assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE;
308 assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
309 assert ispow2(INSN_PER_ROW) report "INSN_PER_ROW not power of 2" severity FAILURE;
310 assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
311 report "geometry bits don't add up" severity FAILURE;
312 assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
313 report "geometry bits don't add up" severity FAILURE;
314 assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
315 report "geometry bits don't add up" severity FAILURE;
316 assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
317 report "geometry bits don't add up" severity FAILURE;
319 sim_debug: if SIM generate
322 report "ROW_SIZE = " & natural'image(ROW_SIZE);
323 report "ROW_PER_LINE = " & natural'image(ROW_PER_LINE);
324 report "BRAM_ROWS = " & natural'image(BRAM_ROWS);
325 report "INSN_PER_ROW = " & natural'image(INSN_PER_ROW);
326 report "INSN_BITS = " & natural'image(INSN_BITS);
327 report "ROW_BITS = " & natural'image(ROW_BITS);
328 report "ROW_LINEBITS = " & natural'image(ROW_LINEBITS);
329 report "LINE_OFF_BITS = " & natural'image(LINE_OFF_BITS);
330 report "ROW_OFF_BITS = " & natural'image(ROW_OFF_BITS);
331 report "INDEX_BITS = " & natural'image(INDEX_BITS);
332 report "TAG_BITS = " & natural'image(TAG_BITS);
333 report "WAY_BITS = " & natural'image(WAY_BITS);
338 -- Generate a cache RAM for each way
339 rams: for i in 0 to NUM_WAYS-1 generate
340 signal do_read : std_ulogic;
341 signal do_write : std_ulogic;
342 signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
343 signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
344 signal dout : cache_row_t;
345 signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
347 way: entity work.cache_ram
349 ROW_BITS => ROW_BITS,
350 WIDTH => wishbone_data_bits
359 wr_data => wishbone_in.dat
365 if wishbone_in.ack = '1' and r.store_way = i then
368 cache_out(i) <= dout;
369 rd_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
370 wr_addr <= std_ulogic_vector(to_unsigned(r.store_row, ROW_BITS));
371 for i in 0 to ROW_SIZE-1 loop
372 wr_sel(i) <= do_write;
378 maybe_plrus: if NUM_WAYS > 1 generate
380 plrus: for i in 0 to NUM_LINES-1 generate
382 signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
383 signal plru_acc_en : std_ulogic;
384 signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
387 plru : entity work.plru
395 acc_en => plru_acc_en,
399 process(req_index, req_is_hit, req_hit_way, req_is_hit, plru_out)
402 if req_is_hit = '1' and req_index = i then
403 plru_acc_en <= req_is_hit;
407 plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way, WAY_BITS));
408 plru_victim(i) <= plru_out;
413 -- TLB hit detection and real address generation
414 itlb_lookup : process(all)
415 variable pte : tlb_pte_t;
416 variable ttag : tlb_tag_t;
418 tlb_req_index <= hash_ea(i_in.nia);
419 pte := itlb_ptes(tlb_req_index);
420 ttag := itlb_tags(tlb_req_index);
421 if i_in.virt_mode = '1' then
422 real_addr <= pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
423 i_in.nia(TLB_LG_PGSZ - 1 downto 0);
424 if ttag = i_in.nia(63 downto TLB_LG_PGSZ + TLB_BITS) then
425 ra_valid <= itlb_valids(tlb_req_index);
431 real_addr <= i_in.nia(REAL_ADDR_BITS - 1 downto 0);
436 -- no IAMR, so no KUEP support for now
437 priv_fault <= eaa_priv and not i_in.priv_mode;
438 access_ok <= ra_valid and not priv_fault;
442 itlb_update: process(clk)
443 variable wr_index : tlb_index_t;
445 if rising_edge(clk) then
446 wr_index := hash_ea(m_in.addr);
447 if rst = '1' or (m_in.tlbie = '1' and m_in.doall = '1') then
448 -- clear all valid bits
449 for i in tlb_index_t loop
450 itlb_valids(i) <= '0';
452 elsif m_in.tlbie = '1' then
453 -- clear entry regardless of hit or miss
454 itlb_valids(wr_index) <= '0';
455 elsif m_in.tlbld = '1' then
456 itlb_tags(wr_index) <= m_in.addr(63 downto TLB_LG_PGSZ + TLB_BITS);
457 itlb_ptes(wr_index) <= m_in.pte;
458 itlb_valids(wr_index) <= '1';
463 -- Cache hit detection, output to fetch2 and other misc logic
464 icache_comb : process(all)
465 variable is_hit : std_ulogic;
466 variable hit_way : way_t;
468 -- Extract line, row and tag from request
469 req_index <= get_index(i_in.nia);
470 req_row <= get_row(i_in.nia);
471 req_tag <= get_tag(real_addr);
473 -- Calculate address of beginning of cache line, will be
474 -- used for cache miss processing if needed
476 req_laddr <= (63 downto REAL_ADDR_BITS => '0') &
477 real_addr(REAL_ADDR_BITS - 1 downto LINE_OFF_BITS) &
478 (LINE_OFF_BITS-1 downto 0 => '0');
480 -- Test if pending request is a hit on any way
484 if i_in.req = '1' and cache_valids(req_index)(i) = '1' then
485 if read_tag(i, cache_tags(req_index)) = req_tag then
492 -- Generate the "hit" and "miss" signals for the synchronous blocks
493 if i_in.req = '1' and access_ok = '1' and flush_in = '0' and rst = '0' then
494 req_is_hit <= is_hit;
495 req_is_miss <= not is_hit;
500 req_hit_way <= hit_way;
502 -- The way to replace on a miss
503 replace_way <= to_integer(unsigned(plru_victim(req_index)));
505 -- Output instruction from current cache row
507 -- Note: This is a mild violation of our design principle of having pipeline
508 -- stages output from a clean latch. In this case we output the result
509 -- of a mux. The alternative would be output an entire row which
510 -- I prefer not to do just yet as it would force fetch2 to know about
511 -- some of the cache geometry information.
513 i_out.insn <= read_insn_word(r.hit_nia, cache_out(r.hit_way));
514 i_out.valid <= r.hit_valid;
515 i_out.nia <= r.hit_nia;
516 i_out.stop_mark <= r.hit_smark;
517 i_out.fetch_failed <= r.fetch_failed;
519 -- Stall fetch1 if we have a miss on cache or TLB or a protection fault
520 stall_out <= not (is_hit and access_ok);
522 -- Wishbone requests output (from the cache miss reload machine)
523 wishbone_out <= r.wb;
526 -- Cache hit synchronous machine
527 icache_hit : process(clk)
529 if rising_edge(clk) then
530 -- On a hit, latch the request for the next cycle, when the BRAM data
531 -- will be available on the cache_out output of the corresponding way
533 r.hit_valid <= req_is_hit;
534 -- Send stop marks and NIA down regardless of validity
535 r.hit_smark <= i_in.stop_mark;
536 r.hit_nia <= i_in.nia;
537 if req_is_hit = '1' then
538 r.hit_way <= req_hit_way;
539 r.hit_smark <= i_in.stop_mark;
541 report "cache hit nia:" & to_hstring(i_in.nia) &
542 " IR:" & std_ulogic'image(i_in.virt_mode) &
543 " SM:" & std_ulogic'image(i_in.stop_mark) &
544 " idx:" & integer'image(req_index) &
545 " tag:" & to_hstring(req_tag) &
546 " way:" & integer'image(req_hit_way) &
547 " RA:" & to_hstring(real_addr);
552 -- Cache miss/reload synchronous machine
553 icache_miss : process(clk)
554 variable tagset : cache_tags_set_t;
555 variable stbs_done : boolean;
557 if rising_edge(clk) then
558 -- On reset, clear all valid bits to force misses
560 for i in index_t loop
561 cache_valids(i) <= (others => '0');
567 -- We only ever do reads on wishbone
568 r.wb.dat <= (others => '0');
569 r.wb.sel <= "11111111";
572 -- Not useful normally but helps avoiding tons of sim warnings
573 r.wb.adr <= (others => '0');
575 -- Process cache invalidations
576 if inval_in = '1' then
577 for i in index_t loop
578 cache_valids(i) <= (others => '0');
580 r.store_valid <= '0';
583 -- Main state machine
586 -- We need to read a cache line
587 if req_is_miss = '1' then
588 report "cache miss nia:" & to_hstring(i_in.nia) &
589 " IR:" & std_ulogic'image(i_in.virt_mode) &
590 " SM:" & std_ulogic'image(i_in.stop_mark) &
591 " idx:" & integer'image(req_index) &
592 " way:" & integer'image(replace_way) &
593 " tag:" & to_hstring(req_tag) &
594 " RA:" & to_hstring(real_addr);
596 -- Force misses on that way while reloading that line
597 cache_valids(req_index)(replace_way) <= '0';
599 -- Store new tag in selected way
600 for i in 0 to NUM_WAYS-1 loop
601 if i = replace_way then
602 tagset := cache_tags(req_index);
603 write_tag(i, tagset, req_tag);
604 cache_tags(req_index) <= tagset;
608 -- Keep track of our index and way for subsequent stores
609 r.store_index <= req_index;
610 r.store_way <= replace_way;
611 r.store_row <= get_row(req_laddr);
612 r.store_valid <= '1';
614 -- Prep for first wishbone read. We calculate the address of
615 -- the start of the cache line and start the WB cycle.
617 r.wb.adr <= req_laddr(r.wb.adr'left downto 0);
621 -- Track that we had one request sent
626 -- Requests are all sent if stb is 0
627 stbs_done := r.wb.stb = '0';
629 -- If we are still sending requests, was one accepted ?
630 if wishbone_in.stall = '0' and not stbs_done then
631 -- That was the last word ? We are done sending. Clear
632 -- stb and set stbs_done so we can handle an eventual last
633 -- ack on the same cycle.
635 if is_last_row_addr(r.wb.adr) then
640 -- Calculate the next row address
641 r.wb.adr <= next_row_addr(r.wb.adr);
644 -- Incoming acks processing
645 if wishbone_in.ack = '1' then
646 -- Check for completion
647 if stbs_done and is_last_row(r.store_row) then
648 -- Complete wishbone cycle
651 -- Cache line is now valid
652 cache_valids(r.store_index)(r.store_way) <= r.store_valid and not inval_in;
658 -- Increment store row counter
659 r.store_row <= next_row(r.store_row);
664 -- TLB miss and protection fault processing
665 if rst = '1' or flush_in = '1' or m_in.tlbld = '1' then
666 r.fetch_failed <= '0';
667 elsif i_in.req = '1' and access_ok = '0' then
668 r.fetch_failed <= '1';