icache_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.common.all;
   6 use work.wishbone_types.all;
   7
   8 entity icache_tb is
   9 end icache_tb;
  10
  11 architecture behave of icache_tb is
  12     signal clk          : std_ulogic;
  13     signal rst          : std_ulogic;
  14
  15     signal i_out        : Fetch2ToIcacheType;
  16     signal i_in         : IcacheToFetch2Type;
  17
  18     signal wb_bram_in   : wishbone_master_out;
  19     signal wb_bram_out  : wishbone_slave_out;
  20
  21     constant clk_period : time := 10 ns;
  22 begin
  23     icache0: entity work.icache
  24         generic map(
  25             LINE_SIZE_DW => 8,
  26             NUM_LINES => 4
  27             )
  28         port map(
  29             clk => clk,
  30             rst => rst,
  31             i_in => i_out,
  32             i_out => i_in,
  33             wishbone_out => wb_bram_in,
  34             wishbone_in => wb_bram_out
  35             );
  36
  37     -- BRAM Memory slave
  38     bram0: entity work.mw_soc_memory
  39         generic map(
  40             MEMORY_SIZE   => 128,
  41             RAM_INIT_FILE => "icache_test.bin"
  42             )
  43         port map(
  44             clk => clk,
  45             rst => rst,
  46             wishbone_in => wb_bram_in,
  47             wishbone_out => wb_bram_out
  48             );
  49
  50     clk_process: process
  51     begin
  52         clk <= '0';
  53         wait for clk_period/2;
  54         clk <= '1';
  55         wait for clk_period/2;
  56     end process;
  57
  58     rst_process: process
  59     begin
  60         rst <= '1';
  61         wait for 2*clk_period;
  62         rst <= '0';
  63         wait;
  64     end process;
  65
  66     stim: process
  67     begin
  68         i_out.req <= '0';
  69         i_out.addr <= (others => '0');
  70
  71         wait for 4*clk_period;
  72
  73         i_out.req <= '1';
  74         i_out.addr <= x"0000000000000004";
  75
  76         wait for 30*clk_period;
  77
  78         assert i_in.ack = '1';
  79         assert i_in.insn = x"00000001";
  80
  81         i_out.req <= '0';
  82
  83         wait for clk_period;
  84
  85         -- hit
  86         i_out.req <= '1';
  87         i_out.addr <= x"0000000000000008";
  88         wait for clk_period/2;
  89         assert i_in.ack = '1';
  90         assert i_in.insn = x"00000002";
  91         wait for clk_period/2;
  92
  93         -- another miss
  94         i_out.req <= '1';
  95         i_out.addr <= x"0000000000000040";
  96
  97         wait for 30*clk_period;
  98
  99         assert i_in.ack = '1';
 100         assert i_in.insn = x"00000010";
 101
 102         -- test something that aliases
 103         i_out.req <= '1';
 104         i_out.addr <= x"0000000000000100";
 105         wait for clk_period/2;
 106         assert i_in.ack = '0';
 107         wait for clk_period/2;
 108
 109         wait for 30*clk_period;
 110
 111         assert i_in.ack = '1';
 112         assert i_in.insn = x"00000040";
 113
 114         i_out.req <= '0';
 115
 116         assert false report "end of test" severity failure;
 117         wait;
 118
 119     end process;
 120 end;