icache_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.common.all;
   6 use work.wishbone_types.all;
   7
   8 entity icache_tb is
   9 end icache_tb;
  10
  11 architecture behave of icache_tb is
  12     signal clk          : std_ulogic;
  13     signal rst          : std_ulogic;
  14
  15     signal i_out        : Fetch1ToIcacheType;
  16     signal i_in         : IcacheToFetch2Type;
  17
  18     signal m_out        : MmuToIcacheType;
  19
  20     signal wb_bram_in   : wishbone_master_out;
  21     signal wb_bram_out  : wishbone_slave_out;
  22
  23     constant clk_period : time := 10 ns;
  24 begin
  25     icache0: entity work.icache
  26         generic map(
  27             LINE_SIZE => 64,
  28             NUM_LINES => 4
  29             )
  30         port map(
  31             clk => clk,
  32             rst => rst,
  33             i_in => i_out,
  34             i_out => i_in,
  35             m_in => m_out,
  36             flush_in => '0',
  37             wishbone_out => wb_bram_in,
  38             wishbone_in => wb_bram_out
  39             );
  40
  41     -- BRAM Memory slave
  42     bram0: entity work.wishbone_bram_wrapper
  43         generic map(
  44             MEMORY_SIZE   => 1024,
  45             RAM_INIT_FILE => "icache_test.bin"
  46             )
  47         port map(
  48             clk => clk,
  49             rst => rst,
  50             wishbone_in => wb_bram_in,
  51             wishbone_out => wb_bram_out
  52             );
  53
  54     clk_process: process
  55     begin
  56         clk <= '0';
  57         wait for clk_period/2;
  58         clk <= '1';
  59         wait for clk_period/2;
  60     end process;
  61
  62     rst_process: process
  63     begin
  64         rst <= '1';
  65         wait for 2*clk_period;
  66         rst <= '0';
  67         wait;
  68     end process;
  69
  70     stim: process
  71     begin
  72         i_out.req <= '0';
  73         i_out.nia <= (others => '0');
  74         i_out.stop_mark <= '0';
  75
  76         m_out.tlbld <= '0';
  77         m_out.tlbie <= '0';
  78         m_out.addr <= (others => '0');
  79         m_out.pte <= (others => '0');
  80
  81         wait until rising_edge(clk);
  82         wait until rising_edge(clk);
  83         wait until rising_edge(clk);
  84         wait until rising_edge(clk);
  85
  86         i_out.req <= '1';
  87         i_out.nia <= x"0000000000000004";
  88
  89         wait for 30*clk_period;
  90         wait until rising_edge(clk);
  91
  92         assert i_in.valid = '1' severity failure;
  93         assert i_in.insn = x"00000001"
  94             report "insn @" & to_hstring(i_out.nia) &
  95             "=" & to_hstring(i_in.insn) &
  96             " expected 00000001"
  97             severity failure;
  98
  99         i_out.req <= '0';
 100
 101         wait until rising_edge(clk);
 102
 103         -- hit
 104         i_out.req <= '1';
 105         i_out.nia <= x"0000000000000008";
 106         wait until rising_edge(clk);
 107         wait until rising_edge(clk);
 108         assert i_in.valid = '1' severity failure;
 109         assert i_in.insn = x"00000002"
 110             report "insn @" & to_hstring(i_out.nia) &
 111             "=" & to_hstring(i_in.insn) &
 112             " expected 00000002"
 113             severity failure;
 114         wait until rising_edge(clk);
 115
 116         -- another miss
 117         i_out.req <= '1';
 118         i_out.nia <= x"0000000000000040";
 119
 120         wait for 30*clk_period;
 121         wait until rising_edge(clk);
 122
 123         assert i_in.valid = '1' severity failure;
 124         assert i_in.insn = x"00000010"
 125             report "insn @" & to_hstring(i_out.nia) &
 126             "=" & to_hstring(i_in.insn) &
 127             " expected 00000010"
 128             severity failure;
 129
 130         -- test something that aliases
 131         i_out.req <= '1';
 132         i_out.nia <= x"0000000000000100";
 133         wait until rising_edge(clk);
 134         wait until rising_edge(clk);
 135         assert i_in.valid = '0' severity failure;
 136         wait until rising_edge(clk);
 137
 138         wait for 30*clk_period;
 139         wait until rising_edge(clk);
 140
 141         assert i_in.valid = '1' severity failure;
 142         assert i_in.insn = x"00000040"
 143             report "insn @" & to_hstring(i_out.nia) &
 144             "=" & to_hstring(i_in.insn) &
 145             " expected 00000040"
 146             severity failure;
 147
 148         i_out.req <= '0';
 149
 150         assert false report "end of test" severity failure;
 151         wait;
 152
 153     end process;
 154 end;