icache_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.common.all;
   6 use work.wishbone_types.all;
   7
   8 entity icache_tb is
   9 end icache_tb;
  10
  11 architecture behave of icache_tb is
  12     signal clk          : std_ulogic;
  13     signal rst          : std_ulogic;
  14
  15     signal i_out        : Fetch1ToIcacheType;
  16     signal i_in         : IcacheToFetch2Type;
  17
  18     signal wb_bram_in   : wishbone_master_out;
  19     signal wb_bram_out  : wishbone_slave_out;
  20
  21     constant clk_period : time := 10 ns;
  22 begin
  23     icache0: entity work.icache
  24         generic map(
  25             LINE_SIZE => 64,
  26             NUM_LINES => 4
  27             )
  28         port map(
  29             clk => clk,
  30             rst => rst,
  31             i_in => i_out,
  32             i_out => i_in,
  33             flush_in => '0',
  34             wishbone_out => wb_bram_in,
  35             wishbone_in => wb_bram_out
  36             );
  37
  38     -- BRAM Memory slave
  39     bram0: entity work.mw_soc_memory
  40         generic map(
  41             MEMORY_SIZE   => 128,
  42             RAM_INIT_FILE => "icache_test.bin"
  43             )
  44         port map(
  45             clk => clk,
  46             rst => rst,
  47             wishbone_in => wb_bram_in,
  48             wishbone_out => wb_bram_out
  49             );
  50
  51     clk_process: process
  52     begin
  53         clk <= '0';
  54         wait for clk_period/2;
  55         clk <= '1';
  56         wait for clk_period/2;
  57     end process;
  58
  59     rst_process: process
  60     begin
  61         rst <= '1';
  62         wait for 2*clk_period;
  63         rst <= '0';
  64         wait;
  65     end process;
  66
  67     stim: process
  68     begin
  69         i_out.req <= '0';
  70         i_out.nia <= (others => '0');
  71         i_out.stop_mark <= '0';
  72
  73         wait for 4*clk_period;
  74
  75         i_out.req <= '1';
  76         i_out.nia <= x"0000000000000004";
  77
  78         wait for 30*clk_period;
  79
  80         assert i_in.valid = '1';
  81         assert i_in.insn = x"00000001"
  82             report "insn @" & to_hstring(i_out.nia) &
  83             "=" & to_hstring(i_in.insn) &
  84             " expected 00000001"
  85             severity failure;
  86
  87         i_out.req <= '0';
  88
  89         wait for clk_period;
  90
  91         -- hit
  92         i_out.req <= '1';
  93         i_out.nia <= x"0000000000000008";
  94         wait for clk_period;
  95         assert i_in.valid = '1';
  96         assert i_in.insn = x"00000002"
  97             report "insn @" & to_hstring(i_out.nia) &
  98             "=" & to_hstring(i_in.insn) &
  99             " expected 00000002"
 100             severity failure;
 101         wait for clk_period;
 102
 103         -- another miss
 104         i_out.req <= '1';
 105         i_out.nia <= x"0000000000000040";
 106
 107         wait for 30*clk_period;
 108
 109         assert i_in.valid = '1';
 110         assert i_in.insn = x"00000010"
 111             report "insn @" & to_hstring(i_out.nia) &
 112             "=" & to_hstring(i_in.insn) &
 113             " expected 00000010"
 114             severity failure;
 115
 116         -- test something that aliases
 117         i_out.req <= '1';
 118         i_out.nia <= x"0000000000000100";
 119         wait for clk_period;
 120         assert i_in.valid = '0';
 121         wait for clk_period;
 122
 123         wait for 30*clk_period;
 124
 125         assert i_in.valid = '1';
 126         assert i_in.insn = x"00000040"
 127             report "insn @" & to_hstring(i_out.nia) &
 128             "=" & to_hstring(i_in.insn) &
 129             " expected 00000040"
 130             severity failure;
 131
 132         i_out.req <= '0';
 133
 134         assert false report "end of test" severity failure;
 135         wait;
 136
 137     end process;
 138 end;