5250a19f1710a8fe8c39153a4aa42706d2d10782
1 #ifndef __TEST_MACROS_SCALAR_H
2 #define __TEST_MACROS_SCALAR_H
5 #-----------------------------------------------------------------------
7 #-----------------------------------------------------------------------
9 #define TEST_CASE( testnum, testreg, correctval, code... ) \
13 li TESTNUM, testnum; \
14 bne testreg, x29, fail;
16 #define TEST_CASE_JUMP( testnum, testreg, correctval, code... ) \
20 li TESTNUM, testnum; \
21 beq testreg, x29, pass_ ## testnum; \
25 # We use a macro hack to simpify code generation for various numbers
28 #define TEST_INSERT_NOPS_0
29 #define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0
30 #define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1
31 #define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2
32 #define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3
33 #define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4
34 #define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5
35 #define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6
36 #define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7
37 #define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8
38 #define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
41 #-----------------------------------------------------------------------
43 #-----------------------------------------------------------------------
45 #-----------------------------------------------------------------------
46 # Tests for instructions with immediate operand
47 #-----------------------------------------------------------------------
49 #define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
51 #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
52 TEST_CASE( testnum, x3, result, \
54 inst x3, x1, SEXT_IMM(imm); \
57 #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
58 TEST_CASE( testnum, x1, result, \
60 inst x1, x1, SEXT_IMM(imm); \
63 #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
64 TEST_CASE( testnum, x6, result, \
67 inst x3, x1, SEXT_IMM(imm); \
68 TEST_INSERT_NOPS_ ## nop_cycles \
75 #define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
76 TEST_CASE( testnum, x3, result, \
79 TEST_INSERT_NOPS_ ## nop_cycles \
80 inst x3, x1, SEXT_IMM(imm); \
86 #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
87 TEST_CASE( testnum, x1, result, \
88 inst x1, x0, SEXT_IMM(imm); \
91 #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
92 TEST_CASE( testnum, x0, 0, \
94 inst x0, x1, SEXT_IMM(imm); \
97 #-----------------------------------------------------------------------
98 # Tests for vector config instructions
99 #-----------------------------------------------------------------------
101 #define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
102 TEST_CASE_JUMP( testnum, x1, result, \
103 li x1, (bank << 12); \
104 vsetcfg x1,nxpr,nfpr; \
109 #define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \
110 TEST_CASE_JUMP( testnum, x1, result, \
111 li x1, (bank << 12) | (nfpr << 6) | nxpr; \
117 #define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \
118 TEST_CASE_JUMP( testnum, x1, result, \
119 li x1, (bank << 12); \
120 vsetcfg x1,nxpr,nfpr; \
125 #-----------------------------------------------------------------------
126 # Tests for an instruction with register operands
127 #-----------------------------------------------------------------------
129 #define TEST_R_OP( testnum, inst, result, val1 ) \
130 TEST_CASE( testnum, x3, result, \
135 #define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
136 TEST_CASE( testnum, x1, result, \
141 #define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
142 TEST_CASE( testnum, x6, result, \
146 TEST_INSERT_NOPS_ ## nop_cycles \
153 #-----------------------------------------------------------------------
154 # Tests for an instruction with register-register operands
155 #-----------------------------------------------------------------------
157 #define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
158 TEST_CASE( testnum, x3, result, \
164 #define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
165 TEST_CASE( testnum, x1, result, \
171 #define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
172 TEST_CASE( testnum, x2, result, \
178 #define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
179 TEST_CASE( testnum, x1, result, \
184 #define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
185 TEST_CASE( testnum, x6, result, \
190 TEST_INSERT_NOPS_ ## nop_cycles \
197 #define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
198 TEST_CASE( testnum, x3, result, \
201 TEST_INSERT_NOPS_ ## src1_nops \
203 TEST_INSERT_NOPS_ ## src2_nops \
210 #define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
211 TEST_CASE( testnum, x3, result, \
214 TEST_INSERT_NOPS_ ## src1_nops \
216 TEST_INSERT_NOPS_ ## src2_nops \
223 #define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
224 TEST_CASE( testnum, x2, result, \
229 #define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
230 TEST_CASE( testnum, x2, result, \
235 #define TEST_RR_ZEROSRC12( testnum, inst, result ) \
236 TEST_CASE( testnum, x1, result, \
240 #define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
241 TEST_CASE( testnum, x0, 0, \
247 #-----------------------------------------------------------------------
248 # Test memory instructions
249 #-----------------------------------------------------------------------
251 #define TEST_LD_OP( testnum, inst, result, offset, base ) \
252 TEST_CASE( testnum, x3, result, \
254 inst x3, offset(x1); \
257 #define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
258 TEST_CASE( testnum, x3, result, \
261 store_inst x2, offset(x1); \
262 load_inst x3, offset(x1); \
265 #define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
267 li TESTNUM, testnum; \
270 inst x3, offset(x1); \
271 TEST_INSERT_NOPS_ ## nop_cycles \
279 #define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
281 li TESTNUM, testnum; \
284 TEST_INSERT_NOPS_ ## nop_cycles \
285 inst x3, offset(x1); \
292 #define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
294 li TESTNUM, testnum; \
297 TEST_INSERT_NOPS_ ## src1_nops \
299 TEST_INSERT_NOPS_ ## src2_nops \
300 store_inst x1, offset(x2); \
301 load_inst x3, offset(x2); \
308 #define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
310 li TESTNUM, testnum; \
313 TEST_INSERT_NOPS_ ## src1_nops \
315 TEST_INSERT_NOPS_ ## src2_nops \
316 store_inst x1, offset(x2); \
317 load_inst x3, offset(x2); \
324 #-----------------------------------------------------------------------
325 # Test branch instructions
326 #-----------------------------------------------------------------------
328 #define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
330 li TESTNUM, testnum; \
333 bne x0, TESTNUM, fail; \
334 1: bne x0, TESTNUM, 3f; \
336 bne x0, TESTNUM, fail; \
339 #define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
341 li TESTNUM, testnum; \
344 bne x0, TESTNUM, 2f; \
345 1: bne x0, TESTNUM, fail; \
349 #define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
351 li TESTNUM, testnum; \
354 TEST_INSERT_NOPS_ ## nop_cycles \
360 #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
362 li TESTNUM, testnum; \
366 bne x0, TESTNUM, fail; \
367 1: bne x0, TESTNUM, 3f; \
368 2: inst x1, x2, 1b; \
369 bne x0, TESTNUM, fail; \
372 #define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
374 li TESTNUM, testnum; \
378 bne x0, TESTNUM, 2f; \
379 1: bne x0, TESTNUM, fail; \
380 2: inst x1, x2, 1b; \
383 #define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
385 li TESTNUM, testnum; \
388 TEST_INSERT_NOPS_ ## src1_nops \
390 TEST_INSERT_NOPS_ ## src2_nops \
396 #define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
398 li TESTNUM, testnum; \
401 TEST_INSERT_NOPS_ ## src1_nops \
403 TEST_INSERT_NOPS_ ## src2_nops \
409 #-----------------------------------------------------------------------
410 # Test jump instructions
411 #-----------------------------------------------------------------------
413 #define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
415 li TESTNUM, testnum; \
418 TEST_INSERT_NOPS_ ## nop_cycles \
420 bne x0, TESTNUM, fail; \
425 #define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
427 li TESTNUM, testnum; \
430 TEST_INSERT_NOPS_ ## nop_cycles \
432 bne x0, TESTNUM, fail; \
438 #-----------------------------------------------------------------------
440 #-----------------------------------------------------------------------
442 #-----------------------------------------------------------------------
443 # Tests floating-point instructions
444 #-----------------------------------------------------------------------
446 #define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
448 li TESTNUM, testnum; \
449 la a0, test_ ## testnum ## _data ;\
462 test_ ## testnum ## _data: \
470 #define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
472 li TESTNUM, testnum; \
473 la a0, test_ ## testnum ## _data ;\
486 test_ ## testnum ## _data: \
494 #define TEST_FCVT_S_D( testnum, result, val1 ) \
495 TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
496 fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
498 #define TEST_FCVT_D_S( testnum, result, val1 ) \
499 TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
500 fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
502 #define TEST_FP_OP1_S( testnum, inst, result, val1 ) \
503 TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
504 inst f3, f0; fmv.x.s a0, f3)
506 #define TEST_FP_OP1_D( testnum, inst, result, val1 ) \
507 TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
508 inst f3, f0; fmv.x.d a0, f3)
510 #define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
511 TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
512 inst f3, f0, f1; fmv.x.s a0, f3)
514 #define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
515 TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
516 inst f3, f0, f1; fmv.x.d a0, f3)
518 #define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
519 TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
520 inst f3, f0, f1, f2; fmv.x.s a0, f3)
522 #define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
523 TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \
524 inst f3, f0, f1, f2; fmv.x.d a0, f3)
526 #define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
527 TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
530 #define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
531 TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
534 #define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \
535 TEST_FP_OP_S_INTERNAL( testnum, 0, word result, val1, val2, 0.0, \
538 #define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \
539 TEST_FP_OP_D_INTERNAL( testnum, 0, dword result, val1, val2, 0.0, \
542 #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
544 li TESTNUM, testnum; \
545 la a0, test_ ## testnum ## _data ;\
554 test_ ## testnum ## _data: \
558 #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
560 li TESTNUM, testnum; \
561 la a0, test_ ## testnum ## _data ;\
570 test_ ## testnum ## _data: \
575 #-----------------------------------------------------------------------
577 #-----------------------------------------------------------------------
579 #define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
580 csrs status, SR_EI; \
581 la a0, handler ## testnum; \
583 vsetcfg nxreg, nfreg; \
590 lui a0,%hi(vtcode1 ## testnum); \
591 vf %lo(vtcode1 ## testnum)(a0); \
593 illegal ## testnum: \
598 vtcode1 ## testnum: \
601 vtcode2 ## testnum: \
604 handler ## testnum: \
608 li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
611 la a1, illegal ## testnum; \
621 lui a0,%hi(vtcode2 ## testnum); \
622 vf %lo(vtcode2 ## testnum)(a0); \
640 #define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
641 csrs status, SR_EI; \
642 la a0, handler ## testnum; \
644 vsetcfg nxreg, nfreg; \
651 lui a0,%hi(vtcode1 ## testnum); \
652 vf %lo(vtcode1 ## testnum)(a0); \
656 vtcode1 ## testnum: \
658 illegal ## testnum: \
659 inst reg1, reg2, reg3; \
661 vtcode2 ## testnum: \
664 handler ## testnum: \
668 li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
671 la a1,illegal ## testnum; \
680 lui a0,%hi(vtcode2 ## testnum); \
681 vf %lo(vtcode2 ## testnum)(a0); \
699 #-----------------------------------------------------------------------
700 # Pass and fail code (assumes test num is in TESTNUM)
701 #-----------------------------------------------------------------------
703 #define TEST_PASSFAIL \
704 bne x0, TESTNUM, pass; \
711 #-----------------------------------------------------------------------
713 #-----------------------------------------------------------------------