d827bf51a4fa9ec305b8a5cde9b652b78735fc44
[riscv-tests.git] / isa / rv32si / privileged.S
1 #*****************************************************************************
2 # privileged.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test privileged instruction trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV32S
12 RVTEST_CODE_BEGIN
13
14 la t0, evec
15 csrw evec, t0
16
17 csrci status, 1
18
19 li TESTNUM, 2
20 sret
21 j fail
22
23 TEST_PASSFAIL
24
25 evec:
26 li t1, CAUSE_PRIVILEGED_INSTRUCTION
27 csrr t0, cause
28 bne t0, t1, fail
29 j pass
30
31 RVTEST_CODE_END
32
33 .data
34 RVTEST_DATA_BEGIN
35
36 TEST_DATA
37
38 RVTEST_DATA_END