isa/rv64mi/access.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # access.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test access-exception behavior.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   .align 2
  17
  18   # Flipping just the MSB should result in an illegal address for RV64.
  19   la t2, fail
  20   li t0, 1 << (__riscv_xlen - 1)
  21   xor t0, t0, t2
  22
  23   # jalr to an illegal address should commit (hence should write rd).
  24   # after the pc is set to rs1, an access exception should be raised.
  25   li TESTNUM, 2
  26   li t1, CAUSE_FETCH_ACCESS
  27   la t3, 1f
  28   li t2, 0
  29   jalr t2, t0
  30 1:
  31
  32   # A load to an illegal address should not commit.
  33   li TESTNUM, 3
  34   li t1, CAUSE_LOAD_ACCESS
  35   la t3, 1f
  36   mv t2, t3
  37   lb t2, (t0)
  38   j fail
  39 1:
  40
  41   j pass
  42
  43   TEST_PASSFAIL
  44
  45   .align 2
  46   .global mtvec_handler
  47 mtvec_handler:
  48   li a0, 2
  49   beq TESTNUM, a0, 2f
  50   li a0, 3
  51   beq TESTNUM, a0, 2f
  52   j fail
  53
  54 2:
  55   bne t2, t3, fail
  56
  57   csrr t2, mcause
  58   bne t2, t1, fail
  59
  60   csrw mepc, t3
  61   mret
  62
  63 RVTEST_CODE_END
  64
  65   .data
  66 RVTEST_DATA_BEGIN
  67
  68   TEST_DATA
  69
  70 RVTEST_DATA_END