isa/rv64mi/breakpoint.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # breakpoint.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test breakpoints, if they are implemented.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   # Set up breakpoint to trap on M-mode fetches.
  17   li TESTNUM, 2
  18
  19   # Skip tdrselect is hard-wired.
  20   li t0, 1<<(_RISCV_SZLONG-1)
  21   csrw tdrselect, t0
  22   csrr t1, tdrselect
  23   bne t0, t1, pass
  24
  25   # Make sure there's a breakpoint there.
  26   csrr t0, tdrdata1
  27   srli t0, t0, _RISCV_SZLONG-4
  28   li t1, 1
  29   bne t0, t1, pass
  30
  31   la t2, 1f
  32   csrw tdrdata2, t2
  33   li t0, BPCONTROL_M | BPCONTROL_X
  34   csrw tdrdata1, t0
  35   # Skip if breakpoint type is unsupported.
  36   csrr t1, tdrdata1
  37   andi t1, t1, 0x7ff
  38   bne t0, t1, 2f
  39 1:
  40   # Trap handler should skip this instruction.
  41   j fail
  42
  43   # Make sure reads don't trap.
  44   li TESTNUM, 3
  45   lw t0, (t2)
  46
  47 2:
  48   # Set up breakpoint to trap on M-mode reads.
  49   li TESTNUM, 4
  50   li t0, BPCONTROL_M | BPCONTROL_R
  51   csrw tdrdata1, t0
  52   # Skip if breakpoint type is unsupported.
  53   csrr t1, tdrdata1
  54   andi t1, t1, 0x7ff
  55   bne t0, t1, 2f
  56   la t2, write_data
  57   csrw tdrdata2, t2
  58
  59   # Trap handler should skip this instruction.
  60   lw t2, (t2)
  61   beqz t2, fail
  62
  63   # Make sure writes don't trap.
  64   li TESTNUM, 5
  65   sw x0, (t2)
  66
  67 2:
  68   # Set up breakpoint to trap on M-mode stores.
  69   li TESTNUM, 6
  70   li t0, BPCONTROL_M | BPCONTROL_W
  71   csrw tdrdata1, t0
  72   # Skip if breakpoint type is unsupported.
  73   csrr t1, tdrdata1
  74   andi t1, t1, 0x7ff
  75   bne t0, t1, 2f
  76
  77   # Trap handler should skip this instruction.
  78   sw t2, (t2)
  79
  80   # Make sure store didn't succeed.
  81   li TESTNUM, 7
  82   lw t2, (t2)
  83   bnez t2, fail
  84
  85 2:
  86   TEST_PASSFAIL
  87
  88 mtvec_handler:
  89   # Only even-numbered tests should trap.
  90   andi a0, TESTNUM, 1
  91   bnez a0, fail
  92
  93   li a0, CAUSE_BREAKPOINT
  94   csrr a1, mcause
  95   bne a0, a1, fail
  96
  97   csrr a0, mepc
  98   addi a0, a0, 4
  99   csrw mepc, a0
 100   mret
 101
 102 RVTEST_CODE_END
 103
 104   .data
 105 RVTEST_DATA_BEGIN
 106
 107   TEST_DATA
 108
 109 write_data: .word 0
 110
 111 RVTEST_DATA_END