isa/rv64mi/ma_addr.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_addr.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned ld/st trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   .align 2
  17   .option norvc
  18
  19   la s0, data
  20
  21   # indicate it's a load test
  22   li s1, CAUSE_MISALIGNED_LOAD
  23
  24 #define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1)))
  25
  26 /* Check that a misaligned load either writes the correct value, or
  27    takes an exception and performs no writeback.  */
  28 #define MISALIGNED_LOAD_TEST(testnum, insn, base, offset, res) \
  29   li TESTNUM, testnum; \
  30   la t2, 1f; \
  31   addi t1, base, offset; \
  32   insn t1, offset(base); \
  33   li t2, res; \
  34   bne t1, t2, fail; \
  35 1:
  36
  37   MISALIGNED_LOAD_TEST(2,  lh,  s0, 1, SEXT(0xbbcc, 16))
  38   MISALIGNED_LOAD_TEST(3,  lhu, s0, 1, 0xbbcc)
  39   MISALIGNED_LOAD_TEST(4,  lw,  s0, 1, SEXT(0x99aabbcc, 32))
  40   MISALIGNED_LOAD_TEST(5,  lw,  s0, 2, SEXT(0x8899aabb, 32))
  41   MISALIGNED_LOAD_TEST(6,  lw,  s0, 3, SEXT(0x778899aa, 32))
  42
  43 #if __riscv_xlen == 64
  44   MISALIGNED_LOAD_TEST(7,  lwu, s0, 1, 0x99aabbcc)
  45   MISALIGNED_LOAD_TEST(8,  lwu, s0, 2, 0x8899aabb)
  46   MISALIGNED_LOAD_TEST(9,  lwu, s0, 3, 0x778899aa)
  47
  48   MISALIGNED_LOAD_TEST(10, ld, s0, 1, 0x5566778899aabbcc)
  49   MISALIGNED_LOAD_TEST(11, ld, s0, 2, 0x445566778899aabb)
  50   MISALIGNED_LOAD_TEST(12, ld, s0, 3, 0x33445566778899aa)
  51   MISALIGNED_LOAD_TEST(13, ld, s0, 4, 0x2233445566778899)
  52   MISALIGNED_LOAD_TEST(14, ld, s0, 5, 0x1122334455667788)
  53   MISALIGNED_LOAD_TEST(15, ld, s0, 6, 0xee11223344556677)
  54   MISALIGNED_LOAD_TEST(16, ld, s0, 7, 0xffee112233445566)
  55 #endif
  56
  57   # indicate it's a store test
  58   li s1, CAUSE_MISALIGNED_STORE
  59
  60 /* Check that a misaligned store has some effect and takes no exception,
  61    or takes no effect and generates an exception.  This is not very
  62    thorough.  */
  63 #define MISALIGNED_STORE_TEST(testnum, insn, base, offset, size) \
  64   li TESTNUM, testnum; \
  65   la t2, 1f; \
  66   addi t1, base, offset; \
  67   insn x0, offset(base); \
  68   lb t1, (offset - 1)(base); \
  69   beqz t1, fail; \
  70   lb t1, (offset + size)(base); \
  71   beqz t1, fail; \
  72   lb t1, (offset + 0)(base); \
  73   bnez t1, fail; \
  74   lb t1, (offset + size - 1)(base); \
  75   bnez t1, fail; \
  76 1:
  77
  78   MISALIGNED_STORE_TEST(22,  sh,  s0, 1, 2)
  79   MISALIGNED_STORE_TEST(23,  sw,  s0, 5, 4)
  80   MISALIGNED_STORE_TEST(24,  sw,  s0, 10, 4)
  81   MISALIGNED_STORE_TEST(25,  sw,  s0, 15, 4)
  82
  83 #if __riscv_xlen == 64
  84   MISALIGNED_STORE_TEST(26, sd, s0, 25, 8)
  85   MISALIGNED_STORE_TEST(27, sd, s0, 34, 8)
  86   MISALIGNED_STORE_TEST(28, sd, s0, 43, 8)
  87   MISALIGNED_STORE_TEST(29, sd, s0, 52, 8)
  88   MISALIGNED_STORE_TEST(30, sd, s0, 61, 8)
  89   MISALIGNED_STORE_TEST(31, sd, s0, 70, 8)
  90   MISALIGNED_STORE_TEST(32, sd, s0, 79, 8)
  91 #endif
  92
  93   TEST_PASSFAIL
  94
  95   .align 3
  96   .global mtvec_handler
  97 mtvec_handler:
  98   csrr t0, mcause
  99   bne t0, s1, fail
 100
 101   csrr t0, mbadaddr
 102   bne t0, t1, fail
 103
 104   lb t0, (t0)
 105   beqz t0, fail
 106
 107   csrw mepc, t2
 108   mret
 109
 110 RVTEST_CODE_END
 111
 112   .data
 113 RVTEST_DATA_BEGIN
 114
 115 data:
 116   .align 3
 117 .word 0xaabbccdd
 118 .word 0x66778899
 119 .word 0x22334455
 120 .word 0xeeffee11
 121 .fill 0xff, 1, 80
 122
 123
 124   TEST_DATA
 125
 126 RVTEST_DATA_END