isa/rv64sv/ma_vt_inst.S

   1 #*****************************************************************************
   2 # ma_vt_inst.S
   3 #-----------------------------------------------------------------------------
   4 #
   5 # Test misaligned vt instruction trap.
   6 #
   7
   8 #include "riscv_test.h"
   9 #include "test_macros.h"
  10
  11 RVTEST_RV64S
  12 RVTEST_CODE_BEGIN
  13
  14   mfpcr a3,cr0
  15   li a4,1
  16   slli a5,a4,8
  17   or a3,a3,a4 # enable traps
  18   mtpcr a3,cr0
  19
  20   la a3,handler
  21   mtpcr a3,cr3 # set exception handler
  22
  23   li a3,4
  24   vvcfgivl a3,a3,32,0
  25
  26   lui a0,%hi(vtcode1+2)
  27   vf %lo(vtcode1+2)(a0)
  28 1:      j 1b
  29
  30 vtcode1:
  31   add x2,x2,x3
  32   stop
  33
  34 handler:
  35   vxcptkill
  36
  37   li x28,2
  38
  39   # check cause
  40   mfpcr a3,cr6
  41   li a4,24
  42   bne a3,a4,fail
  43
  44   # check badvaddr
  45   mfpcr a3,cr2
  46   la a4,vtcode1+2
  47   bne a3,a4,fail
  48
  49   # make sure vector unit has cleared out
  50   li a3,4
  51   vvcfgivl a3,a3,32,0
  52
  53   la a3,src1
  54   la a4,src2
  55   vld vx2,a3
  56   vld vx3,a4
  57   lui a0,%hi(vtcode1)
  58   vf %lo(vtcode1)(a0)
  59   la a5,dest
  60   vsd vx2,a5
  61   fence.v.l
  62
  63   ld a1,0(a5)
  64   li a2,5
  65   li x28,2
  66   bne a1,a2,fail
  67   ld a1,8(a5)
  68   li x28,3
  69   bne a1,a2,fail
  70   ld a1,16(a5)
  71   li x28,4
  72   bne a1,a2,fail
  73   ld a1,24(a5)
  74   li x28,5
  75   bne a1,a2,fail
  76
  77   TEST_PASSFAIL
  78
  79 RVTEST_CODE_END
  80
  81   .data
  82 RVTEST_DATA_BEGIN
  83
  84   TEST_DATA
  85
  86 src1:
  87   .dword 1
  88   .dword 2
  89   .dword 3
  90   .dword 4
  91 src2:
  92   .dword 4
  93   .dword 3
  94   .dword 2
  95   .dword 1
  96 dest:
  97   .dword 0xdeadbeefcafebabe
  98   .dword 0xdeadbeefcafebabe
  99   .dword 0xdeadbeefcafebabe
 100   .dword 0xdeadbeefcafebabe
 101
 102 RVTEST_DATA_END