d772041263dbb1462c9b3053b133574f417e6a15
[riscv-tests.git] / isa / rv64sv / ma_vt_inst.S
1 #*****************************************************************************
2 # ma_vt_inst.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test misaligned vt instruction trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 li a0, SR_EA | SR_EI
15 csrs status, a0
16
17 la a3,handler
18 csrw evec,a3
19
20 csrr a3,status
21 li a4,(1 << IRQ_COP)
22 slli a4,a4,SR_IM_SHIFT
23 or a3,a3,a4 # enable IM[COP]
24 csrw status,a3
25
26 vsetcfg 32,0
27 li a3,4
28 vsetvl a3,a3
29
30 lui a0,%hi(vtcode1+2)
31 vf %lo(vtcode1+2)(a0)
32 1: j 1b
33
34 vtcode1:
35 add x2,x2,x3
36 stop
37
38 handler:
39 vxcptkill
40
41 li TESTNUM,2
42
43 # check cause
44 vxcptcause a3
45 li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
46 bne a3,a4,fail
47
48 # check badvaddr
49 vxcptaux a3
50 la a4,vtcode1+2
51 andi a3, a3, -4 # mask off lower bits so that may
52 andi a4, a4, -4 # ignore impl. specific behavior
53 bne a3,a4,fail
54
55 # make sure vector unit has cleared out
56 vsetcfg 32,0
57 li a3,4
58 vsetvl a3,a3
59
60 la a3,src1
61 la a4,src2
62 vld vx2,a3
63 vld vx3,a4
64 lui a0,%hi(vtcode1)
65 vf %lo(vtcode1)(a0)
66 la a5,dest
67 vsd vx2,a5
68 fence
69
70 ld a1,0(a5)
71 li a2,5
72 li TESTNUM,2
73 bne a1,a2,fail
74 ld a1,8(a5)
75 li TESTNUM,3
76 bne a1,a2,fail
77 ld a1,16(a5)
78 li TESTNUM,4
79 bne a1,a2,fail
80 ld a1,24(a5)
81 li TESTNUM,5
82 bne a1,a2,fail
83
84 TEST_PASSFAIL
85
86 RVTEST_CODE_END
87
88 .data
89 RVTEST_DATA_BEGIN
90
91 TEST_DATA
92
93 src1:
94 .dword 1
95 .dword 2
96 .dword 3
97 .dword 4
98 src2:
99 .dword 4
100 .dword 3
101 .dword 2
102 .dword 1
103 dest:
104 .dword 0xdeadbeefcafebabe
105 .dword 0xdeadbeefcafebabe
106 .dword 0xdeadbeefcafebabe
107 .dword 0xdeadbeefcafebabe
108
109 RVTEST_DATA_END