Add LICENSE
[riscv-tests.git] / isa / rv64sv / privileged_inst.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # illegal_tvec_cmd.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test illegal tvec command trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64S
14 RVTEST_CODE_BEGIN
15
16 li a0, SR_EA | SR_EI
17 csrs status, a0
18
19 la a3,handler
20 csrw evec,a3 # set exception handler
21
22 csrr a3,status
23 li a4,(1 << IRQ_COP)
24 slli a4,a4,SR_IM_SHIFT
25 or a3,a3,a4 # enable IM[COP]
26 csrw status,a3
27
28 la a0, SR_U64
29 csrs status, a0
30 csrc status, SR_S
31
32 privileged_inst:
33 vxcptcause a3 # privileged inst
34
35 vtcode2:
36 add x2,x2,x3
37 stop
38
39 handler:
40 vxcptkill
41
42 li TESTNUM,2
43
44 # check cause
45 vxcptcause a3
46 li a4,HWACHA_CAUSE_PRIVILEGED_INSTRUCTION
47 bne a3,a4,fail
48
49 # check vec irq aux
50 vxcptaux a3
51 la a4, privileged_inst
52 lw a5, 0(a4)
53 bne a3,a5,fail
54
55 # make sure vector unit has cleared out
56 vsetcfg 32,0
57 li a3,4
58 vsetvl a3,a3
59
60 la a3,src1
61 la a4,src2
62 vld vx2,a3
63 vld vx3,a4
64 lui a0,%hi(vtcode2)
65 vf %lo(vtcode2)(a0)
66 la a5,dest
67 vsd vx2,a5
68 fence
69
70 ld a1,0(a5)
71 li a2,5
72 li TESTNUM,2
73 bne a1,a2,fail
74 ld a1,8(a5)
75 li TESTNUM,3
76 bne a1,a2,fail
77 ld a1,16(a5)
78 li TESTNUM,4
79 bne a1,a2,fail
80 ld a1,24(a5)
81 li TESTNUM,5
82 bne a1,a2,fail
83
84 TEST_PASSFAIL
85
86 RVTEST_CODE_END
87
88 .data
89 RVTEST_DATA_BEGIN
90
91 TEST_DATA
92
93 src1:
94 .dword 1
95 .dword 2
96 .dword 3
97 .dword 4
98 src2:
99 .dword 4
100 .dword 3
101 .dword 2
102 .dword 1
103 dest:
104 .dword 0xdeadbeefcafebabe
105 .dword 0xdeadbeefcafebabe
106 .dword 0xdeadbeefcafebabe
107 .dword 0xdeadbeefcafebabe
108
109 RVTEST_DATA_END