Add RV32 RVC and breakpoint tests
[riscv-tests.git] / isa / rv64uc / rvc.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # rvc.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test RVC corner cases.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64U
14 RVTEST_CODE_BEGIN
15
16 .option push
17 .option norvc
18
19 #define RVC_TEST_CASE(n, r, v, code...) \
20 TEST_CASE (n, r, v, .option push; .option rvc; code; .option pop)
21
22 // Make sure fetching a 4-byte instruction across a page boundary works.
23 li TESTNUM, 2
24 li a1, 666
25 li a2, 1
26 RVC_TEST_CASE (2, a1, 2, \
27 j 1f; \
28 .align 12; \
29 .skip 4094; \
30 1: addi a1, a2, 1)
31
32 li sp, 0x1234
33 RVC_TEST_CASE (3, a0, 0x1234 + 1020, c.addi4spn a0, sp, 1020)
34 RVC_TEST_CASE (4, sp, 0x1234 + 496, c.addi16sp sp, 496)
35 RVC_TEST_CASE (5, sp, 0x1234 + 496 - 512, c.addi16sp sp, -512)
36
37 la a1, data
38 RVC_TEST_CASE (6, a2, 0xfffffffffedcba99, c.lw a0, 4(a1); addi a0, a0, 1; c.sw a0, 4(a1); c.lw a2, 4(a1))
39 #ifdef __riscv64
40 RVC_TEST_CASE (7, a2, 0xfedcba9976543211, c.ld a0, 0(a1); addi a0, a0, 1; c.sd a0, 0(a1); c.ld a2, 0(a1))
41 #endif
42
43 RVC_TEST_CASE (8, a0, -15, ori a0, x0, 1; c.addi a0, -16)
44 RVC_TEST_CASE (9, a5, -16, ori a5, x0, 1; c.li a5, -16)
45 #ifdef __riscv64
46 RVC_TEST_CASE (10, a0, 0x76543210, ld a0, (a1); c.addiw a0, -1)
47 #endif
48
49 RVC_TEST_CASE (11, s0, 0xffffffffffffffe1, c.lui s0, 0xfffe1; c.srai s0, 12)
50 #ifdef __riscv64
51 RVC_TEST_CASE (12, s0, 0x000fffffffffffe1, c.lui s0, 0xfffe1; c.srli s0, 12)
52 #else
53 RVC_TEST_CASE (12, s0, 0x000fffe1, c.lui s0, 0xfffe1; c.srli s0, 12)
54 #endif
55 RVC_TEST_CASE (14, s0, ~0x11, c.li s0, -2; c.andi s0, ~0x10)
56 RVC_TEST_CASE (15, s1, 14, li s1, 20; li a0, 6; c.sub s1, a0)
57 RVC_TEST_CASE (16, s1, 18, li s1, 20; li a0, 6; c.xor s1, a0)
58 RVC_TEST_CASE (17, s1, 22, li s1, 20; li a0, 6; c.or s1, a0)
59 RVC_TEST_CASE (18, s1, 4, li s1, 20; li a0, 6; c.and s1, a0)
60 #ifdef __riscv64
61 RVC_TEST_CASE (19, s1, 0xffffffff80000000, li s1, 0x7fffffff; li a0, -1; c.subw s1, a0)
62 RVC_TEST_CASE (20, s1, 0xffffffff80000000, li s1, 0x7fffffff; li a0, 1; c.addw s1, a0)
63 #endif
64 RVC_TEST_CASE (21, s0, 0x12340, li s0, 0x1234; c.slli s0, 4)
65
66 RVC_TEST_CASE (30, ra, 0, \
67 li ra, 0; \
68 c.j 1f; \
69 c.j 2f; \
70 1:c.j 1f; \
71 2:j fail; \
72 1:)
73
74 RVC_TEST_CASE (31, x0, 0, \
75 li a0, 0; \
76 c.beqz a0, 1f; \
77 c.j 2f; \
78 1:c.j 1f; \
79 2:j fail; \
80 1:)
81
82 RVC_TEST_CASE (32, x0, 0, \
83 li a0, 1; \
84 c.bnez a0, 1f; \
85 c.j 2f; \
86 1:c.j 1f; \
87 2:j fail; \
88 1:)
89
90 RVC_TEST_CASE (33, x0, 0, \
91 li a0, 1; \
92 c.beqz a0, 1f; \
93 c.j 2f; \
94 1:c.j fail; \
95 2:)
96
97 RVC_TEST_CASE (34, x0, 0, \
98 li a0, 0; \
99 c.bnez a0, 1f; \
100 c.j 2f; \
101 1:c.j fail; \
102 2:)
103
104 RVC_TEST_CASE (35, ra, 0, \
105 la t0, 1f; \
106 li ra, 0; \
107 c.jr t0; \
108 c.j 2f; \
109 1:c.j 1f; \
110 2:j fail; \
111 1:)
112
113 RVC_TEST_CASE (36, ra, -2, \
114 la t0, 1f; \
115 li ra, 0; \
116 c.jalr t0; \
117 c.j 2f; \
118 1:c.j 1f; \
119 2:j fail; \
120 1:sub ra, ra, t0)
121
122 #ifdef __riscv32
123 RVC_TEST_CASE (37, ra, -2, \
124 la t0, 1f; \
125 li ra, 0; \
126 c.jal 1f; \
127 c.j 2f; \
128 1:c.j 1f; \
129 2:j fail; \
130 1:sub ra, ra, t0)
131 #endif
132
133 la sp, data
134 RVC_TEST_CASE (40, a2, 0xfffffffffedcba99, c.lwsp a0, 12(sp); addi a0, a0, 1; c.swsp a0, 12(sp); c.lwsp a2, 12(sp))
135 #ifdef __riscv64
136 RVC_TEST_CASE (41, a2, 0xfedcba9976543211, c.ldsp a0, 8(sp); addi a0, a0, 1; c.sdsp a0, 8(sp); c.ldsp a2, 8(sp))
137 #endif
138
139 RVC_TEST_CASE (42, t0, 0x246, li a0, 0x123; c.mv t0, a0; c.add t0, a0)
140
141 .option pop
142
143 TEST_PASSFAIL
144
145 RVTEST_CODE_END
146
147 .data
148 RVTEST_DATA_BEGIN
149
150 data:
151 .dword 0xfedcba9876543210
152 .dword 0xfedcba9876543210
153
154 RVTEST_DATA_END