1 #include "riscv_test.h"
2 #include "sv_test_macros.h"
4 RVTEST_RV64U # Define TVM used by program.
7 # SV test: vector-vector add different rd and rs1
9 # sets up x6 and x7 with data, sets VL to 2, and carries out
10 # an "x3 = 1 + x6". which actually means "x3 = 1 + x6 *AND* x4 = 1 + x7"
13 RVTEST_CODE_BEGIN # Start of test code.
17 SV_LD_DATA( x6, testdata+0 , 0)
18 SV_LD_DATA( x7, testdata+8, 0)
19 SV_LD_DATA( x8, testdata+16, 0)
21 li x3, 0 # deliberately set x3 to 0 (target of add)
22 li x4, 0 # deliberately set x4 to 0
23 li x5, 0 # deliberately set x4 to 0
26 SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0),
27 SV_REG_CSR(1, 6, 0, 6, 1, 0) )
38 TEST_SV_IMM(x3, 1001) # should not be modified
42 RVTEST_PASS # Signal success.
45 RVTEST_CODE_END # End of test code.
48 # This section is optional, and this data is NOT saved in the output.
56 # Output data section.
57 RVTEST_DATA_BEGIN # Start of test output data region.
63 RVTEST_DATA_END # End of test output data region.