isa/rv64uv/fma_many.S

   1 #*****************************************************************************
   2 # fma.S
   3 #-----------------------------------------------------------------------------
   4 #
   5 # Test fma instruction in a vf block.
   6 #
   7
   8 #include "riscv_test.h"
   9 #include "test_macros.h"
  10
  11 RVTEST_RV64UV
  12 RVTEST_CODE_BEGIN
  13
  14   vsetcfg 3,16
  15   li a3,2048
  16   vsetvl a3,a3
  17
  18   la a4,src
  19   fld f0,0(a4)
  20   fld f1,8(a4)
  21   fmv.x.d s0,f0
  22   fmv.x.d s1,f1
  23   vmsv vx1,s0
  24   vmsv vx2,s1
  25   lui a0,%hi(vtcode)
  26   vf %lo(vtcode)(a0)
  27
  28   li a7,0
  29   li a6,400
  30 wait:
  31   addi a7,a7,1
  32   bne a7,a6,wait
  33
  34   fadd.d f0,f0,f1
  35   fmv.x.d s2,f0
  36
  37   la a5,dest
  38   vfsd vf0,a5
  39   fence
  40
  41   la s3,result
  42   ld s4,0(s3)
  43   li TESTNUM,2
  44   bne s2,s4,fail
  45
  46 # verify 1st fadd
  47   li a2,0
  48 loop1:
  49   ld a0,0(a5)
  50   addi TESTNUM,a2,3
  51   bne a0,s4,fail
  52   addi a5,a5,8
  53   addi a2,a2,1
  54   bne a2,a3,loop1
  55
  56 # verify 2nd fmadd
  57   la a5,dest
  58   vfsd vf2,a5
  59   fence
  60   ld s4,8(s3)
  61
  62   li a2,0
  63 loop2:
  64   ld a0,0(a5)
  65   addi TESTNUM,a2,3
  66   bne a0,s4,fail
  67   addi a5,a5,8
  68   addi a2,a2,1
  69   bne a2,a3,loop2
  70
  71 # verify 3rd fmul
  72   la a5,dest
  73   vfsd vf5,a5
  74   fence
  75   ld s4,16(s3)
  76
  77   li a2,0
  78 loop3:
  79   ld a0,0(a5)
  80   addi TESTNUM,a2,3
  81   bne a0,s4,fail
  82   addi a5,a5,8
  83   addi a2,a2,1
  84   bne a2,a3,loop3
  85
  86 # verify 4th fmul
  87   la a5,dest
  88   vfsd vf8,a5
  89   fence
  90   ld s4,24(s3)
  91
  92   li a2,0
  93 loop4:
  94   ld a0,0(a5)
  95   addi TESTNUM,a2,3
  96   bne a0,s4,fail
  97   addi a5,a5,8
  98   addi a2,a2,1
  99   bne a2,a3,loop4
 100
 101 # verify 5th fmadd
 102   la a5,dest
 103   vfsd vf9,a5
 104   fence
 105   ld s4,32(s3)
 106
 107   li a2,0
 108 loop5:
 109   ld a0,0(a5)
 110   addi TESTNUM,a2,3
 111   bne a0,s4,fail
 112   addi a5,a5,8
 113   addi a2,a2,1
 114   bne a2,a3,loop5
 115
 116 # verify 6th fnmadd
 117   la a5,dest
 118   vfsd vf11,a5
 119   fence
 120   ld s4,40(s3)
 121
 122   li a2,0
 123 loop6:
 124   ld a0,0(a5)
 125   addi TESTNUM,a2,3
 126   bne a0,s4,fail
 127   addi a5,a5,8
 128   addi a2,a2,1
 129   bne a2,a3,loop6
 130
 131   j pass
 132
 133 vtcode:
 134   fmv.d.x f0,x1
 135   fmv.d.x f1,x2
 136   fmv.d.x f2,x1
 137   fmv.d.x f3,x2
 138   fmv.d.x f4,x1
 139   fmv.d.x f5,x2
 140   fmv.d.x f6,x1
 141   fmv.d.x f7,x2
 142   fmv.d.x f8,x1
 143   fmv.d.x f9,x2
 144   fmv.d.x f10,x1
 145   fmv.d.x f11,x2
 146   fmv.d.x f12,x1
 147   fmv.d.x f13,x2
 148   fmv.d.x f14,x1
 149   fmv.d.x f15,x2
 150   fadd.d f0,f0,f1
 151   fmadd.d f2,f2,f3,f4
 152   fmul.d f5,f5,f6
 153   fmul.d f8,f5,f7
 154   fmadd.d f9,f9,f10,f9
 155   fnmadd.d f11,f12,f13,f14
 156   stop
 157
 158   TEST_PASSFAIL
 159
 160 RVTEST_CODE_END
 161
 162   .data
 163 RVTEST_DATA_BEGIN
 164
 165   TEST_DATA
 166
 167 src:
 168   .double 1.0
 169   .double 2.0
 170 result:
 171   .double 3.0
 172   .double 3.0
 173   .double 2.0
 174   .double 4.0
 175   .double 4.0
 176   .double -3.0
 177 dest:
 178   .skip 16384
 179
 180 RVTEST_DATA_END