initial commit
[riscv-tests.git] / isa / rv64uv / movn.S
1 #*****************************************************************************
2 # movn.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test movn instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64U
12 RVTEST_CODE_BEGIN
13
14 li a6,2048
15 vvcfgivl a6,a6,4,0
16
17 lui a0,%hi(vtcode)
18 vf %lo(vtcode)(a0)
19 la a7,dest
20 vsd vx3,a7
21 fence.v.l
22
23 li a1,0
24 li a2,-1
25 loop:
26 ld a0,0(a7)
27 slt a4,a1,10
28 slli a4,a4,63
29 srai a4,a4,63
30 and a5,a2,a4
31 addi s8,a1,2
32 bne a0,a5,fail
33 addi a7,a7,8
34 addi a1,a1,1
35 bne a1,a6,loop
36 j pass
37
38 vtcode:
39 utidx x1
40 slti x2,x1,10
41 li x1,-1
42 li x3,0
43 movn x3,x2,x1
44 stop
45
46 TEST_PASSFAIL
47
48 RVTEST_CODE_END
49
50 .data
51 RVTEST_DATA_BEGIN
52
53 TEST_DATA
54
55 dest:
56 .skip 16384
57
58 RVTEST_DATA_END