dd6f72ae424e87db7a25013e3513071aeb2ade46
[riscv-tests.git] / isa / rv64uv / sd.S
1 #*****************************************************************************
2 # sd.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test sd instruction in a vf block.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64U
12 RVTEST_CODE_BEGIN
13
14 li a4,512
15 vvcfgivl a4,a4,16,0
16
17 la a5,src
18 vld vx1,a5
19 la a6,dest
20 vmsv vx2,a6
21 lui a0,%hi(vtcode)
22 vf %lo(vtcode)(a0)
23 fence.v.l
24
25 li a2,0
26 loop:
27 ld a0,0(a6)
28 ld a1,0(a5)
29 addi x28,a2,2
30 bne a0,a1,fail
31 addi a6,a6,8
32 addi a5,a5,8
33 addi a2,a2,1
34 bne a2,a4,loop
35 j pass
36
37 vtcode:
38 utidx x3
39 slli x3,x3,3
40 add x2,x2,x3
41 sd x1,0(x2)
42 stop
43
44 TEST_PASSFAIL
45
46 RVTEST_CODE_END
47
48 .data
49 RVTEST_DATA_BEGIN
50
51 TEST_DATA
52
53 src:
54 #include "data_d.h"
55
56 dest:
57 .skip 16384
58
59 RVTEST_DATA_END