kernel/timinginfo.h

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
   5  *            (C) 2020  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 #ifndef TIMINGINFO_H
  22 #define TIMINGINFO_H
  23
  24 #include "kernel/yosys.h"
  25
  26 YOSYS_NAMESPACE_BEGIN
  27
  28 struct TimingInfo
  29 {
  30         struct NameBit
  31         {
  32                 RTLIL::IdString name;
  33                 int offset;
  34                 NameBit() : offset(0) {}
  35                 NameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}
  36                 explicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
  37                 bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }
  38                 bool operator!=(const NameBit& nb) const { return !operator==(nb); }
  39                 unsigned int hash() const { return mkhash_add(name.hash(), offset); }
  40         };
  41         struct BitBit
  42         {
  43                 NameBit first, second;
  44                 BitBit(const NameBit &first, const NameBit &second) : first(first), second(second) {}
  45                 BitBit(const SigBit &first, const SigBit &second) : first(first), second(second) {}
  46                 bool operator==(const BitBit& bb) const { return bb.first == first && bb.second == second; }
  47                 unsigned int hash() const { return mkhash_add(first.hash(), second.hash()); }
  48         };
  49
  50         struct ModuleTiming
  51         {
  52                 dict<BitBit, int> comb;
  53                 dict<NameBit, std::pair<int,NameBit>> arrival, required;
  54                 bool has_inputs;
  55         };
  56
  57         dict<RTLIL::IdString, ModuleTiming> data;
  58
  59         TimingInfo()
  60         {
  61         }
  62
  63         TimingInfo(RTLIL::Design *design)
  64         {
  65                 setup(design);
  66         }
  67
  68         void setup(RTLIL::Design *design)
  69         {
  70                 for (auto module : design->modules()) {
  71                         if (!module->get_blackbox_attribute())
  72                                 continue;
  73                         setup_module(module);
  74                 }
  75         }
  76
  77         const ModuleTiming& setup_module(RTLIL::Module *module)
  78         {
  79                 auto r = data.insert(module->name);
  80                 log_assert(r.second);
  81                 auto &t = r.first->second;
  82
  83                 for (auto cell : module->cells()) {
  84                         if (cell->type == ID($specify2)) {
  85                                 auto en = cell->getPort(ID::EN);
  86                                 if (en.is_fully_const() && !en.as_bool())
  87                                         continue;
  88                                 auto src = cell->getPort(ID::SRC);
  89                                 auto dst = cell->getPort(ID::DST);
  90                                 for (const auto &c : src.chunks())
  91                                         if (!c.wire || !c.wire->port_input)
  92                                                 log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
  93                                 for (const auto &c : dst.chunks())
  94                                         if (!c.wire || !c.wire->port_output)
  95                                                 log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
  96                                 int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
  97                                 int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
  98                                 int max = std::max(rise_max,fall_max);
  99                                 if (max < 0)
 100                                         log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
 101                                 if (cell->getParam(ID::FULL).as_bool()) {
 102                                         for (const auto &s : src)
 103                                                 for (const auto &d : dst) {
 104                                                         auto r = t.comb.insert(BitBit(s,d));
 105                                                         if (!r.second)
 106                                                                 log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
 107                                                         r.first->second = max;
 108                                                 }
 109                                 }
 110                                 else {
 111                                         log_assert(GetSize(src) == GetSize(dst));
 112                                         for (auto i = 0; i < GetSize(src); i++) {
 113                                                 const auto &s = src[i];
 114                                                 const auto &d = dst[i];
 115                                                 auto r = t.comb.insert(BitBit(s,d));
 116                                                 if (!r.second)
 117                                                         log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
 118                                                 r.first->second = max;
 119                                         }
 120                                 }
 121                         }
 122                         else if (cell->type == ID($specify3)) {
 123                                 auto src = cell->getPort(ID::SRC).as_bit();
 124                                 auto dst = cell->getPort(ID::DST);
 125                                 if (!src.wire || !src.wire->port_input)
 126                                         log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
 127                                 for (const auto &c : dst.chunks())
 128                                         if (!c.wire->port_output)
 129                                                 log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
 130                                 int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
 131                                 int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
 132                                 int max = std::max(rise_max,fall_max);
 133                                 if (max < 0) {
 134                                         log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell));
 135                                         max = 0;
 136                                 }
 137                                 for (const auto &d : dst) {
 138                                         auto r = t.arrival.insert(NameBit(d));
 139                                         auto &v = r.first->second;
 140                                         if (r.second || v.first < max) {
 141                                                 v.first = max;
 142                                                 v.second = NameBit(src);
 143                                         }
 144                                 }
 145                         }
 146                         else if (cell->type == ID($specrule)) {
 147                                 IdString type = cell->getParam(ID::TYPE).decode_string();
 148                                 if (type != ID($setup) && type != ID($setuphold))
 149                                         continue;
 150                                 auto src = cell->getPort(ID::SRC);
 151                                 auto dst = cell->getPort(ID::DST).as_bit();
 152                                 for (const auto &c : src.chunks())
 153                                         if (!c.wire || !c.wire->port_input)
 154                                                 log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
 155                                 if (!dst.wire || !dst.wire->port_input)
 156                                         log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
 157                                 int max = cell->getParam(ID::T_LIMIT_MAX).as_int();
 158                                 if (max < 0) {
 159                                         log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell));
 160                                         max = 0;
 161                                 }
 162                                 for (const auto &s : src) {
 163                                         auto r = t.required.insert(NameBit(s));
 164                                         auto &v = r.first->second;
 165                                         if (r.second || v.first < max) {
 166                                                 v.first = max;
 167                                                 v.second = NameBit(dst);
 168                                         }
 169                                 }
 170                         }
 171                 }
 172
 173                 for (auto port_name : module->ports) {
 174                         auto wire = module->wire(port_name);
 175                         if (wire->port_input) {
 176                                 t.has_inputs = true;
 177                                 break;
 178                         }
 179                 }
 180
 181                 return t;
 182         }
 183
 184         decltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }
 185         decltype(data)::const_iterator end() const { return data.end(); }
 186         int count(RTLIL::IdString module_name) const { return data.count(module_name); }
 187         const ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }
 188 };
 189
 190 YOSYS_NAMESPACE_END
 191
 192 #endif