libgram/src/dfii.c

   1 #include <stdint.h>
   2
   3 #include "hw_regs.h"
   4 #include <gram.h>
   5 #include "dfii.h"
   6 #include "helpers.h"
   7 #include "io.h"
   8
   9 static void dfii_setcontrol(const struct gramCtx *ctx, uint32_t val) {
  10 #ifdef GRAM_RW_FUNC
  11         gram_write(ctx, (void*)&(ctx->core->control), val);
  12 #else
  13         writel(val, (unsigned long)&(ctx->core->control));
  14 #endif
  15 }
  16
  17 void dfii_reset(const struct gramCtx *ctx) {
  18         dfii_set_p0_address(ctx, 0);
  19         dfii_set_p0_baddress(ctx, 0);
  20                 dfii_setcontrol(ctx, DFII_CONTROL_ODT|DFII_CONTROL_RESET);
  21 }
  22
  23 void dfii_setsw(const struct gramCtx *ctx, bool software_control) {
  24         if (software_control) {
  25                 dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT|
  26                              DFII_CONTROL_RESET);
  27         } else {
  28                 dfii_setcontrol(ctx, DFII_CONTROL_SEL);
  29         }
  30 }
  31
  32 void dfii_set_p0_address(const struct gramCtx *ctx, uint32_t val) {
  33 #ifdef GRAM_RW_FUNC
  34         gram_write(ctx, (void*)&(ctx->core->phases[0].address), val);
  35 #else
  36         writel(val, (unsigned long)&(ctx->core->phases[0].address));
  37 #endif
  38 }
  39
  40 void dfii_set_p0_baddress(const struct gramCtx *ctx, uint32_t val) {
  41 #ifdef GRAM_RW_FUNC
  42         gram_write(ctx, (void*)&(ctx->core->phases[0].baddress), val);
  43 #else
  44         writel(val, (unsigned long)&(ctx->core->phases[0].baddress));
  45 #endif
  46 }
  47
  48 void dfii_p0_command(const struct gramCtx *ctx, uint32_t cmd) {
  49 #ifdef GRAM_RW_FUNC
  50         gram_write(ctx, (void*)&(ctx->core->phases[0].command), cmd);
  51         gram_write(ctx, (void*)&(ctx->core->phases[0].command_issue), 1);
  52 #else
  53         writel(cmd, (unsigned long)&(ctx->core->phases[0].command));
  54         writel(1, (unsigned long)&(ctx->core->phases[0].command_issue));
  55 #endif
  56 }
  57
  58 /* Set MRx register */
  59 static void dfii_set_mr(const struct gramCtx *ctx, uint8_t mr, uint16_t val) {
  60         dfii_set_p0_address(ctx, val);
  61         dfii_set_p0_baddress(ctx, mr);
  62         dfii_p0_command(ctx, DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
  63 }
  64
  65 //comment these in to speed up icarus verilog simulations dramatically
  66 //#define LONG_TIMER_MULT 1
  67 //#define SHORT_TIMER_MULT 1
  68
  69 #define MR0_DLL_RESET (1 << 8)
  70 void dfii_initseq(const struct gramCtx *ctx, const struct gramProfile *profile) {
  71         /* Release reset */
  72         dfii_set_p0_address(ctx, 0x0);
  73         dfii_set_p0_baddress(ctx, 0);
  74         dfii_setcontrol(ctx, DFII_CONTROL_ODT|DFII_CONTROL_RESET);
  75         //cdelay(5*LONG_TIMER_MULT);
  76
  77         /* Bring CKE high */
  78         //dfii_set_p0_address(ctx, 0x0);
  79         //dfii_set_p0_baddress(ctx, 0);
  80         dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET);
  81         cdelay(1*LONG_TIMER_MULT);
  82
  83         /* Load Mode Register 2, CWL=5 */
  84         dfii_set_mr(ctx, 2, profile->mode_registers[2]);
  85
  86         /* Load Mode Register 3 */
  87         dfii_set_mr(ctx, 3, profile->mode_registers[3]);
  88
  89         /* Load Mode Register 1 */
  90         dfii_set_mr(ctx, 1, profile->mode_registers[1]);
  91
  92         /* Load Mode Register 0, CL=6, BL=8 */
  93         dfii_set_mr(ctx, 0, profile->mode_registers[0]);
  94     if (profile->mode_registers[0] & MR0_DLL_RESET) {
  95            cdelay(1*SHORT_TIMER_MULT);
  96            dfii_set_mr(ctx, 0, profile->mode_registers[0] & ~MR0_DLL_RESET);
  97     }
  98         cdelay(6*SHORT_TIMER_MULT);
  99
 100         /* ZQ Calibration */
 101         dfii_set_p0_address(ctx, 0x400);
 102         dfii_set_p0_baddress(ctx, 0);
 103         dfii_p0_command(ctx, DFII_COMMAND_WE|DFII_COMMAND_CS);
 104         cdelay(6*SHORT_TIMER_MULT);
 105 }