Add Tercel PHY reset synchronization
[microwatt.git] / liteeth / fusesoc-add-files.py
1 #!/usr/bin/python3
2 from fusesoc.capi2.generator import Generator
3 import os
4 import sys
5 import pathlib
6
7 class LiteEthGenerator(Generator):
8 def run(self):
9 board = self.config.get('board')
10
11 # Collect a bunch of directory path
12 script_dir = os.path.dirname(sys.argv[0])
13 gen_dir = os.path.join(script_dir, "generated", board)
14
15 print("Adding LiteEth for board... ", board)
16
17 # Add files to fusesoc
18 files = []
19 f = os.path.join(gen_dir, "liteeth_core.v")
20 files.append({f : {'file_type' : 'verilogSource'}})
21
22 self.add_files(files)
23
24 g = LiteEthGenerator()
25 g.run()
26 g.write()
27