loadstore1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8
   9 -- 2 cycle LSU
  10 -- We calculate the address in the first cycle
  11
  12 entity loadstore1 is
  13     generic (
  14         -- Non-zero to enable log data collection
  15         LOG_LENGTH : natural := 0
  16         );
  17     port (
  18         clk   : in std_ulogic;
  19         rst   : in std_ulogic;
  20
  21         l_in  : in Execute1ToLoadstore1Type;
  22         e_out : out Loadstore1ToExecute1Type;
  23         l_out : out Loadstore1ToWritebackType;
  24
  25         d_out : out Loadstore1ToDcacheType;
  26         d_in  : in DcacheToLoadstore1Type;
  27
  28         m_out : out Loadstore1ToMmuType;
  29         m_in  : in MmuToLoadstore1Type;
  30
  31         dc_stall  : in std_ulogic;
  32
  33         log_out : out std_ulogic_vector(9 downto 0)
  34         );
  35 end loadstore1;
  36
  37 -- Note, we don't currently use the stall output from the dcache because
  38 -- we know it can take two requests without stalling when idle, we are
  39 -- its only user, and we know it never stalls when idle.
  40
  41 architecture behave of loadstore1 is
  42
  43     -- State machine for unaligned loads/stores
  44     type state_t is (IDLE,              -- ready for instruction
  45                      SECOND_REQ,        -- send 2nd request of unaligned xfer
  46                      ACK_WAIT,          -- waiting for ack from dcache
  47                      MMU_LOOKUP,        -- waiting for MMU to look up translation
  48                      TLBIE_WAIT,        -- waiting for MMU to finish doing a tlbie
  49                      COMPLETE           -- extra cycle to complete an operation
  50                      );
  51
  52     type reg_stage_t is record
  53         -- latch most of the input request
  54         load         : std_ulogic;
  55         tlbie        : std_ulogic;
  56         dcbz         : std_ulogic;
  57         mfspr        : std_ulogic;
  58         addr         : std_ulogic_vector(63 downto 0);
  59         store_data   : std_ulogic_vector(63 downto 0);
  60         load_data    : std_ulogic_vector(63 downto 0);
  61         write_reg    : gpr_index_t;
  62         length       : std_ulogic_vector(3 downto 0);
  63         byte_reverse : std_ulogic;
  64         sign_extend  : std_ulogic;
  65         update       : std_ulogic;
  66         update_reg   : gpr_index_t;
  67         xerc         : xer_common_t;
  68         reserve      : std_ulogic;
  69         rc           : std_ulogic;
  70         nc           : std_ulogic;              -- non-cacheable access
  71         virt_mode    : std_ulogic;
  72         priv_mode    : std_ulogic;
  73         state        : state_t;
  74         dwords_done  : std_ulogic;
  75         last_dword   : std_ulogic;
  76         first_bytes  : std_ulogic_vector(7 downto 0);
  77         second_bytes : std_ulogic_vector(7 downto 0);
  78         dar          : std_ulogic_vector(63 downto 0);
  79         dsisr        : std_ulogic_vector(31 downto 0);
  80         instr_fault  : std_ulogic;
  81         sprval       : std_ulogic_vector(63 downto 0);
  82         busy         : std_ulogic;
  83         wait_dcache  : std_ulogic;
  84         wait_mmu     : std_ulogic;
  85         do_update    : std_ulogic;
  86         extra_cycle  : std_ulogic;
  87     end record;
  88
  89     type byte_sel_t is array(0 to 7) of std_ulogic;
  90     subtype byte_trim_t is std_ulogic_vector(1 downto 0);
  91     type trim_ctl_t is array(0 to 7) of byte_trim_t;
  92
  93     signal r, rin : reg_stage_t;
  94     signal lsu_sum : std_ulogic_vector(63 downto 0);
  95
  96     -- Generate byte enables from sizes
  97     function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is
  98     begin
  99         case length is
 100             when "0001" =>
 101                 return "00000001";
 102             when "0010" =>
 103                 return "00000011";
 104             when "0100" =>
 105                 return "00001111";
 106             when "1000" =>
 107                 return "11111111";
 108             when others =>
 109                 return "00000000";
 110         end case;
 111     end function length_to_sel;
 112
 113     -- Calculate byte enables
 114     -- This returns 16 bits, giving the select signals for two transfers,
 115     -- to account for unaligned loads or stores
 116     function xfer_data_sel(size : in std_logic_vector(3 downto 0);
 117                            address : in std_logic_vector(2 downto 0))
 118         return std_ulogic_vector is
 119         variable longsel : std_ulogic_vector(15 downto 0);
 120     begin
 121         longsel := "00000000" & length_to_sel(size);
 122         return std_ulogic_vector(shift_left(unsigned(longsel),
 123                                             to_integer(unsigned(address))));
 124     end function xfer_data_sel;
 125
 126 begin
 127     -- Calculate the address in the first cycle
 128     lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0');
 129
 130     loadstore1_0: process(clk)
 131     begin
 132         if rising_edge(clk) then
 133             if rst = '1' then
 134                 r.state <= IDLE;
 135                 r.busy <= '0';
 136                 r.do_update <= '0';
 137             else
 138                 r <= rin;
 139             end if;
 140         end if;
 141     end process;
 142
 143     loadstore1_1: process(all)
 144         variable v : reg_stage_t;
 145         variable brev_lenm1 : unsigned(2 downto 0);
 146         variable byte_offset : unsigned(2 downto 0);
 147         variable j : integer;
 148         variable k : unsigned(2 downto 0);
 149         variable kk : unsigned(3 downto 0);
 150         variable long_sel : std_ulogic_vector(15 downto 0);
 151         variable byte_sel : std_ulogic_vector(7 downto 0);
 152         variable req : std_ulogic;
 153         variable busy : std_ulogic;
 154         variable addr : std_ulogic_vector(63 downto 0);
 155         variable maddr : std_ulogic_vector(63 downto 0);
 156         variable wdata : std_ulogic_vector(63 downto 0);
 157         variable write_enable : std_ulogic;
 158         variable do_update : std_ulogic;
 159         variable done : std_ulogic;
 160         variable data_permuted : std_ulogic_vector(63 downto 0);
 161         variable data_trimmed : std_ulogic_vector(63 downto 0);
 162         variable store_data : std_ulogic_vector(63 downto 0);
 163         variable use_second : byte_sel_t;
 164         variable trim_ctl : trim_ctl_t;
 165         variable negative : std_ulogic;
 166         variable sprn : std_ulogic_vector(9 downto 0);
 167         variable exception : std_ulogic;
 168         variable next_addr : std_ulogic_vector(63 downto 0);
 169         variable mmureq : std_ulogic;
 170         variable dsisr : std_ulogic_vector(31 downto 0);
 171         variable mmu_mtspr : std_ulogic;
 172         variable itlb_fault : std_ulogic;
 173     begin
 174         v := r;
 175         req := '0';
 176         v.mfspr := '0';
 177         mmu_mtspr := '0';
 178         itlb_fault := '0';
 179         sprn := std_ulogic_vector(to_unsigned(decode_spr_num(l_in.insn), 10));
 180         dsisr := (others => '0');
 181         mmureq := '0';
 182
 183         write_enable := '0';
 184
 185         do_update := r.do_update;
 186         v.do_update := '0';
 187
 188         -- load data formatting
 189         byte_offset := unsigned(r.addr(2 downto 0));
 190         brev_lenm1 := "000";
 191         if r.byte_reverse = '1' then
 192             brev_lenm1 := unsigned(r.length(2 downto 0)) - 1;
 193         end if;
 194
 195         -- shift and byte-reverse data bytes
 196         for i in 0 to 7 loop
 197             kk := ('0' & (to_unsigned(i, 3) xor brev_lenm1)) + ('0' & byte_offset);
 198             use_second(i) := kk(3);
 199             j := to_integer(kk(2 downto 0)) * 8;
 200             data_permuted(i * 8 + 7 downto i * 8) := d_in.data(j + 7 downto j);
 201         end loop;
 202
 203         -- Work out the sign bit for sign extension.
 204         -- For unaligned loads crossing two dwords, the sign bit is in the
 205         -- first dword for big-endian (byte_reverse = 1), or the second dword
 206         -- for little-endian.
 207         if r.dwords_done = '1' and r.byte_reverse = '1' then
 208             negative := (r.length(3) and r.load_data(63)) or
 209                         (r.length(2) and r.load_data(31)) or
 210                         (r.length(1) and r.load_data(15)) or
 211                         (r.length(0) and r.load_data(7));
 212         else
 213             negative := (r.length(3) and data_permuted(63)) or
 214                         (r.length(2) and data_permuted(31)) or
 215                         (r.length(1) and data_permuted(15)) or
 216                         (r.length(0) and data_permuted(7));
 217         end if;
 218
 219         -- trim and sign-extend
 220         for i in 0 to 7 loop
 221             if i < to_integer(unsigned(r.length)) then
 222                 if r.dwords_done = '1' then
 223                     trim_ctl(i) := '1' & not use_second(i);
 224                 else
 225                     trim_ctl(i) := "10";
 226                 end if;
 227             else
 228                 trim_ctl(i) := '0' & (negative and r.sign_extend);
 229             end if;
 230             case trim_ctl(i) is
 231                 when "11" =>
 232                     data_trimmed(i * 8 + 7 downto i * 8) := r.load_data(i * 8 + 7 downto i * 8);
 233                 when "10" =>
 234                     data_trimmed(i * 8 + 7 downto i * 8) := data_permuted(i * 8 + 7 downto i * 8);
 235                 when "01" =>
 236                     data_trimmed(i * 8 + 7 downto i * 8) := x"FF";
 237                 when others =>
 238                     data_trimmed(i * 8 + 7 downto i * 8) := x"00";
 239             end case;
 240         end loop;
 241
 242         -- Byte reversing and rotating for stores
 243         -- Done in the first cycle (when l_in.valid = 1)
 244         store_data := r.store_data;
 245         if l_in.valid = '1' then
 246             byte_offset := unsigned(lsu_sum(2 downto 0));
 247             brev_lenm1 := "000";
 248             if l_in.byte_reverse = '1' then
 249                 brev_lenm1 := unsigned(l_in.length(2 downto 0)) - 1;
 250             end if;
 251             for i in 0 to 7 loop
 252                 k := (to_unsigned(i, 3) - byte_offset) xor brev_lenm1;
 253                 j := to_integer(k) * 8;
 254                 store_data(i * 8 + 7 downto i * 8) := l_in.data(j + 7 downto j);
 255             end loop;
 256         end if;
 257         v.store_data := store_data;
 258
 259         -- compute (addr + 8) & ~7 for the second doubleword when unaligned
 260         next_addr := std_ulogic_vector(unsigned(r.addr(63 downto 3)) + 1) & "000";
 261
 262         -- Busy calculation.
 263         -- We need to minimize the delay from clock to busy valid because it
 264         -- gates the start of execution of the next instruction.
 265         busy := r.busy and not ((r.wait_dcache and d_in.valid) or (r.wait_mmu and m_in.done));
 266         v.busy := busy;
 267
 268         done := '0';
 269         if r.state /= IDLE and busy = '0' then
 270             done := '1';
 271         end if;
 272         exception := '0';
 273
 274         if r.dwords_done = '1' or r.state = SECOND_REQ then
 275             maddr := next_addr;
 276             byte_sel := r.second_bytes;
 277         else
 278             maddr := r.addr;
 279             byte_sel := r.first_bytes;
 280         end if;
 281         addr := maddr;
 282
 283         case r.state is
 284         when IDLE =>
 285
 286         when SECOND_REQ =>
 287             req := '1';
 288             v.state := ACK_WAIT;
 289             v.last_dword := '0';
 290
 291         when ACK_WAIT =>
 292             if d_in.error = '1' then
 293                 -- dcache will discard the second request if it
 294                 -- gets an error on the 1st of two requests
 295                 if d_in.cache_paradox = '1' then
 296                     -- signal an interrupt straight away
 297                     exception := '1';
 298                     dsisr(63 - 38) := not r.load;
 299                     -- XXX there is no architected bit for this
 300                     dsisr(63 - 35) := d_in.cache_paradox;
 301                 else
 302                     -- Look up the translation for TLB miss
 303                     -- and also for permission error and RC error
 304                     -- in case the PTE has been updated.
 305                     mmureq := '1';
 306                     v.state := MMU_LOOKUP;
 307                 end if;
 308             end if;
 309             if d_in.valid = '1' then
 310                 if r.last_dword = '0' then
 311                     v.dwords_done := '1';
 312                     v.last_dword := '1';
 313                     if r.load = '1' then
 314                         v.load_data := data_permuted;
 315                     end if;
 316                 else
 317                     write_enable := r.load;
 318                     if r.extra_cycle = '1' then
 319                         -- loads with rA update need an extra cycle
 320                         v.state := COMPLETE;
 321                         v.do_update := r.update;
 322                     else
 323                         -- stores write back rA update in this cycle
 324                         do_update := r.update;
 325                     end if;
 326                     v.busy := '0';
 327                 end if;
 328             end if;
 329             -- r.wait_dcache gets set one cycle after we come into ACK_WAIT state,
 330             -- which is OK because the dcache always takes at least two cycles.
 331             v.wait_dcache := r.last_dword and not r.extra_cycle;
 332
 333         when MMU_LOOKUP =>
 334             if m_in.done = '1' then
 335                 if r.instr_fault = '0' then
 336                     -- retry the request now that the MMU has installed a TLB entry
 337                     req := '1';
 338                     if r.last_dword = '0' then
 339                         v.state := SECOND_REQ;
 340                     else
 341                         v.state := ACK_WAIT;
 342                     end if;
 343                 end if;
 344             end if;
 345             if m_in.err = '1' then
 346                 exception := '1';
 347                 dsisr(63 - 33) := m_in.invalid;
 348                 dsisr(63 - 36) := m_in.perm_error;
 349                 dsisr(63 - 38) := not r.load;
 350                 dsisr(63 - 44) := m_in.badtree;
 351                 dsisr(63 - 45) := m_in.rc_error;
 352             end if;
 353
 354         when TLBIE_WAIT =>
 355
 356         when COMPLETE =>
 357
 358         end case;
 359
 360         if done = '1' or exception = '1' then
 361             v.state := IDLE;
 362             v.busy := '0';
 363         end if;
 364
 365         -- Note that l_in.valid is gated with busy inside execute1
 366         if l_in.valid = '1' then
 367             v.addr := lsu_sum;
 368             v.load := '0';
 369             v.dcbz := '0';
 370             v.tlbie := '0';
 371             v.instr_fault := '0';
 372             v.dwords_done := '0';
 373             v.last_dword := '1';
 374             v.write_reg := l_in.write_reg;
 375             v.length := l_in.length;
 376             v.byte_reverse := l_in.byte_reverse;
 377             v.sign_extend := l_in.sign_extend;
 378             v.update := l_in.update;
 379             v.update_reg := l_in.update_reg;
 380             v.xerc := l_in.xerc;
 381             v.reserve := l_in.reserve;
 382             v.rc := l_in.rc;
 383             v.nc := l_in.ci;
 384             v.virt_mode := l_in.virt_mode;
 385             v.priv_mode := l_in.priv_mode;
 386             v.wait_dcache := '0';
 387             v.wait_mmu := '0';
 388             v.do_update := '0';
 389             v.extra_cycle := '0';
 390
 391             addr := lsu_sum;
 392             maddr := l_in.addr2;    -- address from RB for tlbie
 393
 394             -- XXX Temporary hack. Mark the op as non-cachable if the address
 395             -- is the form 0xc------- for a real-mode access.
 396             if lsu_sum(31 downto 28) = "1100" and l_in.virt_mode = '0' then
 397                 v.nc := '1';
 398             end if;
 399
 400             -- Do length_to_sel and work out if we are doing 2 dwords
 401             long_sel := xfer_data_sel(l_in.length, v.addr(2 downto 0));
 402             byte_sel := long_sel(7 downto 0);
 403             v.first_bytes := byte_sel;
 404             v.second_bytes := long_sel(15 downto 8);
 405
 406             case l_in.op is
 407                 when OP_STORE =>
 408                     req := '1';
 409                 when OP_LOAD =>
 410                     req := '1';
 411                     v.load := '1';
 412                     -- Allow an extra cycle for RA update on loads
 413                     v.extra_cycle := l_in.update;
 414                 when OP_DCBZ =>
 415                     req := '1';
 416                     v.dcbz := '1';
 417                 when OP_TLBIE =>
 418                     mmureq := '1';
 419                     v.tlbie := '1';
 420                     v.state := TLBIE_WAIT;
 421                     v.wait_mmu := '1';
 422                 when OP_MFSPR =>
 423                     v.mfspr := '1';
 424                     -- partial decode on SPR number should be adequate given
 425                     -- the restricted set that get sent down this path
 426                     if sprn(9) = '0' and sprn(5) = '0' then
 427                         if sprn(0) = '0' then
 428                             v.sprval := x"00000000" & r.dsisr;
 429                         else
 430                             v.sprval := r.dar;
 431                         end if;
 432                     else
 433                         -- reading one of the SPRs in the MMU
 434                         v.sprval := m_in.sprval;
 435                     end if;
 436                     v.state := COMPLETE;
 437                 when OP_MTSPR =>
 438                     if sprn(9) = '0' and sprn(5) = '0' then
 439                         if sprn(0) = '0' then
 440                             v.dsisr := l_in.data(31 downto 0);
 441                         else
 442                             v.dar := l_in.data;
 443                         end if;
 444                         v.state := COMPLETE;
 445                     else
 446                         -- writing one of the SPRs in the MMU
 447                         mmu_mtspr := '1';
 448                         v.state := TLBIE_WAIT;
 449                         v.wait_mmu := '1';
 450                     end if;
 451                 when OP_FETCH_FAILED =>
 452                     -- send it to the MMU to do the radix walk
 453                     maddr := l_in.nia;
 454                     v.instr_fault := '1';
 455                     mmureq := '1';
 456                     v.state := MMU_LOOKUP;
 457                     v.wait_mmu := '1';
 458                 when others =>
 459                     assert false report "unknown op sent to loadstore1";
 460             end case;
 461
 462             if req = '1' then
 463                 if long_sel(15 downto 8) = "00000000" then
 464                     v.state := ACK_WAIT;
 465                 else
 466                     v.state := SECOND_REQ;
 467                 end if;
 468             end if;
 469
 470             v.busy := req or mmureq or mmu_mtspr;
 471         end if;
 472
 473         -- Update outputs to dcache
 474         d_out.valid <= req;
 475         d_out.load <= v.load;
 476         d_out.dcbz <= v.dcbz;
 477         d_out.nc <= v.nc;
 478         d_out.reserve <= v.reserve;
 479         d_out.addr <= addr;
 480         d_out.data <= store_data;
 481         d_out.byte_sel <= byte_sel;
 482         d_out.virt_mode <= v.virt_mode;
 483         d_out.priv_mode <= v.priv_mode;
 484
 485         -- Update outputs to MMU
 486         m_out.valid <= mmureq;
 487         m_out.iside <= v.instr_fault;
 488         m_out.load <= r.load;
 489         m_out.priv <= r.priv_mode;
 490         m_out.tlbie <= v.tlbie;
 491         m_out.mtspr <= mmu_mtspr;
 492         m_out.sprn <= sprn;
 493         m_out.addr <= maddr;
 494         m_out.slbia <= l_in.insn(7);
 495         m_out.rs <= l_in.data;
 496
 497         -- Update outputs to writeback
 498         -- Multiplex either cache data to the destination GPR or
 499         -- the address for the rA update.
 500         l_out.valid <= done;
 501         if r.mfspr = '1' then
 502             l_out.write_enable <= '1';
 503             l_out.write_reg <= r.write_reg;
 504             l_out.write_data <= r.sprval;
 505         elsif do_update = '1' then
 506             l_out.write_enable <= '1';
 507             l_out.write_reg <= r.update_reg;
 508             l_out.write_data <= r.addr;
 509         else
 510             l_out.write_enable <= write_enable;
 511             l_out.write_reg <= r.write_reg;
 512             l_out.write_data <= data_trimmed;
 513         end if;
 514         l_out.xerc <= r.xerc;
 515         l_out.rc <= r.rc and done;
 516         l_out.store_done <= d_in.store_done;
 517
 518         -- update exception info back to execute1
 519         e_out.busy <= busy;
 520         e_out.exception <= exception;
 521         e_out.instr_fault <= r.instr_fault;
 522         e_out.invalid <= m_in.invalid;
 523         e_out.badtree <= m_in.badtree;
 524         e_out.perm_error <= m_in.perm_error;
 525         e_out.rc_error <= m_in.rc_error;
 526         e_out.segment_fault <= m_in.segerr;
 527         if exception = '1' and r.instr_fault = '0' then
 528             v.dar := addr;
 529             if m_in.segerr = '0' then
 530                 v.dsisr := dsisr;
 531             end if;
 532         end if;
 533
 534         -- Update registers
 535         rin <= v;
 536
 537     end process;
 538
 539     l1_log: if LOG_LENGTH > 0 generate
 540         signal log_data : std_ulogic_vector(9 downto 0);
 541     begin
 542         ls1_log: process(clk)
 543         begin
 544             if rising_edge(clk) then
 545                 log_data <= e_out.busy &
 546                             e_out.exception &
 547                             l_out.valid &
 548                             m_out.valid &
 549                             d_out.valid &
 550                             m_in.done &
 551                             r.dwords_done &
 552                             std_ulogic_vector(to_unsigned(state_t'pos(r.state), 3));
 553             end if;
 554         end process;
 555         log_out <= log_data;
 556     end generate;
 557
 558 end;