logical.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.ppc_fx_insns.all;
   8
   9 entity logical is
  10     port (
  11         rs         : in std_ulogic_vector(63 downto 0);
  12         rb         : in std_ulogic_vector(63 downto 0);
  13         op         : in insn_type_t;
  14         invert_in  : in std_ulogic;
  15         invert_out : in std_ulogic;
  16         result     : out std_ulogic_vector(63 downto 0);
  17         datalen    : in std_logic_vector(3 downto 0)
  18         );
  19 end entity logical;
  20
  21 architecture behaviour of logical is
  22
  23     subtype twobit is unsigned(1 downto 0);
  24     type twobit32 is array(0 to 31) of twobit;
  25     signal pc2      : twobit32;
  26     subtype threebit is unsigned(2 downto 0);
  27     type threebit16 is array(0 to 15) of threebit;
  28     signal pc4      : threebit16;
  29     subtype fourbit is unsigned(3 downto 0);
  30     type fourbit8 is array(0 to 7) of fourbit;
  31     signal pc8      : fourbit8;
  32     subtype sixbit is unsigned(5 downto 0);
  33     type sixbit2 is array(0 to 1) of sixbit;
  34     signal pc32     : sixbit2;
  35     signal par0, par1 : std_ulogic;
  36     signal popcnt   : std_ulogic_vector(63 downto 0);
  37     signal parity   : std_ulogic_vector(63 downto 0);
  38
  39 begin
  40     logical_0: process(all)
  41         variable rb_adj, tmp : std_ulogic_vector(63 downto 0);
  42         variable negative : std_ulogic;
  43     begin
  44         -- population counts
  45         for i in 0 to 31 loop
  46             pc2(i) <= unsigned("0" & rs(i * 2 downto i * 2)) + unsigned("0" & rs(i * 2 + 1 downto i * 2 + 1));
  47         end loop;
  48         for i in 0 to 15 loop
  49             pc4(i) <= ('0' & pc2(i * 2)) + ('0' & pc2(i * 2 + 1));
  50         end loop;
  51         for i in 0 to 7 loop
  52             pc8(i) <= ('0' & pc4(i * 2)) + ('0' & pc4(i * 2 + 1));
  53         end loop;
  54         for i in 0 to 1 loop
  55             pc32(i) <= ("00" & pc8(i * 4)) + ("00" & pc8(i * 4 + 1)) +
  56                        ("00" & pc8(i * 4 + 2)) + ("00" & pc8(i * 4 + 3));
  57         end loop;
  58         popcnt <= (others => '0');
  59         if datalen(3 downto 2) = "00" then
  60             -- popcntb
  61             for i in 0 to 7 loop
  62                 popcnt(i * 8 + 3 downto i * 8) <= std_ulogic_vector(pc8(i));
  63             end loop;
  64         elsif datalen(3) = '0' then
  65             -- popcntw
  66             for i in 0 to 1 loop
  67                 popcnt(i * 32 + 5 downto i * 32) <= std_ulogic_vector(pc32(i));
  68             end loop;
  69         else
  70             popcnt(6 downto 0) <= std_ulogic_vector(('0' & pc32(0)) + ('0' & pc32(1)));
  71         end if;
  72
  73         -- parity calculations
  74         par0 <= rs(0) xor rs(8) xor rs(16) xor rs(24);
  75         par1 <= rs(32) xor rs(40) xor rs(48) xor rs(56);
  76         parity <= (others => '0');
  77         if datalen(3) = '1' then
  78             parity(0) <= par0 xor par1;
  79         else
  80             parity(0) <= par0;
  81             parity(32) <= par1;
  82         end if;
  83
  84         rb_adj := rb;
  85         if invert_in = '1' then
  86             rb_adj := not rb;
  87         end if;
  88
  89         case op is
  90             when OP_AND =>
  91                 tmp := rs and rb_adj;
  92             when OP_OR =>
  93                 tmp := rs or rb_adj;
  94             when OP_XOR =>
  95                 tmp := rs xor rb_adj;
  96             when OP_POPCNT =>
  97                 tmp := popcnt;
  98             when OP_PRTY =>
  99                 tmp := parity;
 100             when OP_CMPB =>
 101                 tmp := ppc_cmpb(rs, rb);
 102             when others =>
 103                 -- EXTS
 104                 -- note datalen is a 1-hot encoding
 105                 negative := (datalen(0) and rs(7)) or
 106                             (datalen(1) and rs(15)) or
 107                             (datalen(2) and rs(31));
 108                 tmp := (others => negative);
 109                 if datalen(2) = '1' then
 110                     tmp(31 downto 16) := rs(31 downto 16);
 111                 end if;
 112                 if datalen(2) = '1' or datalen(1) = '1' then
 113                     tmp(15 downto 8) := rs(15 downto 8);
 114                 end if;
 115                 tmp(7 downto 0) := rs(7 downto 0);
 116         end case;
 117
 118         if invert_out = '1' then
 119             tmp := not tmp;
 120         end if;
 121         result <= tmp;
 122
 123     end process;
 124 end behaviour;