logical.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 entity logical is
   9     port (
  10         rs         : in std_ulogic_vector(63 downto 0);
  11         rb         : in std_ulogic_vector(63 downto 0);
  12         op         : in insn_type_t;
  13         invert_in  : in std_ulogic;
  14         invert_out : in std_ulogic;
  15         result     : out std_ulogic_vector(63 downto 0)
  16         );
  17 end entity logical;
  18
  19 architecture behaviour of logical is
  20 begin
  21     logical_0: process(all)
  22         variable rb_adj, tmp : std_ulogic_vector(63 downto 0);
  23     begin
  24         rb_adj := rb;
  25         if invert_in = '1' then
  26             rb_adj := not rb;
  27         end if;
  28
  29         case op is
  30             when OP_AND =>
  31                 tmp := rs and rb_adj;
  32             when OP_OR =>
  33                 tmp := rs or rb_adj;
  34             when others =>
  35                 tmp := rs xor rb_adj;
  36         end case;
  37
  38         result <= tmp;
  39         if invert_out = '1' then
  40             result <= not tmp;
  41         end if;
  42
  43     end process;
  44 end behaviour;