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3aada6ebd80b09e3a5130bef1243b8db9324f519
[soc-cocotb-sim.git] / ls180 / post_pnr / chip_corona / chip_r.vhd
1 LIBRARY IEEE;
2 USE IEEE.std_logic_1164.ALL;
3 USE IEEE.numeric_std.ALL;
4
5 -- =======================================================================
6 -- Coriolis Structural VHDL Driver
7 -- Generated on Apr 10, 2021, 14:21
8 --
9 -- To be interoperable with Alliance, it uses it's special VHDL subset.
10 -- ("man vhdl" under Alliance for more informations)
11 -- =======================================================================
12
13 entity chip_r is
14 port ( eint_0 : inout std_logic
15 ; eint_1 : inout std_logic
16 ; eint_2 : inout std_logic
17 ; gpio_10 : inout std_logic
18 ; gpio_11 : inout std_logic
19 ; gpio_12 : inout std_logic
20 ; gpio_13 : inout std_logic
21 ; gpio_14 : inout std_logic
22 ; gpio_15 : inout std_logic
23 ; i2c_sda : inout std_logic
24 ; jtag_tck : inout std_logic
25 ; jtag_tdi : inout std_logic
26 ; jtag_tms : inout std_logic
27 ; sdram_dq_10 : inout std_logic
28 ; sdram_dq_11 : inout std_logic
29 ; sdram_dq_12 : inout std_logic
30 ; sdram_dq_13 : inout std_logic
31 ; sdram_dq_14 : inout std_logic
32 ; sdram_dq_15 : inout std_logic
33 ; spimaster_miso : inout std_logic
34 ; sys_clk : inout std_logic
35 ; sys_rst : inout std_logic
36 ; uart_rx : inout std_logic
37 ; uart_tx : inout std_logic
38 ; nc : inout std_logic_vector(39 downto 0)
39 ; gpio_0 : inout std_logic
40 ; gpio_1 : inout std_logic
41 ; gpio_2 : inout std_logic
42 ; gpio_3 : inout std_logic
43 ; gpio_4 : inout std_logic
44 ; gpio_5 : inout std_logic
45 ; gpio_6 : inout std_logic
46 ; gpio_7 : inout std_logic
47 ; gpio_8 : inout std_logic
48 ; gpio_9 : inout std_logic
49 ; i2c_scl : inout std_logic
50 ; jtag_tdo : inout std_logic
51 ; sdram_cas_n : inout std_logic
52 ; sdram_cke : inout std_logic
53 ; sdram_clock : inout std_logic
54 ; sdram_cs_n : inout std_logic
55 ; sdram_dq_0 : inout std_logic
56 ; sdram_dq_1 : inout std_logic
57 ; sdram_dq_2 : inout std_logic
58 ; sdram_dq_3 : inout std_logic
59 ; sdram_dq_4 : inout std_logic
60 ; sdram_dq_5 : inout std_logic
61 ; sdram_dq_6 : inout std_logic
62 ; sdram_dq_7 : inout std_logic
63 ; sdram_dq_8 : inout std_logic
64 ; sdram_dq_9 : inout std_logic
65 ; sdram_ras_n : inout std_logic
66 ; sdram_we_n : inout std_logic
67 ; spimaster_clk : inout std_logic
68 ; spimaster_cs_n : inout std_logic
69 ; spimaster_mosi : inout std_logic
70 ; sdram_ba : out std_logic_vector(1 downto 0)
71 ; sdram_dm : out std_logic_vector(1 downto 0)
72 ; sdram_a : out std_logic_vector(12 downto 0)
73 ; iovdd : in bit
74 ; iovss : in bit
75 ; vdd : in bit
76 ; vss : in bit
77 );
78 end chip_r;
79
80 architecture structural of chip_r is
81
82 component corona_cts_r
83 port ( eint_0_from_pad : in bit
84 ; eint_1_from_pad : in bit
85 ; eint_2_from_pad : in bit
86 ; i2c_sda_i_from_pad : in bit
87 ; jtag_tck_from_pad : in bit
88 ; jtag_tdi_from_pad : in bit
89 ; jtag_tms_from_pad : in bit
90 ; spimaster_miso_from_pad : in bit
91 ; sys_clk_from_pad : in bit
92 ; sys_rst_from_pad : in bit
93 ; uart_rx_from_pad : in bit
94 ; uart_tx_from_pad : in bit
95 ; gpio_i_from_pad : in bit_vector(15 downto 0)
96 ; sdram_dq_i_from_pad : in bit_vector(15 downto 0)
97 ; nc_from_pad : in bit_vector(39 downto 0)
98 ; eint_0_enable_to_pad : out bit
99 ; eint_1_enable_to_pad : out bit
100 ; eint_2_enable_to_pad : out bit
101 ; i2c_scl_enable_to_pad : out bit
102 ; i2c_scl_to_pad : out bit
103 ; i2c_sda_o_to_pad : out bit
104 ; i2c_sda_oe_to_pad : out bit
105 ; jtag_tck_enable_to_pad : out bit
106 ; jtag_tdi_enable_to_pad : out bit
107 ; jtag_tdo_enable_to_pad : out bit
108 ; jtag_tdo_to_pad : out bit
109 ; jtag_tms_enable_to_pad : out bit
110 ; nc_0_enable_to_pad : out bit
111 ; nc_10_enable_to_pad : out bit
112 ; nc_11_enable_to_pad : out bit
113 ; nc_12_enable_to_pad : out bit
114 ; nc_13_enable_to_pad : out bit
115 ; nc_14_enable_to_pad : out bit
116 ; nc_15_enable_to_pad : out bit
117 ; nc_16_enable_to_pad : out bit
118 ; nc_17_enable_to_pad : out bit
119 ; nc_18_enable_to_pad : out bit
120 ; nc_19_enable_to_pad : out bit
121 ; nc_1_enable_to_pad : out bit
122 ; nc_20_enable_to_pad : out bit
123 ; nc_21_enable_to_pad : out bit
124 ; nc_22_enable_to_pad : out bit
125 ; nc_23_enable_to_pad : out bit
126 ; nc_24_enable_to_pad : out bit
127 ; nc_25_enable_to_pad : out bit
128 ; nc_26_enable_to_pad : out bit
129 ; nc_27_enable_to_pad : out bit
130 ; nc_28_enable_to_pad : out bit
131 ; nc_29_enable_to_pad : out bit
132 ; nc_2_enable_to_pad : out bit
133 ; nc_30_enable_to_pad : out bit
134 ; nc_31_enable_to_pad : out bit
135 ; nc_32_enable_to_pad : out bit
136 ; nc_33_enable_to_pad : out bit
137 ; nc_34_enable_to_pad : out bit
138 ; nc_35_enable_to_pad : out bit
139 ; nc_36_enable_to_pad : out bit
140 ; nc_37_enable_to_pad : out bit
141 ; nc_38_enable_to_pad : out bit
142 ; nc_39_enable_to_pad : out bit
143 ; nc_3_enable_to_pad : out bit
144 ; nc_4_enable_to_pad : out bit
145 ; nc_5_enable_to_pad : out bit
146 ; nc_6_enable_to_pad : out bit
147 ; nc_7_enable_to_pad : out bit
148 ; nc_8_enable_to_pad : out bit
149 ; nc_9_enable_to_pad : out bit
150 ; sdram_a_0_enable_to_pad : out bit
151 ; sdram_a_10_enable_to_pad : out bit
152 ; sdram_a_11_enable_to_pad : out bit
153 ; sdram_a_12_enable_to_pad : out bit
154 ; sdram_a_1_enable_to_pad : out bit
155 ; sdram_a_2_enable_to_pad : out bit
156 ; sdram_a_3_enable_to_pad : out bit
157 ; sdram_a_4_enable_to_pad : out bit
158 ; sdram_a_5_enable_to_pad : out bit
159 ; sdram_a_6_enable_to_pad : out bit
160 ; sdram_a_7_enable_to_pad : out bit
161 ; sdram_a_8_enable_to_pad : out bit
162 ; sdram_a_9_enable_to_pad : out bit
163 ; sdram_ba_0_enable_to_pad : out bit
164 ; sdram_ba_1_enable_to_pad : out bit
165 ; sdram_cas_n_enable_to_pad : out bit
166 ; sdram_cas_n_to_pad : out bit
167 ; sdram_cke_enable_to_pad : out bit
168 ; sdram_cke_to_pad : out bit
169 ; sdram_clock_enable_to_pad : out bit
170 ; sdram_clock_to_pad : out bit
171 ; sdram_cs_n_enable_to_pad : out bit
172 ; sdram_cs_n_to_pad : out bit
173 ; sdram_dm_0_enable_to_pad : out bit
174 ; sdram_dm_1_enable_to_pad : out bit
175 ; sdram_ras_n_enable_to_pad : out bit
176 ; sdram_ras_n_to_pad : out bit
177 ; sdram_we_n_enable_to_pad : out bit
178 ; sdram_we_n_to_pad : out bit
179 ; spimaster_clk_enable_to_pad : out bit
180 ; spimaster_clk_to_pad : out bit
181 ; spimaster_cs_n_enable_to_pad : out bit
182 ; spimaster_cs_n_to_pad : out bit
183 ; spimaster_miso_enable_to_pad : out bit
184 ; spimaster_mosi_enable_to_pad : out bit
185 ; spimaster_mosi_to_pad : out bit
186 ; sys_clk_enable_to_pad : out bit
187 ; sys_rst_enable_to_pad : out bit
188 ; uart_rx_enable_to_pad : out bit
189 ; uart_tx_enable_to_pad : out bit
190 ; sdram_ba_to_pad : out bit_vector(1 downto 0)
191 ; sdram_dm_to_pad : out bit_vector(1 downto 0)
192 ; sdram_a_to_pad : out bit_vector(12 downto 0)
193 ; gpio_o_to_pad : out bit_vector(15 downto 0)
194 ; gpio_oe_to_pad : out bit_vector(15 downto 0)
195 ; sdram_dq_o_to_pad : out bit_vector(15 downto 0)
196 ; sdram_dq_oe_to_pad : out bit_vector(15 downto 0)
197 ; vdd : in bit
198 ; vss : in bit
199 );
200 end component;
201
202 component cmpt_iovss
203 port ( iovdd : in bit
204 ; iovss : in bit
205 ; vdd : in bit
206 ; vss : in bit
207 );
208 end component;
209
210 component cmpt_iovdd
211 port ( iovdd : in bit
212 ; iovss : in bit
213 ; vdd : in bit
214 ; vss : in bit
215 );
216 end component;
217
218 component cmpt_vss
219 port ( iovdd : in bit
220 ; iovss : in bit
221 ; vdd : in bit
222 ; vss : in bit
223 );
224 end component;
225
226 component cmpt_vdd
227 port ( iovdd : in bit
228 ; iovss : in bit
229 ; vdd : in bit
230 ; vss : in bit
231 );
232 end component;
233
234 component cmpt_gpio
235 port ( i : in bit
236 ; oe : in bit
237 ; o : out bit
238 ; pad : inout std_logic
239 ; iovdd : in bit
240 ; iovss : in bit
241 ; vdd : in bit
242 ; vss : in bit
243 );
244 end component;
245
246 signal chip_dummy_0 : bit;
247 signal chip_dummy_1 : bit;
248 signal chip_dummy_10 : bit;
249 signal chip_dummy_11 : bit;
250 signal chip_dummy_12 : bit;
251 signal chip_dummy_13 : bit;
252 signal chip_dummy_14 : bit;
253 signal chip_dummy_15 : bit;
254 signal chip_dummy_16 : bit;
255 signal chip_dummy_17 : bit;
256 signal chip_dummy_18 : bit;
257 signal chip_dummy_19 : bit;
258 signal chip_dummy_2 : bit;
259 signal chip_dummy_20 : bit;
260 signal chip_dummy_21 : bit;
261 signal chip_dummy_22 : bit;
262 signal chip_dummy_23 : bit;
263 signal chip_dummy_24 : bit;
264 signal chip_dummy_25 : bit;
265 signal chip_dummy_26 : bit;
266 signal chip_dummy_27 : bit;
267 signal chip_dummy_28 : bit;
268 signal chip_dummy_29 : bit;
269 signal chip_dummy_3 : bit;
270 signal chip_dummy_30 : bit;
271 signal chip_dummy_31 : bit;
272 signal chip_dummy_32 : bit;
273 signal chip_dummy_33 : bit;
274 signal chip_dummy_34 : bit;
275 signal chip_dummy_35 : bit;
276 signal chip_dummy_36 : bit;
277 signal chip_dummy_37 : bit;
278 signal chip_dummy_38 : bit;
279 signal chip_dummy_39 : bit;
280 signal chip_dummy_4 : bit;
281 signal chip_dummy_40 : bit;
282 signal chip_dummy_41 : bit;
283 signal chip_dummy_42 : bit;
284 signal chip_dummy_43 : bit;
285 signal chip_dummy_44 : bit;
286 signal chip_dummy_45 : bit;
287 signal chip_dummy_46 : bit;
288 signal chip_dummy_47 : bit;
289 signal chip_dummy_48 : bit;
290 signal chip_dummy_49 : bit;
291 signal chip_dummy_5 : bit;
292 signal chip_dummy_50 : bit;
293 signal chip_dummy_51 : bit;
294 signal chip_dummy_52 : bit;
295 signal chip_dummy_53 : bit;
296 signal chip_dummy_54 : bit;
297 signal chip_dummy_55 : bit;
298 signal chip_dummy_56 : bit;
299 signal chip_dummy_57 : bit;
300 signal chip_dummy_58 : bit;
301 signal chip_dummy_59 : bit;
302 signal chip_dummy_6 : bit;
303 signal chip_dummy_60 : bit;
304 signal chip_dummy_61 : bit;
305 signal chip_dummy_62 : bit;
306 signal chip_dummy_63 : bit;
307 signal chip_dummy_64 : bit;
308 signal chip_dummy_65 : bit;
309 signal chip_dummy_66 : bit;
310 signal chip_dummy_67 : bit;
311 signal chip_dummy_68 : bit;
312 signal chip_dummy_69 : bit;
313 signal chip_dummy_7 : bit;
314 signal chip_dummy_70 : bit;
315 signal chip_dummy_71 : bit;
316 signal chip_dummy_72 : bit;
317 signal chip_dummy_73 : bit;
318 signal chip_dummy_74 : bit;
319 signal chip_dummy_75 : bit;
320 signal chip_dummy_76 : bit;
321 signal chip_dummy_77 : bit;
322 signal chip_dummy_78 : bit;
323 signal chip_dummy_8 : bit;
324 signal chip_dummy_9 : bit;
325 signal eint_0_enable_to_pad : bit;
326 signal eint_1_enable_to_pad : bit;
327 signal eint_2_enable_to_pad : bit;
328 signal i2c_scl_enable_to_pad : bit;
329 signal jtag_tck_enable_to_pad : bit;
330 signal jtag_tdi_enable_to_pad : bit;
331 signal jtag_tdo_enable_to_pad : bit;
332 signal jtag_tms_enable_to_pad : bit;
333 signal nc_0_enable_to_pad : bit;
334 signal nc_10_enable_to_pad : bit;
335 signal nc_11_enable_to_pad : bit;
336 signal nc_12_enable_to_pad : bit;
337 signal nc_13_enable_to_pad : bit;
338 signal nc_14_enable_to_pad : bit;
339 signal nc_15_enable_to_pad : bit;
340 signal nc_16_enable_to_pad : bit;
341 signal nc_17_enable_to_pad : bit;
342 signal nc_18_enable_to_pad : bit;
343 signal nc_19_enable_to_pad : bit;
344 signal nc_1_enable_to_pad : bit;
345 signal nc_20_enable_to_pad : bit;
346 signal nc_21_enable_to_pad : bit;
347 signal nc_22_enable_to_pad : bit;
348 signal nc_23_enable_to_pad : bit;
349 signal nc_24_enable_to_pad : bit;
350 signal nc_25_enable_to_pad : bit;
351 signal nc_26_enable_to_pad : bit;
352 signal nc_27_enable_to_pad : bit;
353 signal nc_28_enable_to_pad : bit;
354 signal nc_29_enable_to_pad : bit;
355 signal nc_2_enable_to_pad : bit;
356 signal nc_30_enable_to_pad : bit;
357 signal nc_31_enable_to_pad : bit;
358 signal nc_32_enable_to_pad : bit;
359 signal nc_33_enable_to_pad : bit;
360 signal nc_34_enable_to_pad : bit;
361 signal nc_35_enable_to_pad : bit;
362 signal nc_36_enable_to_pad : bit;
363 signal nc_37_enable_to_pad : bit;
364 signal nc_38_enable_to_pad : bit;
365 signal nc_39_enable_to_pad : bit;
366 signal nc_3_enable_to_pad : bit;
367 signal nc_4_enable_to_pad : bit;
368 signal nc_5_enable_to_pad : bit;
369 signal nc_6_enable_to_pad : bit;
370 signal nc_7_enable_to_pad : bit;
371 signal nc_8_enable_to_pad : bit;
372 signal nc_9_enable_to_pad : bit;
373 signal sdram_a_0_enable_to_pad : bit;
374 signal sdram_a_10_enable_to_pad : bit;
375 signal sdram_a_11_enable_to_pad : bit;
376 signal sdram_a_12_enable_to_pad : bit;
377 signal sdram_a_1_enable_to_pad : bit;
378 signal sdram_a_2_enable_to_pad : bit;
379 signal sdram_a_3_enable_to_pad : bit;
380 signal sdram_a_4_enable_to_pad : bit;
381 signal sdram_a_5_enable_to_pad : bit;
382 signal sdram_a_6_enable_to_pad : bit;
383 signal sdram_a_7_enable_to_pad : bit;
384 signal sdram_a_8_enable_to_pad : bit;
385 signal sdram_a_9_enable_to_pad : bit;
386 signal sdram_ba_0_enable_to_pad : bit;
387 signal sdram_ba_1_enable_to_pad : bit;
388 signal sdram_cas_n_enable_to_pad : bit;
389 signal sdram_cke_enable_to_pad : bit;
390 signal sdram_clock_enable_to_pad : bit;
391 signal sdram_cs_n_enable_to_pad : bit;
392 signal sdram_dm_0_enable_to_pad : bit;
393 signal sdram_dm_1_enable_to_pad : bit;
394 signal sdram_ras_n_enable_to_pad : bit;
395 signal sdram_we_n_enable_to_pad : bit;
396 signal spimaster_clk_enable_to_pad : bit;
397 signal spimaster_cs_n_enable_to_pad : bit;
398 signal spimaster_miso_enable_to_pad : bit;
399 signal spimaster_mosi_enable_to_pad : bit;
400 signal sys_clk_enable_to_pad : bit;
401 signal sys_rst_enable_to_pad : bit;
402 signal uart_rx_enable_to_pad : bit;
403 signal uart_tx_enable_to_pad : bit;
404
405 begin
406
407 p_sys_rst : cmpt_gpio
408 port map ( i => sys_rst_from_pad
409 , oe => sys_rst_enable_to_pad
410 , o => chip_dummy_73
411 , pad => sys_rst
412 , iovdd => iovdd
413 , iovss => iovss
414 , vdd => vdd
415 , vss => vss
416 );
417
418 p_gpio_15 : cmpt_gpio
419 port map ( i => gpio_o_to_pad(15)
420 , oe => gpio_oe_to_pad(15)
421 , o => gpio_i_from_pad(15)
422 , pad => gpio_15
423 , iovdd => iovdd
424 , iovss => iovss
425 , vdd => vdd
426 , vss => vss
427 );
428
429 p_gpio_14 : cmpt_gpio
430 port map ( i => gpio_o_to_pad(14)
431 , oe => gpio_oe_to_pad(14)
432 , o => gpio_i_from_pad(14)
433 , pad => gpio_14
434 , iovdd => iovdd
435 , iovss => iovss
436 , vdd => vdd
437 , vss => vss
438 );
439
440 p_gpio_13 : cmpt_gpio
441 port map ( i => gpio_o_to_pad(13)
442 , oe => gpio_oe_to_pad(13)
443 , o => gpio_i_from_pad(13)
444 , pad => gpio_13
445 , iovdd => iovdd
446 , iovss => iovss
447 , vdd => vdd
448 , vss => vss
449 );
450
451 p_gpio_12 : cmpt_gpio
452 port map ( i => gpio_o_to_pad(12)
453 , oe => gpio_oe_to_pad(12)
454 , o => gpio_i_from_pad(12)
455 , pad => gpio_12
456 , iovdd => iovdd
457 , iovss => iovss
458 , vdd => vdd
459 , vss => vss
460 );
461
462 p_gpio_11 : cmpt_gpio
463 port map ( i => gpio_o_to_pad(11)
464 , oe => gpio_oe_to_pad(11)
465 , o => gpio_i_from_pad(11)
466 , pad => gpio_11
467 , iovdd => iovdd
468 , iovss => iovss
469 , vdd => vdd
470 , vss => vss
471 );
472
473 p_gpio_10 : cmpt_gpio
474 port map ( i => gpio_o_to_pad(10)
475 , oe => gpio_oe_to_pad(10)
476 , o => gpio_i_from_pad(10)
477 , pad => gpio_10
478 , iovdd => iovdd
479 , iovss => iovss
480 , vdd => vdd
481 , vss => vss
482 );
483
484 p_sdram_dm_1 : cmpt_gpio
485 port map ( i => chip_dummy_3
486 , oe => sdram_dm_1_enable_to_pad
487 , o => sdram_dm_to_pad(1)
488 , pad => sdram_dm(1)
489 , iovdd => iovdd
490 , iovss => iovss
491 , vdd => vdd
492 , vss => vss
493 );
494
495 p_sdram_dm_0 : cmpt_gpio
496 port map ( i => chip_dummy_40
497 , oe => sdram_dm_0_enable_to_pad
498 , o => sdram_dm_to_pad(0)
499 , pad => sdram_dm(0)
500 , iovdd => iovdd
501 , iovss => iovss
502 , vdd => vdd
503 , vss => vss
504 );
505
506 nc_39 : cmpt_gpio
507 port map ( i => nc_from_pad(39)
508 , oe => nc_39_enable_to_pad
509 , o => chip_dummy_78
510 , pad => nc(39)
511 , iovdd => iovdd
512 , iovss => iovss
513 , vdd => vdd
514 , vss => vss
515 );
516
517 nc_38 : cmpt_gpio
518 port map ( i => nc_from_pad(38)
519 , oe => nc_38_enable_to_pad
520 , o => chip_dummy_77
521 , pad => nc(38)
522 , iovdd => iovdd
523 , iovss => iovss
524 , vdd => vdd
525 , vss => vss
526 );
527
528 nc_37 : cmpt_gpio
529 port map ( i => nc_from_pad(37)
530 , oe => nc_37_enable_to_pad
531 , o => chip_dummy_76
532 , pad => nc(37)
533 , iovdd => iovdd
534 , iovss => iovss
535 , vdd => vdd
536 , vss => vss
537 );
538
539 nc_36 : cmpt_gpio
540 port map ( i => nc_from_pad(36)
541 , oe => nc_36_enable_to_pad
542 , o => chip_dummy_75
543 , pad => nc(36)
544 , iovdd => iovdd
545 , iovss => iovss
546 , vdd => vdd
547 , vss => vss
548 );
549
550 nc_35 : cmpt_gpio
551 port map ( i => nc_from_pad(35)
552 , oe => nc_35_enable_to_pad
553 , o => chip_dummy_74
554 , pad => nc(35)
555 , iovdd => iovdd
556 , iovss => iovss
557 , vdd => vdd
558 , vss => vss
559 );
560
561 nc_34 : cmpt_gpio
562 port map ( i => nc_from_pad(34)
563 , oe => nc_34_enable_to_pad
564 , o => chip_dummy_69
565 , pad => nc(34)
566 , iovdd => iovdd
567 , iovss => iovss
568 , vdd => vdd
569 , vss => vss
570 );
571
572 nc_33 : cmpt_gpio
573 port map ( i => nc_from_pad(33)
574 , oe => nc_33_enable_to_pad
575 , o => chip_dummy_64
576 , pad => nc(33)
577 , iovdd => iovdd
578 , iovss => iovss
579 , vdd => vdd
580 , vss => vss
581 );
582
583 nc_32 : cmpt_gpio
584 port map ( i => nc_from_pad(32)
585 , oe => nc_32_enable_to_pad
586 , o => chip_dummy_63
587 , pad => nc(32)
588 , iovdd => iovdd
589 , iovss => iovss
590 , vdd => vdd
591 , vss => vss
592 );
593
594 nc_31 : cmpt_gpio
595 port map ( i => nc_from_pad(31)
596 , oe => nc_31_enable_to_pad
597 , o => chip_dummy_62
598 , pad => nc(31)
599 , iovdd => iovdd
600 , iovss => iovss
601 , vdd => vdd
602 , vss => vss
603 );
604
605 nc_30 : cmpt_gpio
606 port map ( i => nc_from_pad(30)
607 , oe => nc_30_enable_to_pad
608 , o => chip_dummy_61
609 , pad => nc(30)
610 , iovdd => iovdd
611 , iovss => iovss
612 , vdd => vdd
613 , vss => vss
614 );
615
616 p_sdram_dq_7 : cmpt_gpio
617 port map ( i => sdram_dq_o_to_pad(7)
618 , oe => sdram_dq_oe_to_pad(7)
619 , o => sdram_dq_i_from_pad(7)
620 , pad => sdram_dq_7
621 , iovdd => iovdd
622 , iovss => iovss
623 , vdd => vdd
624 , vss => vss
625 );
626
627 p_sdram_dq_9 : cmpt_gpio
628 port map ( i => sdram_dq_o_to_pad(9)
629 , oe => sdram_dq_oe_to_pad(9)
630 , o => sdram_dq_i_from_pad(9)
631 , pad => sdram_dq_9
632 , iovdd => iovdd
633 , iovss => iovss
634 , vdd => vdd
635 , vss => vss
636 );
637
638 p_sdram_dq_8 : cmpt_gpio
639 port map ( i => sdram_dq_o_to_pad(8)
640 , oe => sdram_dq_oe_to_pad(8)
641 , o => sdram_dq_i_from_pad(8)
642 , pad => sdram_dq_8
643 , iovdd => iovdd
644 , iovss => iovss
645 , vdd => vdd
646 , vss => vss
647 );
648
649 p_sdram_dq_0 : cmpt_gpio
650 port map ( i => sdram_dq_o_to_pad(0)
651 , oe => sdram_dq_oe_to_pad(0)
652 , o => sdram_dq_i_from_pad(0)
653 , pad => sdram_dq_0
654 , iovdd => iovdd
655 , iovss => iovss
656 , vdd => vdd
657 , vss => vss
658 );
659
660 p_sdram_dq_1 : cmpt_gpio
661 port map ( i => sdram_dq_o_to_pad(1)
662 , oe => sdram_dq_oe_to_pad(1)
663 , o => sdram_dq_i_from_pad(1)
664 , pad => sdram_dq_1
665 , iovdd => iovdd
666 , iovss => iovss
667 , vdd => vdd
668 , vss => vss
669 );
670
671 p_sdram_dq_2 : cmpt_gpio
672 port map ( i => sdram_dq_o_to_pad(2)
673 , oe => sdram_dq_oe_to_pad(2)
674 , o => sdram_dq_i_from_pad(2)
675 , pad => sdram_dq_2
676 , iovdd => iovdd
677 , iovss => iovss
678 , vdd => vdd
679 , vss => vss
680 );
681
682 p_sdram_dq_3 : cmpt_gpio
683 port map ( i => sdram_dq_o_to_pad(3)
684 , oe => sdram_dq_oe_to_pad(3)
685 , o => sdram_dq_i_from_pad(3)
686 , pad => sdram_dq_3
687 , iovdd => iovdd
688 , iovss => iovss
689 , vdd => vdd
690 , vss => vss
691 );
692
693 p_sdram_dq_4 : cmpt_gpio
694 port map ( i => sdram_dq_o_to_pad(4)
695 , oe => sdram_dq_oe_to_pad(4)
696 , o => sdram_dq_i_from_pad(4)
697 , pad => sdram_dq_4
698 , iovdd => iovdd
699 , iovss => iovss
700 , vdd => vdd
701 , vss => vss
702 );
703
704 p_sdram_dq_5 : cmpt_gpio
705 port map ( i => sdram_dq_o_to_pad(5)
706 , oe => sdram_dq_oe_to_pad(5)
707 , o => sdram_dq_i_from_pad(5)
708 , pad => sdram_dq_5
709 , iovdd => iovdd
710 , iovss => iovss
711 , vdd => vdd
712 , vss => vss
713 );
714
715 p_sdram_dq_6 : cmpt_gpio
716 port map ( i => sdram_dq_o_to_pad(6)
717 , oe => sdram_dq_oe_to_pad(6)
718 , o => sdram_dq_i_from_pad(6)
719 , pad => sdram_dq_6
720 , iovdd => iovdd
721 , iovss => iovss
722 , vdd => vdd
723 , vss => vss
724 );
725
726 p_uart_rx : cmpt_gpio
727 port map ( i => uart_rx_from_pad
728 , oe => uart_rx_enable_to_pad
729 , o => chip_dummy_71
730 , pad => uart_rx
731 , iovdd => iovdd
732 , iovss => iovss
733 , vdd => vdd
734 , vss => vss
735 );
736
737 p_spimaster_mosi : cmpt_gpio
738 port map ( i => chip_dummy_67
739 , oe => spimaster_mosi_enable_to_pad
740 , o => spimaster_mosi_to_pad
741 , pad => spimaster_mosi
742 , iovdd => iovdd
743 , iovss => iovss
744 , vdd => vdd
745 , vss => vss
746 );
747
748 p_sdram_ba_1 : cmpt_gpio
749 port map ( i => chip_dummy_52
750 , oe => sdram_ba_1_enable_to_pad
751 , o => sdram_ba_to_pad(1)
752 , pad => sdram_ba(1)
753 , iovdd => iovdd
754 , iovss => iovss
755 , vdd => vdd
756 , vss => vss
757 );
758
759 p_sdram_ba_0 : cmpt_gpio
760 port map ( i => chip_dummy_51
761 , oe => sdram_ba_0_enable_to_pad
762 , o => sdram_ba_to_pad(0)
763 , pad => sdram_ba(0)
764 , iovdd => iovdd
765 , iovss => iovss
766 , vdd => vdd
767 , vss => vss
768 );
769
770 p_i2c_scl : cmpt_gpio
771 port map ( i => chip_dummy_60
772 , oe => i2c_scl_enable_to_pad
773 , o => i2c_scl_to_pad
774 , pad => i2c_scl
775 , iovdd => iovdd
776 , iovss => iovss
777 , vdd => vdd
778 , vss => vss
779 );
780
781 p_vdd_4 : cmpt_vdd
782 port map ( iovdd => iovdd
783 , iovss => iovss
784 , vdd => vdd
785 , vss => vss
786 );
787
788 p_vdd_1 : cmpt_vdd
789 port map ( iovdd => iovdd
790 , iovss => iovss
791 , vdd => vdd
792 , vss => vss
793 );
794
795 p_vdd_0 : cmpt_vdd
796 port map ( iovdd => iovdd
797 , iovss => iovss
798 , vdd => vdd
799 , vss => vss
800 );
801
802 p_vdd_2 : cmpt_vdd
803 port map ( iovdd => iovdd
804 , iovss => iovss
805 , vdd => vdd
806 , vss => vss
807 );
808
809 p_vdd_3 : cmpt_vdd
810 port map ( iovdd => iovdd
811 , iovss => iovss
812 , vdd => vdd
813 , vss => vss
814 );
815
816 p_sdram_cs_n : cmpt_gpio
817 port map ( i => chip_dummy_58
818 , oe => sdram_cs_n_enable_to_pad
819 , o => sdram_cs_n_to_pad
820 , pad => sdram_cs_n
821 , iovdd => iovdd
822 , iovss => iovss
823 , vdd => vdd
824 , vss => vss
825 );
826
827 p_iovss_0 : cmpt_iovss
828 port map ( iovdd => iovdd
829 , iovss => iovss
830 , vdd => vdd
831 , vss => vss
832 );
833
834 p_iovss_2 : cmpt_iovss
835 port map ( iovdd => iovdd
836 , iovss => iovss
837 , vdd => vdd
838 , vss => vss
839 );
840
841 p_iovss_1 : cmpt_iovss
842 port map ( iovdd => iovdd
843 , iovss => iovss
844 , vdd => vdd
845 , vss => vss
846 );
847
848 p_sys_clk : cmpt_gpio
849 port map ( i => sys_clk_from_pad
850 , oe => sys_clk_enable_to_pad
851 , o => chip_dummy_72
852 , pad => sys_clk
853 , iovdd => iovdd
854 , iovss => iovss
855 , vdd => vdd
856 , vss => vss
857 );
858
859 p_i2c_sda : cmpt_gpio
860 port map ( i => i2c_sda_o_to_pad
861 , oe => i2c_sda_oe_to_pad
862 , o => i2c_sda_i_from_pad
863 , pad => i2c_sda
864 , iovdd => iovdd
865 , iovss => iovss
866 , vdd => vdd
867 , vss => vss
868 );
869
870 p_sdram_a_10 : cmpt_gpio
871 port map ( i => chip_dummy_0
872 , oe => sdram_a_10_enable_to_pad
873 , o => sdram_a_to_pad(10)
874 , pad => sdram_a(10)
875 , iovdd => iovdd
876 , iovss => iovss
877 , vdd => vdd
878 , vss => vss
879 );
880
881 p_sdram_a_11 : cmpt_gpio
882 port map ( i => chip_dummy_1
883 , oe => sdram_a_11_enable_to_pad
884 , o => sdram_a_to_pad(11)
885 , pad => sdram_a(11)
886 , iovdd => iovdd
887 , iovss => iovss
888 , vdd => vdd
889 , vss => vss
890 );
891
892 p_sdram_a_12 : cmpt_gpio
893 port map ( i => chip_dummy_2
894 , oe => sdram_a_12_enable_to_pad
895 , o => sdram_a_to_pad(12)
896 , pad => sdram_a(12)
897 , iovdd => iovdd
898 , iovss => iovss
899 , vdd => vdd
900 , vss => vss
901 );
902
903 p_uart_tx : cmpt_gpio
904 port map ( i => uart_tx_from_pad
905 , oe => uart_tx_enable_to_pad
906 , o => chip_dummy_70
907 , pad => uart_tx
908 , iovdd => iovdd
909 , iovss => iovss
910 , vdd => vdd
911 , vss => vss
912 );
913
914 nc_0 : cmpt_gpio
915 port map ( i => nc_from_pad(0)
916 , oe => nc_0_enable_to_pad
917 , o => chip_dummy_4
918 , pad => nc(0)
919 , iovdd => iovdd
920 , iovss => iovss
921 , vdd => vdd
922 , vss => vss
923 );
924
925 p_jtag_tck : cmpt_gpio
926 port map ( i => jtag_tck_from_pad
927 , oe => jtag_tck_enable_to_pad
928 , o => chip_dummy_8
929 , pad => jtag_tck
930 , iovdd => iovdd
931 , iovss => iovss
932 , vdd => vdd
933 , vss => vss
934 );
935
936 nc_1 : cmpt_gpio
937 port map ( i => nc_from_pad(1)
938 , oe => nc_1_enable_to_pad
939 , o => chip_dummy_9
940 , pad => nc(1)
941 , iovdd => iovdd
942 , iovss => iovss
943 , vdd => vdd
944 , vss => vss
945 );
946
947 nc_2 : cmpt_gpio
948 port map ( i => nc_from_pad(2)
949 , oe => nc_2_enable_to_pad
950 , o => chip_dummy_10
951 , pad => nc(2)
952 , iovdd => iovdd
953 , iovss => iovss
954 , vdd => vdd
955 , vss => vss
956 );
957
958 nc_3 : cmpt_gpio
959 port map ( i => nc_from_pad(3)
960 , oe => nc_3_enable_to_pad
961 , o => chip_dummy_11
962 , pad => nc(3)
963 , iovdd => iovdd
964 , iovss => iovss
965 , vdd => vdd
966 , vss => vss
967 );
968
969 nc_4 : cmpt_gpio
970 port map ( i => nc_from_pad(4)
971 , oe => nc_4_enable_to_pad
972 , o => chip_dummy_12
973 , pad => nc(4)
974 , iovdd => iovdd
975 , iovss => iovss
976 , vdd => vdd
977 , vss => vss
978 );
979
980 nc_5 : cmpt_gpio
981 port map ( i => nc_from_pad(5)
982 , oe => nc_5_enable_to_pad
983 , o => chip_dummy_13
984 , pad => nc(5)
985 , iovdd => iovdd
986 , iovss => iovss
987 , vdd => vdd
988 , vss => vss
989 );
990
991 nc_6 : cmpt_gpio
992 port map ( i => nc_from_pad(6)
993 , oe => nc_6_enable_to_pad
994 , o => chip_dummy_17
995 , pad => nc(6)
996 , iovdd => iovdd
997 , iovss => iovss
998 , vdd => vdd
999 , vss => vss
1000 );
1001
1002 nc_7 : cmpt_gpio
1003 port map ( i => nc_from_pad(7)
1004 , oe => nc_7_enable_to_pad
1005 , o => chip_dummy_18
1006 , pad => nc(7)
1007 , iovdd => iovdd
1008 , iovss => iovss
1009 , vdd => vdd
1010 , vss => vss
1011 );
1012
1013 nc_8 : cmpt_gpio
1014 port map ( i => nc_from_pad(8)
1015 , oe => nc_8_enable_to_pad
1016 , o => chip_dummy_19
1017 , pad => nc(8)
1018 , iovdd => iovdd
1019 , iovss => iovss
1020 , vdd => vdd
1021 , vss => vss
1022 );
1023
1024 nc_9 : cmpt_gpio
1025 port map ( i => nc_from_pad(9)
1026 , oe => nc_9_enable_to_pad
1027 , o => chip_dummy_20
1028 , pad => nc(9)
1029 , iovdd => iovdd
1030 , iovss => iovss
1031 , vdd => vdd
1032 , vss => vss
1033 );
1034
1035 p_sdram_ras_n : cmpt_gpio
1036 port map ( i => chip_dummy_55
1037 , oe => sdram_ras_n_enable_to_pad
1038 , o => sdram_ras_n_to_pad
1039 , pad => sdram_ras_n
1040 , iovdd => iovdd
1041 , iovss => iovss
1042 , vdd => vdd
1043 , vss => vss
1044 );
1045
1046 p_jtag_tdo : cmpt_gpio
1047 port map ( i => chip_dummy_7
1048 , oe => jtag_tdo_enable_to_pad
1049 , o => jtag_tdo_to_pad
1050 , pad => jtag_tdo
1051 , iovdd => iovdd
1052 , iovss => iovss
1053 , vdd => vdd
1054 , vss => vss
1055 );
1056
1057 p_jtag_tdi : cmpt_gpio
1058 port map ( i => jtag_tdi_from_pad
1059 , oe => jtag_tdi_enable_to_pad
1060 , o => chip_dummy_6
1061 , pad => jtag_tdi
1062 , iovdd => iovdd
1063 , iovss => iovss
1064 , vdd => vdd
1065 , vss => vss
1066 );
1067
1068 p_vss_4 : cmpt_vss
1069 port map ( iovdd => iovdd
1070 , iovss => iovss
1071 , vdd => vdd
1072 , vss => vss
1073 );
1074
1075 p_vss_1 : cmpt_vss
1076 port map ( iovdd => iovdd
1077 , iovss => iovss
1078 , vdd => vdd
1079 , vss => vss
1080 );
1081
1082 p_vss_0 : cmpt_vss
1083 port map ( iovdd => iovdd
1084 , iovss => iovss
1085 , vdd => vdd
1086 , vss => vss
1087 );
1088
1089 p_vss_2 : cmpt_vss
1090 port map ( iovdd => iovdd
1091 , iovss => iovss
1092 , vdd => vdd
1093 , vss => vss
1094 );
1095
1096 p_vss_3 : cmpt_vss
1097 port map ( iovdd => iovdd
1098 , iovss => iovss
1099 , vdd => vdd
1100 , vss => vss
1101 );
1102
1103 p_spimaster_miso : cmpt_gpio
1104 port map ( i => spimaster_miso_from_pad
1105 , oe => spimaster_miso_enable_to_pad
1106 , o => chip_dummy_68
1107 , pad => spimaster_miso
1108 , iovdd => iovdd
1109 , iovss => iovss
1110 , vdd => vdd
1111 , vss => vss
1112 );
1113
1114 p_spimaster_cs_n : cmpt_gpio
1115 port map ( i => chip_dummy_66
1116 , oe => spimaster_cs_n_enable_to_pad
1117 , o => spimaster_cs_n_to_pad
1118 , pad => spimaster_cs_n
1119 , iovdd => iovdd
1120 , iovss => iovss
1121 , vdd => vdd
1122 , vss => vss
1123 );
1124
1125 p_spimaster_clk : cmpt_gpio
1126 port map ( i => chip_dummy_65
1127 , oe => spimaster_clk_enable_to_pad
1128 , o => spimaster_clk_to_pad
1129 , pad => spimaster_clk
1130 , iovdd => iovdd
1131 , iovss => iovss
1132 , vdd => vdd
1133 , vss => vss
1134 );
1135
1136 p_sdram_we_n : cmpt_gpio
1137 port map ( i => chip_dummy_57
1138 , oe => sdram_we_n_enable_to_pad
1139 , o => sdram_we_n_to_pad
1140 , pad => sdram_we_n
1141 , iovdd => iovdd
1142 , iovss => iovss
1143 , vdd => vdd
1144 , vss => vss
1145 );
1146
1147 p_sdram_a_6 : cmpt_gpio
1148 port map ( i => chip_dummy_47
1149 , oe => sdram_a_6_enable_to_pad
1150 , o => sdram_a_to_pad(6)
1151 , pad => sdram_a(6)
1152 , iovdd => iovdd
1153 , iovss => iovss
1154 , vdd => vdd
1155 , vss => vss
1156 );
1157
1158 p_sdram_a_5 : cmpt_gpio
1159 port map ( i => chip_dummy_46
1160 , oe => sdram_a_5_enable_to_pad
1161 , o => sdram_a_to_pad(5)
1162 , pad => sdram_a(5)
1163 , iovdd => iovdd
1164 , iovss => iovss
1165 , vdd => vdd
1166 , vss => vss
1167 );
1168
1169 p_sdram_a_4 : cmpt_gpio
1170 port map ( i => chip_dummy_45
1171 , oe => sdram_a_4_enable_to_pad
1172 , o => sdram_a_to_pad(4)
1173 , pad => sdram_a(4)
1174 , iovdd => iovdd
1175 , iovss => iovss
1176 , vdd => vdd
1177 , vss => vss
1178 );
1179
1180 p_sdram_a_3 : cmpt_gpio
1181 port map ( i => chip_dummy_44
1182 , oe => sdram_a_3_enable_to_pad
1183 , o => sdram_a_to_pad(3)
1184 , pad => sdram_a(3)
1185 , iovdd => iovdd
1186 , iovss => iovss
1187 , vdd => vdd
1188 , vss => vss
1189 );
1190
1191 p_sdram_a_2 : cmpt_gpio
1192 port map ( i => chip_dummy_43
1193 , oe => sdram_a_2_enable_to_pad
1194 , o => sdram_a_to_pad(2)
1195 , pad => sdram_a(2)
1196 , iovdd => iovdd
1197 , iovss => iovss
1198 , vdd => vdd
1199 , vss => vss
1200 );
1201
1202 p_sdram_a_1 : cmpt_gpio
1203 port map ( i => chip_dummy_42
1204 , oe => sdram_a_1_enable_to_pad
1205 , o => sdram_a_to_pad(1)
1206 , pad => sdram_a(1)
1207 , iovdd => iovdd
1208 , iovss => iovss
1209 , vdd => vdd
1210 , vss => vss
1211 );
1212
1213 p_sdram_a_0 : cmpt_gpio
1214 port map ( i => chip_dummy_41
1215 , oe => sdram_a_0_enable_to_pad
1216 , o => sdram_a_to_pad(0)
1217 , pad => sdram_a(0)
1218 , iovdd => iovdd
1219 , iovss => iovss
1220 , vdd => vdd
1221 , vss => vss
1222 );
1223
1224 p_sdram_a_9 : cmpt_gpio
1225 port map ( i => chip_dummy_50
1226 , oe => sdram_a_9_enable_to_pad
1227 , o => sdram_a_to_pad(9)
1228 , pad => sdram_a(9)
1229 , iovdd => iovdd
1230 , iovss => iovss
1231 , vdd => vdd
1232 , vss => vss
1233 );
1234
1235 p_sdram_a_8 : cmpt_gpio
1236 port map ( i => chip_dummy_49
1237 , oe => sdram_a_8_enable_to_pad
1238 , o => sdram_a_to_pad(8)
1239 , pad => sdram_a(8)
1240 , iovdd => iovdd
1241 , iovss => iovss
1242 , vdd => vdd
1243 , vss => vss
1244 );
1245
1246 p_sdram_a_7 : cmpt_gpio
1247 port map ( i => chip_dummy_48
1248 , oe => sdram_a_7_enable_to_pad
1249 , o => sdram_a_to_pad(7)
1250 , pad => sdram_a(7)
1251 , iovdd => iovdd
1252 , iovss => iovss
1253 , vdd => vdd
1254 , vss => vss
1255 );
1256
1257 p_jtag_tms : cmpt_gpio
1258 port map ( i => jtag_tms_from_pad
1259 , oe => jtag_tms_enable_to_pad
1260 , o => chip_dummy_5
1261 , pad => jtag_tms
1262 , iovdd => iovdd
1263 , iovss => iovss
1264 , vdd => vdd
1265 , vss => vss
1266 );
1267
1268 p_sdram_cke : cmpt_gpio
1269 port map ( i => chip_dummy_54
1270 , oe => sdram_cke_enable_to_pad
1271 , o => sdram_cke_to_pad
1272 , pad => sdram_cke
1273 , iovdd => iovdd
1274 , iovss => iovss
1275 , vdd => vdd
1276 , vss => vss
1277 );
1278
1279 corona : corona_cts_r
1280 port map ( eint_0_from_pad => eint_0_from_pad
1281 , eint_1_from_pad => eint_1_from_pad
1282 , eint_2_from_pad => eint_2_from_pad
1283 , i2c_sda_i_from_pad => i2c_sda_i_from_pad
1284 , jtag_tck_from_pad => jtag_tck_from_pad
1285 , jtag_tdi_from_pad => jtag_tdi_from_pad
1286 , jtag_tms_from_pad => jtag_tms_from_pad
1287 , spimaster_miso_from_pad => spimaster_miso_from_pad
1288 , sys_clk_from_pad => sys_clk_from_pad
1289 , sys_rst_from_pad => sys_rst_from_pad
1290 , uart_rx_from_pad => uart_rx_from_pad
1291 , uart_tx_from_pad => uart_tx_from_pad
1292 , gpio_i_from_pad => gpio_i_from_pad(15 downto 0)
1293 , sdram_dq_i_from_pad => sdram_dq_i_from_pad(15 downto 0)
1294 , nc_from_pad => nc_from_pad(39 downto 0)
1295 , eint_0_enable_to_pad => eint_0_enable_to_pad
1296 , eint_1_enable_to_pad => eint_1_enable_to_pad
1297 , eint_2_enable_to_pad => eint_2_enable_to_pad
1298 , i2c_scl_enable_to_pad => i2c_scl_enable_to_pad
1299 , i2c_scl_to_pad => i2c_scl_to_pad
1300 , i2c_sda_o_to_pad => i2c_sda_o_to_pad
1301 , i2c_sda_oe_to_pad => i2c_sda_oe_to_pad
1302 , jtag_tck_enable_to_pad => jtag_tck_enable_to_pad
1303 , jtag_tdi_enable_to_pad => jtag_tdi_enable_to_pad
1304 , jtag_tdo_enable_to_pad => jtag_tdo_enable_to_pad
1305 , jtag_tdo_to_pad => jtag_tdo_to_pad
1306 , jtag_tms_enable_to_pad => jtag_tms_enable_to_pad
1307 , nc_0_enable_to_pad => nc_0_enable_to_pad
1308 , nc_10_enable_to_pad => nc_10_enable_to_pad
1309 , nc_11_enable_to_pad => nc_11_enable_to_pad
1310 , nc_12_enable_to_pad => nc_12_enable_to_pad
1311 , nc_13_enable_to_pad => nc_13_enable_to_pad
1312 , nc_14_enable_to_pad => nc_14_enable_to_pad
1313 , nc_15_enable_to_pad => nc_15_enable_to_pad
1314 , nc_16_enable_to_pad => nc_16_enable_to_pad
1315 , nc_17_enable_to_pad => nc_17_enable_to_pad
1316 , nc_18_enable_to_pad => nc_18_enable_to_pad
1317 , nc_19_enable_to_pad => nc_19_enable_to_pad
1318 , nc_1_enable_to_pad => nc_1_enable_to_pad
1319 , nc_20_enable_to_pad => nc_20_enable_to_pad
1320 , nc_21_enable_to_pad => nc_21_enable_to_pad
1321 , nc_22_enable_to_pad => nc_22_enable_to_pad
1322 , nc_23_enable_to_pad => nc_23_enable_to_pad
1323 , nc_24_enable_to_pad => nc_24_enable_to_pad
1324 , nc_25_enable_to_pad => nc_25_enable_to_pad
1325 , nc_26_enable_to_pad => nc_26_enable_to_pad
1326 , nc_27_enable_to_pad => nc_27_enable_to_pad
1327 , nc_28_enable_to_pad => nc_28_enable_to_pad
1328 , nc_29_enable_to_pad => nc_29_enable_to_pad
1329 , nc_2_enable_to_pad => nc_2_enable_to_pad
1330 , nc_30_enable_to_pad => nc_30_enable_to_pad
1331 , nc_31_enable_to_pad => nc_31_enable_to_pad
1332 , nc_32_enable_to_pad => nc_32_enable_to_pad
1333 , nc_33_enable_to_pad => nc_33_enable_to_pad
1334 , nc_34_enable_to_pad => nc_34_enable_to_pad
1335 , nc_35_enable_to_pad => nc_35_enable_to_pad
1336 , nc_36_enable_to_pad => nc_36_enable_to_pad
1337 , nc_37_enable_to_pad => nc_37_enable_to_pad
1338 , nc_38_enable_to_pad => nc_38_enable_to_pad
1339 , nc_39_enable_to_pad => nc_39_enable_to_pad
1340 , nc_3_enable_to_pad => nc_3_enable_to_pad
1341 , nc_4_enable_to_pad => nc_4_enable_to_pad
1342 , nc_5_enable_to_pad => nc_5_enable_to_pad
1343 , nc_6_enable_to_pad => nc_6_enable_to_pad
1344 , nc_7_enable_to_pad => nc_7_enable_to_pad
1345 , nc_8_enable_to_pad => nc_8_enable_to_pad
1346 , nc_9_enable_to_pad => nc_9_enable_to_pad
1347 , sdram_a_0_enable_to_pad => sdram_a_0_enable_to_pad
1348 , sdram_a_10_enable_to_pad => sdram_a_10_enable_to_pad
1349 , sdram_a_11_enable_to_pad => sdram_a_11_enable_to_pad
1350 , sdram_a_12_enable_to_pad => sdram_a_12_enable_to_pad
1351 , sdram_a_1_enable_to_pad => sdram_a_1_enable_to_pad
1352 , sdram_a_2_enable_to_pad => sdram_a_2_enable_to_pad
1353 , sdram_a_3_enable_to_pad => sdram_a_3_enable_to_pad
1354 , sdram_a_4_enable_to_pad => sdram_a_4_enable_to_pad
1355 , sdram_a_5_enable_to_pad => sdram_a_5_enable_to_pad
1356 , sdram_a_6_enable_to_pad => sdram_a_6_enable_to_pad
1357 , sdram_a_7_enable_to_pad => sdram_a_7_enable_to_pad
1358 , sdram_a_8_enable_to_pad => sdram_a_8_enable_to_pad
1359 , sdram_a_9_enable_to_pad => sdram_a_9_enable_to_pad
1360 , sdram_ba_0_enable_to_pad => sdram_ba_0_enable_to_pad
1361 , sdram_ba_1_enable_to_pad => sdram_ba_1_enable_to_pad
1362 , sdram_cas_n_enable_to_pad => sdram_cas_n_enable_to_pad
1363 , sdram_cas_n_to_pad => sdram_cas_n_to_pad
1364 , sdram_cke_enable_to_pad => sdram_cke_enable_to_pad
1365 , sdram_cke_to_pad => sdram_cke_to_pad
1366 , sdram_clock_enable_to_pad => sdram_clock_enable_to_pad
1367 , sdram_clock_to_pad => sdram_clock_to_pad
1368 , sdram_cs_n_enable_to_pad => sdram_cs_n_enable_to_pad
1369 , sdram_cs_n_to_pad => sdram_cs_n_to_pad
1370 , sdram_dm_0_enable_to_pad => sdram_dm_0_enable_to_pad
1371 , sdram_dm_1_enable_to_pad => sdram_dm_1_enable_to_pad
1372 , sdram_ras_n_enable_to_pad => sdram_ras_n_enable_to_pad
1373 , sdram_ras_n_to_pad => sdram_ras_n_to_pad
1374 , sdram_we_n_enable_to_pad => sdram_we_n_enable_to_pad
1375 , sdram_we_n_to_pad => sdram_we_n_to_pad
1376 , spimaster_clk_enable_to_pad => spimaster_clk_enable_to_pad
1377 , spimaster_clk_to_pad => spimaster_clk_to_pad
1378 , spimaster_cs_n_enable_to_pad => spimaster_cs_n_enable_to_pad
1379 , spimaster_cs_n_to_pad => spimaster_cs_n_to_pad
1380 , spimaster_miso_enable_to_pad => spimaster_miso_enable_to_pad
1381 , spimaster_mosi_enable_to_pad => spimaster_mosi_enable_to_pad
1382 , spimaster_mosi_to_pad => spimaster_mosi_to_pad
1383 , sys_clk_enable_to_pad => sys_clk_enable_to_pad
1384 , sys_rst_enable_to_pad => sys_rst_enable_to_pad
1385 , uart_rx_enable_to_pad => uart_rx_enable_to_pad
1386 , uart_tx_enable_to_pad => uart_tx_enable_to_pad
1387 , sdram_ba_to_pad => sdram_ba_to_pad(1 downto 0)
1388 , sdram_dm_to_pad => sdram_dm_to_pad(1 downto 0)
1389 , sdram_a_to_pad => sdram_a_to_pad(12 downto 0)
1390 , gpio_o_to_pad => gpio_o_to_pad(15 downto 0)
1391 , gpio_oe_to_pad => gpio_oe_to_pad(15 downto 0)
1392 , sdram_dq_o_to_pad => sdram_dq_o_to_pad(15 downto 0)
1393 , sdram_dq_oe_to_pad => sdram_dq_oe_to_pad(15 downto 0)
1394 , vdd => vdd
1395 , vss => vss
1396 );
1397
1398 p_gpio_7 : cmpt_gpio
1399 port map ( i => gpio_o_to_pad(7)
1400 , oe => gpio_oe_to_pad(7)
1401 , o => gpio_i_from_pad(7)
1402 , pad => gpio_7
1403 , iovdd => iovdd
1404 , iovss => iovss
1405 , vdd => vdd
1406 , vss => vss
1407 );
1408
1409 p_gpio_6 : cmpt_gpio
1410 port map ( i => gpio_o_to_pad(6)
1411 , oe => gpio_oe_to_pad(6)
1412 , o => gpio_i_from_pad(6)
1413 , pad => gpio_6
1414 , iovdd => iovdd
1415 , iovss => iovss
1416 , vdd => vdd
1417 , vss => vss
1418 );
1419
1420 p_gpio_5 : cmpt_gpio
1421 port map ( i => gpio_o_to_pad(5)
1422 , oe => gpio_oe_to_pad(5)
1423 , o => gpio_i_from_pad(5)
1424 , pad => gpio_5
1425 , iovdd => iovdd
1426 , iovss => iovss
1427 , vdd => vdd
1428 , vss => vss
1429 );
1430
1431 p_gpio_4 : cmpt_gpio
1432 port map ( i => gpio_o_to_pad(4)
1433 , oe => gpio_oe_to_pad(4)
1434 , o => gpio_i_from_pad(4)
1435 , pad => gpio_4
1436 , iovdd => iovdd
1437 , iovss => iovss
1438 , vdd => vdd
1439 , vss => vss
1440 );
1441
1442 p_gpio_3 : cmpt_gpio
1443 port map ( i => gpio_o_to_pad(3)
1444 , oe => gpio_oe_to_pad(3)
1445 , o => gpio_i_from_pad(3)
1446 , pad => gpio_3
1447 , iovdd => iovdd
1448 , iovss => iovss
1449 , vdd => vdd
1450 , vss => vss
1451 );
1452
1453 p_gpio_2 : cmpt_gpio
1454 port map ( i => gpio_o_to_pad(2)
1455 , oe => gpio_oe_to_pad(2)
1456 , o => gpio_i_from_pad(2)
1457 , pad => gpio_2
1458 , iovdd => iovdd
1459 , iovss => iovss
1460 , vdd => vdd
1461 , vss => vss
1462 );
1463
1464 p_gpio_1 : cmpt_gpio
1465 port map ( i => gpio_o_to_pad(1)
1466 , oe => gpio_oe_to_pad(1)
1467 , o => gpio_i_from_pad(1)
1468 , pad => gpio_1
1469 , iovdd => iovdd
1470 , iovss => iovss
1471 , vdd => vdd
1472 , vss => vss
1473 );
1474
1475 p_gpio_0 : cmpt_gpio
1476 port map ( i => gpio_o_to_pad(0)
1477 , oe => gpio_oe_to_pad(0)
1478 , o => gpio_i_from_pad(0)
1479 , pad => gpio_0
1480 , iovdd => iovdd
1481 , iovss => iovss
1482 , vdd => vdd
1483 , vss => vss
1484 );
1485
1486 p_sdram_clock : cmpt_gpio
1487 port map ( i => chip_dummy_53
1488 , oe => sdram_clock_enable_to_pad
1489 , o => sdram_clock_to_pad
1490 , pad => sdram_clock
1491 , iovdd => iovdd
1492 , iovss => iovss
1493 , vdd => vdd
1494 , vss => vss
1495 );
1496
1497 p_gpio_9 : cmpt_gpio
1498 port map ( i => gpio_o_to_pad(9)
1499 , oe => gpio_oe_to_pad(9)
1500 , o => gpio_i_from_pad(9)
1501 , pad => gpio_9
1502 , iovdd => iovdd
1503 , iovss => iovss
1504 , vdd => vdd
1505 , vss => vss
1506 );
1507
1508 p_gpio_8 : cmpt_gpio
1509 port map ( i => gpio_o_to_pad(8)
1510 , oe => gpio_oe_to_pad(8)
1511 , o => gpio_i_from_pad(8)
1512 , pad => gpio_8
1513 , iovdd => iovdd
1514 , iovss => iovss
1515 , vdd => vdd
1516 , vss => vss
1517 );
1518
1519 p_sdram_dq_15 : cmpt_gpio
1520 port map ( i => sdram_dq_o_to_pad(15)
1521 , oe => sdram_dq_oe_to_pad(15)
1522 , o => sdram_dq_i_from_pad(15)
1523 , pad => sdram_dq_15
1524 , iovdd => iovdd
1525 , iovss => iovss
1526 , vdd => vdd
1527 , vss => vss
1528 );
1529
1530 p_sdram_dq_14 : cmpt_gpio
1531 port map ( i => sdram_dq_o_to_pad(14)
1532 , oe => sdram_dq_oe_to_pad(14)
1533 , o => sdram_dq_i_from_pad(14)
1534 , pad => sdram_dq_14
1535 , iovdd => iovdd
1536 , iovss => iovss
1537 , vdd => vdd
1538 , vss => vss
1539 );
1540
1541 p_sdram_dq_13 : cmpt_gpio
1542 port map ( i => sdram_dq_o_to_pad(13)
1543 , oe => sdram_dq_oe_to_pad(13)
1544 , o => sdram_dq_i_from_pad(13)
1545 , pad => sdram_dq_13
1546 , iovdd => iovdd
1547 , iovss => iovss
1548 , vdd => vdd
1549 , vss => vss
1550 );
1551
1552 p_sdram_dq_12 : cmpt_gpio
1553 port map ( i => sdram_dq_o_to_pad(12)
1554 , oe => sdram_dq_oe_to_pad(12)
1555 , o => sdram_dq_i_from_pad(12)
1556 , pad => sdram_dq_12
1557 , iovdd => iovdd
1558 , iovss => iovss
1559 , vdd => vdd
1560 , vss => vss
1561 );
1562
1563 p_sdram_dq_11 : cmpt_gpio
1564 port map ( i => sdram_dq_o_to_pad(11)
1565 , oe => sdram_dq_oe_to_pad(11)
1566 , o => sdram_dq_i_from_pad(11)
1567 , pad => sdram_dq_11
1568 , iovdd => iovdd
1569 , iovss => iovss
1570 , vdd => vdd
1571 , vss => vss
1572 );
1573
1574 p_sdram_dq_10 : cmpt_gpio
1575 port map ( i => sdram_dq_o_to_pad(10)
1576 , oe => sdram_dq_oe_to_pad(10)
1577 , o => sdram_dq_i_from_pad(10)
1578 , pad => sdram_dq_10
1579 , iovdd => iovdd
1580 , iovss => iovss
1581 , vdd => vdd
1582 , vss => vss
1583 );
1584
1585 p_eint_0 : cmpt_gpio
1586 port map ( i => eint_0_from_pad
1587 , oe => eint_0_enable_to_pad
1588 , o => chip_dummy_14
1589 , pad => eint_0
1590 , iovdd => iovdd
1591 , iovss => iovss
1592 , vdd => vdd
1593 , vss => vss
1594 );
1595
1596 p_eint_1 : cmpt_gpio
1597 port map ( i => eint_1_from_pad
1598 , oe => eint_1_enable_to_pad
1599 , o => chip_dummy_15
1600 , pad => eint_1
1601 , iovdd => iovdd
1602 , iovss => iovss
1603 , vdd => vdd
1604 , vss => vss
1605 );
1606
1607 p_eint_2 : cmpt_gpio
1608 port map ( i => eint_2_from_pad
1609 , oe => eint_2_enable_to_pad
1610 , o => chip_dummy_16
1611 , pad => eint_2
1612 , iovdd => iovdd
1613 , iovss => iovss
1614 , vdd => vdd
1615 , vss => vss
1616 );
1617
1618 nc_10 : cmpt_gpio
1619 port map ( i => nc_from_pad(10)
1620 , oe => nc_10_enable_to_pad
1621 , o => chip_dummy_21
1622 , pad => nc(10)
1623 , iovdd => iovdd
1624 , iovss => iovss
1625 , vdd => vdd
1626 , vss => vss
1627 );
1628
1629 nc_11 : cmpt_gpio
1630 port map ( i => nc_from_pad(11)
1631 , oe => nc_11_enable_to_pad
1632 , o => chip_dummy_22
1633 , pad => nc(11)
1634 , iovdd => iovdd
1635 , iovss => iovss
1636 , vdd => vdd
1637 , vss => vss
1638 );
1639
1640 nc_12 : cmpt_gpio
1641 port map ( i => nc_from_pad(12)
1642 , oe => nc_12_enable_to_pad
1643 , o => chip_dummy_23
1644 , pad => nc(12)
1645 , iovdd => iovdd
1646 , iovss => iovss
1647 , vdd => vdd
1648 , vss => vss
1649 );
1650
1651 nc_13 : cmpt_gpio
1652 port map ( i => nc_from_pad(13)
1653 , oe => nc_13_enable_to_pad
1654 , o => chip_dummy_24
1655 , pad => nc(13)
1656 , iovdd => iovdd
1657 , iovss => iovss
1658 , vdd => vdd
1659 , vss => vss
1660 );
1661
1662 nc_14 : cmpt_gpio
1663 port map ( i => nc_from_pad(14)
1664 , oe => nc_14_enable_to_pad
1665 , o => chip_dummy_25
1666 , pad => nc(14)
1667 , iovdd => iovdd
1668 , iovss => iovss
1669 , vdd => vdd
1670 , vss => vss
1671 );
1672
1673 nc_15 : cmpt_gpio
1674 port map ( i => nc_from_pad(15)
1675 , oe => nc_15_enable_to_pad
1676 , o => chip_dummy_26
1677 , pad => nc(15)
1678 , iovdd => iovdd
1679 , iovss => iovss
1680 , vdd => vdd
1681 , vss => vss
1682 );
1683
1684 nc_16 : cmpt_gpio
1685 port map ( i => nc_from_pad(16)
1686 , oe => nc_16_enable_to_pad
1687 , o => chip_dummy_27
1688 , pad => nc(16)
1689 , iovdd => iovdd
1690 , iovss => iovss
1691 , vdd => vdd
1692 , vss => vss
1693 );
1694
1695 nc_17 : cmpt_gpio
1696 port map ( i => nc_from_pad(17)
1697 , oe => nc_17_enable_to_pad
1698 , o => chip_dummy_28
1699 , pad => nc(17)
1700 , iovdd => iovdd
1701 , iovss => iovss
1702 , vdd => vdd
1703 , vss => vss
1704 );
1705
1706 nc_18 : cmpt_gpio
1707 port map ( i => nc_from_pad(18)
1708 , oe => nc_18_enable_to_pad
1709 , o => chip_dummy_29
1710 , pad => nc(18)
1711 , iovdd => iovdd
1712 , iovss => iovss
1713 , vdd => vdd
1714 , vss => vss
1715 );
1716
1717 nc_19 : cmpt_gpio
1718 port map ( i => nc_from_pad(19)
1719 , oe => nc_19_enable_to_pad
1720 , o => chip_dummy_30
1721 , pad => nc(19)
1722 , iovdd => iovdd
1723 , iovss => iovss
1724 , vdd => vdd
1725 , vss => vss
1726 );
1727
1728 p_sdram_cas_n : cmpt_gpio
1729 port map ( i => chip_dummy_56
1730 , oe => sdram_cas_n_enable_to_pad
1731 , o => sdram_cas_n_to_pad
1732 , pad => sdram_cas_n
1733 , iovdd => iovdd
1734 , iovss => iovss
1735 , vdd => vdd
1736 , vss => vss
1737 );
1738
1739 p_iovdd_0 : cmpt_iovdd
1740 port map ( iovdd => iovdd
1741 , iovss => iovss
1742 , vdd => vdd
1743 , vss => vss
1744 );
1745
1746 p_iovdd_2 : cmpt_iovdd
1747 port map ( iovdd => iovdd
1748 , iovss => iovss
1749 , vdd => vdd
1750 , vss => vss
1751 );
1752
1753 p_iovdd_1 : cmpt_iovdd
1754 port map ( iovdd => iovdd
1755 , iovss => iovss
1756 , vdd => vdd
1757 , vss => vss
1758 );
1759
1760 nc_29 : cmpt_gpio
1761 port map ( i => nc_from_pad(29)
1762 , oe => nc_29_enable_to_pad
1763 , o => chip_dummy_59
1764 , pad => nc(29)
1765 , iovdd => iovdd
1766 , iovss => iovss
1767 , vdd => vdd
1768 , vss => vss
1769 );
1770
1771 nc_20 : cmpt_gpio
1772 port map ( i => nc_from_pad(20)
1773 , oe => nc_20_enable_to_pad
1774 , o => chip_dummy_31
1775 , pad => nc(20)
1776 , iovdd => iovdd
1777 , iovss => iovss
1778 , vdd => vdd
1779 , vss => vss
1780 );
1781
1782 nc_21 : cmpt_gpio
1783 port map ( i => nc_from_pad(21)
1784 , oe => nc_21_enable_to_pad
1785 , o => chip_dummy_32
1786 , pad => nc(21)
1787 , iovdd => iovdd
1788 , iovss => iovss
1789 , vdd => vdd
1790 , vss => vss
1791 );
1792
1793 nc_22 : cmpt_gpio
1794 port map ( i => nc_from_pad(22)
1795 , oe => nc_22_enable_to_pad
1796 , o => chip_dummy_33
1797 , pad => nc(22)
1798 , iovdd => iovdd
1799 , iovss => iovss
1800 , vdd => vdd
1801 , vss => vss
1802 );
1803
1804 nc_23 : cmpt_gpio
1805 port map ( i => nc_from_pad(23)
1806 , oe => nc_23_enable_to_pad
1807 , o => chip_dummy_34
1808 , pad => nc(23)
1809 , iovdd => iovdd
1810 , iovss => iovss
1811 , vdd => vdd
1812 , vss => vss
1813 );
1814
1815 nc_24 : cmpt_gpio
1816 port map ( i => nc_from_pad(24)
1817 , oe => nc_24_enable_to_pad
1818 , o => chip_dummy_35
1819 , pad => nc(24)
1820 , iovdd => iovdd
1821 , iovss => iovss
1822 , vdd => vdd
1823 , vss => vss
1824 );
1825
1826 nc_25 : cmpt_gpio
1827 port map ( i => nc_from_pad(25)
1828 , oe => nc_25_enable_to_pad
1829 , o => chip_dummy_36
1830 , pad => nc(25)
1831 , iovdd => iovdd
1832 , iovss => iovss
1833 , vdd => vdd
1834 , vss => vss
1835 );
1836
1837 nc_26 : cmpt_gpio
1838 port map ( i => nc_from_pad(26)
1839 , oe => nc_26_enable_to_pad
1840 , o => chip_dummy_37
1841 , pad => nc(26)
1842 , iovdd => iovdd
1843 , iovss => iovss
1844 , vdd => vdd
1845 , vss => vss
1846 );
1847
1848 nc_27 : cmpt_gpio
1849 port map ( i => nc_from_pad(27)
1850 , oe => nc_27_enable_to_pad
1851 , o => chip_dummy_38
1852 , pad => nc(27)
1853 , iovdd => iovdd
1854 , iovss => iovss
1855 , vdd => vdd
1856 , vss => vss
1857 );
1858
1859 nc_28 : cmpt_gpio
1860 port map ( i => nc_from_pad(28)
1861 , oe => nc_28_enable_to_pad
1862 , o => chip_dummy_39
1863 , pad => nc(28)
1864 , iovdd => iovdd
1865 , iovss => iovss
1866 , vdd => vdd
1867 , vss => vss
1868 );
1869
1870 end structural;
1871