ls180/post_pnr/cocotb/test.py

   1 import cocotb
   2 from cocotb.clock import Clock
   3 from cocotb.triggers import Timer
   4 from cocotb.utils import get_sim_steps
   5 from cocotb.binary import BinaryValue
   6
   7 from c4m.cocotb.jtag.c4m_jtag import JTAG_Master
   8 from c4m.cocotb.jtag.c4m_jtag_svfcocotb import SVF_Executor
   9
  10 #
  11 # Helper functions
  12 #
  13
  14 def setup_sim(dut, *, clk_period, run):
  15     """Initialize CPU and setup clock"""
  16
  17     clk_steps = get_sim_steps(clk_period, "ns")
  18     cocotb.fork(Clock(dut.sys_clk, clk_steps).start())
  19
  20     dut.vdd <= 1
  21     dut.vss <= 0
  22     dut.iovdd <= 1
  23     dut.iovss <= 0
  24     dut.sys_rst <= 1
  25     dut.sys_clk <= 0
  26     if run:
  27         yield Timer(int(10.5*clk_steps))
  28         dut.sys_rst <= 0
  29         yield Timer(int(5*clk_steps))
  30
  31 def setup_jtag(dut, *, tck_period):
  32     # Make this a generator
  33     if False:
  34         yield Timer(0)
  35     return JTAG_Master(dut.jtag_tck, dut.jtag_tms,
  36                        dut.jtag_tdi, dut.jtag_tdo,
  37                        clk_period=tck_period,
  38                        ir_width=4)
  39
  40 def execute_svf(dut, *, jtag, svf_filename):
  41     jtag_svf = SVF_Executor(jtag)
  42     with open(svf_filename, "r") as f:
  43         svf_deck = f.read()
  44     yield jtag_svf.run(svf_deck, p=dut._log.info)
  45
  46 #
  47 # IDCODE using JTAG_master
  48 #
  49
  50 def idcode(dut, *, jtag):
  51     #jtag.IDCODE = [0, 0, 0, 1]
  52     yield jtag.idcode()
  53     result1 = jtag.result
  54     dut._log.info("IDCODE1: {}".format(result1))
  55     assert(result1 == BinaryValue("00000000000000000001100011111111"))
  56
  57     yield jtag.idcode()
  58     result2 = jtag.result
  59     dut._log.info("IDCODE2: {}".format(result2))
  60
  61     assert(result1 == result2)
  62
  63 @cocotb.test()
  64 def idcode_reset(dut):
  65     dut._log.info("Running IDCODE test; cpu in reset...")
  66
  67     clk_period = 100 # 10MHz
  68     tck_period = 300 # 3MHz
  69
  70     yield from setup_sim(dut, clk_period=clk_period, run=False)
  71     jtag = yield from setup_jtag(dut, tck_period = tck_period)
  72
  73     yield from idcode(dut, jtag=jtag)
  74
  75     dut._log.info("IDCODE test completed")
  76
  77 @cocotb.test()
  78 def idcode_run(dut):
  79     dut._log.info("Running IDCODE test; cpu running...")
  80
  81     clk_period = 100 # 10MHz
  82     tck_period = 300 # 3MHz
  83
  84     yield from setup_sim(dut, clk_period=clk_period, run=True)
  85     jtag = yield from setup_jtag(dut, tck_period = tck_period)
  86
  87     yield from idcode(dut, jtag=jtag)
  88
  89     dut._log.info("IDCODE test completed")
  90
  91 #
  92 # Read IDCODE from SVF file
  93 #
  94
  95 @cocotb.test()
  96 def idcodesvf_reset(dut):
  97     dut._log.info("Running IDCODE through SVF test; cpu in reset...")
  98
  99     clk_period = 100 # 10MHz
 100     tck_period = 300 # 3MHz
 101
 102     yield from setup_sim(dut, clk_period=clk_period, run=False)
 103     jtag = yield from setup_jtag(dut, tck_period = tck_period)
 104
 105     yield from execute_svf(dut, jtag=jtag, svf_filename="idcode.svf")
 106
 107     dut._log.info("IDCODE test completed")
 108
 109 @cocotb.test()
 110 def idcode_run(dut):
 111     dut._log.info("Running IDCODE through test; cpu running...")
 112
 113     clk_period = 100 # 10MHz
 114     tck_period = 300 # 3MHz
 115
 116     yield from setup_sim(dut, clk_period=clk_period, run=True)
 117     jtag = yield from setup_jtag(dut, tck_period = tck_period)
 118
 119     yield from execute_svf(dut, jtag=jtag, svf_filename="idcode.svf")
 120
 121     dut._log.info("IDCODE test completed")
 122
 123 from itertools import chain
 124
 125 import cocotb
 126 from cocotb.clock import Clock
 127 from cocotb.triggers import Timer
 128 from cocotb.utils import get_sim_steps
 129 from cocotb.binary import BinaryValue
 130
 131 from c4m.nmigen.jtag.tap import IOType
 132 from c4m.cocotb.jtag.c4m_jtag import JTAG_Master
 133 from c4m.cocotb.jtag.c4m_jtag_svfcocotb import SVF_Executor
 134
 135 from soc.config.pinouts import get_pinspecs
 136 from soc.debug.jtag import Pins
 137
 138
 139 @cocotb.test()
 140 def wishbone_basic(dut):
 141     """
 142     Test of an added Wishbone interface
 143     """
 144     clk_period = 100 # 100MHz
 145     tck_period = 3000 # 0.3MHz
 146
 147     data_in = BinaryValue()
 148     # these have to match with soc.debug.jtag.JTAG ircodes
 149     cmd_MEMADDRESS = BinaryValue("0101")    # 5
 150     cmd_MEMREAD = BinaryValue("0110")       # 6
 151     cmd_MEMREADWRITE = BinaryValue("0111")  # 7
 152
 153     info = "Running Wishbone basic test"
 154     yield from setup_sim(dut, clk_period=clk_period, run=True)
 155     master = yield from setup_jtag(dut, tck_period = tck_period)
 156
 157     # Load the memory address
 158     yield master.load_ir(cmd_MEMADDRESS)
 159     dut._log.info("Loading address")
 160
 161     data_in.binstr = "000000000000000000000000000001"
 162     dut._log.info("  input: {}".format(data_in.binstr))
 163     yield master.shift_data(data_in)
 164     dut._log.info("  output: {}".format(master.result.binstr))
 165
 166     # Do write
 167     yield master.load_ir(cmd_MEMREADWRITE)
 168     dut._log.info("Writing memory")
 169
 170     data_in.binstr = "01010101" * 8
 171     dut._log.info("  input: {}".format(data_in.binstr))
 172     yield master.shift_data(data_in)
 173     dut._log.info("  output: {}".format(master.result.binstr))
 174
 175     data_in.binstr = "10101010" * 8
 176     dut._log.info("  input: {}".format(data_in.binstr))
 177     yield master.shift_data(data_in)
 178     dut._log.info("  output: {}".format(master.result.binstr))
 179
 180     # Load the memory address
 181     yield master.load_ir(cmd_MEMADDRESS)
 182     dut._log.info("Loading address")
 183
 184     data_in.binstr = "000000000000000000000000000001"
 185     dut._log.info("  input: {}".format(data_in.binstr))
 186     yield master.shift_data(data_in)
 187     dut._log.info("  output: {}".format(master.result.binstr))
 188     assert master.result.binstr == "000000000000000000000000000000"
 189
 190     # Do read and write
 191     yield master.load_ir(cmd_MEMREADWRITE)
 192     dut._log.info("Reading and writing memory")
 193
 194     data_in.binstr = "10101010" * 4
 195     dut._log.info("  input: {}".format(data_in.binstr))
 196     yield master.shift_data(data_in)
 197     dut._log.info("  output: {}".format(master.result.binstr))
 198     assert master.result.binstr == "01010101" * 4
 199
 200     data_in.binstr = "01010101" * 4
 201     dut._log.info("  input: {}".format(data_in.binstr))
 202     yield master.shift_data(data_in)
 203     dut._log.info("  output: {}".format(master.result.binstr))
 204     assert master.result.binstr == "10101010" * 4
 205
 206     # Load the memory address
 207     yield master.load_ir(cmd_MEMADDRESS)
 208     dut._log.info("Loading address")
 209
 210     data_in.binstr = "000000000000000000000000000001"
 211     dut._log.info("  input: {}".format(data_in.binstr))
 212     yield master.shift_data(data_in)
 213     dut._log.info("  output: {}".format(master.result.binstr))
 214     #assert master.result.binstr == "000000000000000000000000000010"
 215
 216     # Do read
 217     yield master.load_ir(cmd_MEMREAD)
 218     dut._log.info("Reading memory")
 219     data_in.binstr = "00000000" * 4
 220
 221     dut._log.info("  input: {}".format(data_in.binstr))
 222     yield master.shift_data(data_in)
 223     dut._log.info("  output: {}".format(master.result.binstr))
 224     #assert master.result.binstr == "10101010" * 4
 225
 226     dut._log.info("  input: {}".format(data_in.binstr))
 227     yield master.shift_data(data_in)
 228     dut._log.info("  output: {}".format(master.result.binstr))
 229     #assert master.result.binstr == "01010101" * 4
 230
 231     # Load the memory address
 232     yield master.load_ir(cmd_MEMADDRESS) # MEMADDR
 233     dut._log.info("Loading address")
 234
 235     data_in.binstr = "0000000000000000000000000000001"
 236     dut._log.info("  input: {}".format(data_in.binstr))
 237     yield master.shift_data(data_in)
 238     dut._log.info("  output: {}".format(master.result.binstr))
 239     #assert master.result.binstr == "000000000000000000000000000010"
 240
 241     # Do read
 242     yield master.load_ir(cmd_MEMREAD) # MEMREAD
 243     dut._log.info("Reading memory")
 244     data_in.binstr = "00000000" * 4
 245
 246     dut._log.info("  input: {}".format(data_in.binstr))
 247     yield master.shift_data(data_in)
 248     dut._log.info("  output: {}".format(master.result.binstr))
 249     #assert master.result.binstr == "10101010" * 4
 250
 251     dut._log.info("  input: {}".format(data_in.binstr))
 252     yield master.shift_data(data_in)
 253     dut._log.info("  output: {}".format(master.result.binstr))
 254     #assert master.result.binstr == "01010101" * 4
 255
 256     dut._log.info("{!r}".format(wbmem))
 257
 258
 259 # demo / debug how to get boundary scan names. run "python3 test.py"
 260 if __name__ == '__main__':
 261     pinouts = get_jtag_boundary()
 262     for pin in pinouts:
 263         # example: ('eint', '2', <IOType.In: 1>, 'eint_2', 125)
 264         print (pin)