Fix pre-layout simulation with 4K SRAM blocks.
[soc-cocotb-sim.git] / ls180 / pre_pnr / Makefile
1 ifeq ($(SIM),)
2 $(error Use one of the run_*.sh scripts to run cocotb test bench)
3 endif
4
5 TOPLEVEL_LANG := verilog
6
7 # within soc repo, as submodule, this works after "make ls180"
8 # is run inside the litex/florent subdirectory
9 VERILOG_SOURCES := \
10 ../SPBlock_512W64B8W.v \
11 ../../../litex/florent/libresoc.v \
12 ../../../litex/florent/ls180.v \
13 # END VERILOG_SOURCES
14
15 MODULE := test
16
17 include $(shell cocotb-config --makefiles)/Makefile.sim
18