1 # This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
2 # This file is Copyright (c) 2019 Benjamin Herrenschmidt <benh@ozlabs.org>
7 from migen
import ClockSignal
, ResetSignal
, Signal
, Instance
, Cat
9 from litex
.soc
.interconnect
import wishbone
10 from litex
.soc
.cores
.cpu
import CPU
13 CPU_VARIANTS
= ["standard"]
18 human_name
= "Microwatt"
19 variants
= CPU_VARIANTS
22 gcc_triple
= ("powerpc64le-linux", "powerpc64le-linux-gnu", "powerpc64le-unknown-linux-gnu")
23 linker_output_format
= "elf64-powerpcle"
25 io_regions
= {0xc0000000: 0x10000000} # origin, length
29 return {"csr": 0xc0000000}
34 flags
+= "-mabi=elfv2 "
35 flags
+= "-msoft-float "
36 flags
+= "-mno-string "
37 flags
+= "-mno-multiple "
39 flags
+= "-mno-altivec "
40 flags
+= "-mlittle-endian "
41 flags
+= "-mstrict-align "
42 flags
+= "-fno-stack-protector "
43 flags
+= "-mcmodel=small "
44 flags
+= "-D__microwatt__ "
47 def __init__(self
, platform
, variant
="standard"):
48 self
.platform
= platform
49 self
.variant
= variant
51 self
.ibus
= ibus
= wishbone
.Interface(data_width
=64, adr_width
=29)
52 self
.dbus
= dbus
= wishbone
.Interface(data_width
=64, adr_width
=29)
53 self
.periph_buses
= [ibus
, dbus
]
54 self
.memory_buses
= []
56 self
.dmi_addr
= Signal(4)
57 self
.dmi_din
= Signal(64)
58 self
.dmi_dout
= Signal(64)
59 self
.dmi_wr
= Signal(1)
60 self
.dmi_ack
= Signal(1)
61 self
.dmi_req
= Signal(1)
65 self
.cpu_params
= dict(
67 i_clk
= ClockSignal(),
68 i_rst
= ResetSignal() | self
.reset
,
70 # Wishbone instruction bus
71 i_wishbone_insn_dat_r
= ibus
.dat_r
,
72 i_wishbone_insn_ack
= ibus
.ack
,
73 i_wishbone_insn_stall
= ibus
.cyc
& ~ibus
.ack
, # No burst support
75 o_wishbone_insn_adr
= Cat(Signal(3), ibus
.adr
),
76 o_wishbone_insn_dat_w
= ibus
.dat_w
,
77 o_wishbone_insn_cyc
= ibus
.cyc
,
78 o_wishbone_insn_stb
= ibus
.stb
,
79 o_wishbone_insn_sel
= ibus
.sel
,
80 o_wishbone_insn_we
= ibus
.we
,
83 i_wishbone_data_dat_r
= dbus
.dat_r
,
84 i_wishbone_data_ack
= dbus
.ack
,
85 i_wishbone_data_stall
= dbus
.cyc
& ~dbus
.ack
, # No burst support
87 o_wishbone_data_adr
= Cat(Signal(3), dbus
.adr
),
88 o_wishbone_data_dat_w
= dbus
.dat_w
,
89 o_wishbone_data_cyc
= dbus
.cyc
,
90 o_wishbone_data_stb
= dbus
.stb
,
91 o_wishbone_data_sel
= dbus
.sel
,
92 o_wishbone_data_we
= dbus
.we
,
96 i_dmi_addr
= self
.dmi_addr
,
97 i_dmi_din
= self
.dmi_din
,
98 o_dmi_dout
= self
.dmi_dout
,
99 i_dmi_req
= self
.dmi_req
,
100 i_dmi_wr
= self
.dmi_wr
,
101 o_dmi_ack
= self
.dmi_ack
,
105 self
.add_sources(platform
)
107 def set_reset_address(self
, reset_address
):
108 assert not hasattr(self
, "reset_address")
109 self
.reset_address
= reset_address
110 assert reset_address
== 0x00000000
113 def add_sources(platform
):
114 cdir
= os
.path
.dirname(__file__
)
115 platform
.add_source(os
.path
.join(cdir
, "microwatt.v"))
117 def do_finalize(self
):
118 self
.specials
+= Instance("microwatt_wrapper", **self
.cpu_params
)