Share soc.vhdl between FPGA and sim
[microwatt.git] / microwatt.core
1 CAPI=2:
2
3 name : ::microwatt:0
4
5 filesets:
6 core:
7 files:
8 - decode_types.vhdl
9 - wishbone_types.vhdl
10 - common.vhdl
11 - fetch1.vhdl
12 - fetch2.vhdl
13 - decode1.vhdl
14 - helpers.vhdl
15 - decode2.vhdl
16 - register_file.vhdl
17 - cr_file.vhdl
18 - crhelpers.vhdl
19 - ppc_fx_insns.vhdl
20 - sim_console.vhdl
21 - execute1.vhdl
22 - execute2.vhdl
23 - loadstore1.vhdl
24 - loadstore2.vhdl
25 - multiply.vhdl
26 - writeback.vhdl
27 - insn_helpers.vhdl
28 - core.vhdl
29 file_type : vhdlSource-2008
30
31 soc:
32 files:
33 - wishbone_arbiter.vhdl
34 - soc.vhdl
35 file_type : vhdlSource-2008
36
37 fpga:
38 files:
39 - fpga/pp_fifo.vhd
40 - fpga/mw_soc_memory.vhdl
41 - fpga/soc_reset.vhdl
42 - fpga/pp_soc_uart.vhd
43 - fpga/pp_utilities.vhd
44 - fpga/toplevel.vhdl
45 - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
46 file_type : vhdlSource-2008
47
48 nexys_a7:
49 files:
50 - fpga/nexys_a7.xdc : {file_type : xdc}
51 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
52
53 nexys_video:
54 files:
55 - fpga/nexys-video.xdc : {file_type : xdc}
56 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
57
58 arty_a7-35:
59 files:
60 - fpga/arty_a7-35.xdc : {file_type : xdc}
61 - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
62
63 cmod_a7-35:
64 files:
65 - fpga/cmod_a7-35.xdc : {file_type : xdc}
66 - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
67
68 targets:
69 nexys_a7:
70 default_tool: vivado
71 filesets: [core, nexys_a7, soc, fpga]
72 parameters : [memory_size, ram_init_file]
73 tools:
74 vivado: {part : xc7a100tcsg324-1}
75 toplevel : toplevel
76
77 nexys_video:
78 default_tool: vivado
79 filesets: [core, nexys_video, soc, fpga]
80 parameters : [memory_size, ram_init_file]
81 tools:
82 vivado: {part : xc7a200tsbg484-1}
83 toplevel : toplevel
84
85 arty_a7-35:
86 default_tool: vivado
87 filesets: [core, arty_a7-35, soc, fpga]
88 parameters : [memory_size, ram_init_file]
89 tools:
90 vivado: {part : xc7a35ticsg324-1L}
91 toplevel : toplevel
92
93 cmod_a7-35:
94 default_tool: vivado
95 filesets: [core, cmod_a7-35, soc, fpga]
96 parameters : [memory_size, ram_init_file, reset_low=false]
97 tools:
98 vivado: {part : xc7a35tcpg236-1}
99 toplevel : toplevel
100
101 synth:
102 filesets: [core, soc]
103 tools:
104 vivado: {pnr : none}
105 toplevel: core
106
107 parameters:
108 memory_size:
109 datatype : int
110 description : On-chip memory size (bytes)
111 paramtype : generic
112
113 ram_init_file:
114 datatype : file
115 description : Initial on-chip RAM contents
116 paramtype : generic
117
118 reset_low:
119 datatype : bool
120 description : External reset button polarity
121 paramtype : generic