microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - fetch2.vhdl
  13       - decode1.vhdl
  14       - helpers.vhdl
  15       - decode2.vhdl
  16       - register_file.vhdl
  17       - cr_file.vhdl
  18       - crhelpers.vhdl
  19       - ppc_fx_insns.vhdl
  20       - sim_console.vhdl
  21       - execute1.vhdl
  22       - execute2.vhdl
  23       - loadstore1.vhdl
  24       - loadstore2.vhdl
  25       - multiply.vhdl
  26       - divider.vhdl
  27       - writeback.vhdl
  28       - insn_helpers.vhdl
  29       - core.vhdl
  30       - icache.vhdl
  31       - core_debug.vhdl
  32     file_type : vhdlSource-2008
  33
  34   soc:
  35     files:
  36       - wishbone_arbiter.vhdl
  37       - wishbone_debug_master.vhdl
  38       - soc.vhdl
  39     file_type : vhdlSource-2008
  40
  41   fpga:
  42     files:
  43       - fpga/pp_fifo.vhd
  44       - fpga/mw_soc_memory.vhdl
  45       - fpga/soc_reset.vhdl
  46       - fpga/pp_soc_uart.vhd
  47       - fpga/pp_utilities.vhd
  48       - fpga/toplevel.vhdl
  49       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  50     file_type : vhdlSource-2008
  51
  52   debug_xilinx:
  53     files:
  54       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  55
  56   debug_dummy:
  57     files:
  58       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  59
  60   nexys_a7:
  61     files:
  62       - fpga/nexys_a7.xdc : {file_type : xdc}
  63       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  64
  65   nexys_video:
  66     files:
  67       - fpga/nexys-video.xdc : {file_type : xdc}
  68       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  69
  70   arty_a7:
  71     files:
  72       - fpga/arty_a7.xdc : {file_type : xdc}
  73       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  74
  75   cmod_a7-35:
  76     files:
  77       - fpga/cmod_a7-35.xdc : {file_type : xdc}
  78       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
  79
  80 targets:
  81   nexys_a7:
  82     default_tool: vivado
  83     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
  84     parameters :
  85       - memory_size
  86       - ram_init_file
  87       - clk_input
  88       - clk_frequency
  89     tools:
  90       vivado: {part : xc7a100tcsg324-1}
  91     toplevel : toplevel
  92
  93   nexys_video:
  94     default_tool: vivado
  95     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
  96     parameters :
  97       - memory_size
  98       - ram_init_file
  99       - clk_input
 100       - clk_frequency
 101     tools:
 102       vivado: {part : xc7a200tsbg484-1}
 103     toplevel : toplevel
 104
 105   arty_a7-35:
 106     default_tool: vivado
 107     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 108     parameters :
 109       - memory_size
 110       - ram_init_file
 111       - clk_input
 112       - clk_frequency
 113     tools:
 114       vivado: {part : xc7a35ticsg324-1L}
 115     toplevel : toplevel
 116
 117   arty_a7-100:
 118     default_tool: vivado
 119     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
 120     parameters :
 121       - memory_size
 122       - ram_init_file
 123       - clk_input
 124       - clk_frequency
 125     tools:
 126       vivado: {part : xc7a100ticsg324-1L}
 127     toplevel : toplevel
 128
 129   cmod_a7-35:
 130     default_tool: vivado
 131     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
 132     parameters :
 133       - memory_size
 134       - ram_init_file
 135       - reset_low=false
 136       - clk_input=12000000
 137     tools:
 138       vivado: {part : xc7a35tcpg236-1}
 139     toplevel : toplevel
 140
 141   synth:
 142     filesets: [core, soc]
 143     tools:
 144       vivado: {pnr : none}
 145     toplevel: core
 146
 147 parameters:
 148   memory_size:
 149     datatype    : int
 150     description : On-chip memory size (bytes)
 151     paramtype   : generic
 152
 153   ram_init_file:
 154     datatype    : file
 155     description : Initial on-chip RAM contents
 156     paramtype   : generic
 157
 158   reset_low:
 159     datatype    : bool
 160     description : External reset button polarity
 161     paramtype   : generic
 162
 163   clk_input:
 164     datatype    : int
 165     description : Clock input frequency in HZ (for top-generic based boards)
 166     paramtype   : generic
 167     default     : 100000000
 168
 169   clk_frequency:
 170     datatype    : int
 171     description : Generated system clock frequency in HZ (for top-generic based boards)
 172     paramtype   : generic
 173     default     : 50000000